isa.cc revision 11150:a8a64cca231b
1/* 2 * Copyright (c) 2010-2015 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "dev/arm/generic_timer.hh" 49#include "params/ArmISA.hh" 50#include "sim/faults.hh" 51#include "sim/stat_control.hh" 52#include "sim/system.hh" 53 54namespace ArmISA 55{ 56 57 58/** 59 * Some registers aliase with others, and therefore need to be translated. 60 * For each entry: 61 * The first value is the misc register that is to be looked up 62 * the second value is the lower part of the translation 63 * the third the upper part 64 */ 65const struct ISA::MiscRegInitializerEntry 66 ISA::MiscRegSwitch[miscRegTranslateMax] = { 67 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 68 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 69 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 70 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 71 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 72 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 73 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 74 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 75 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 76 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 77 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 78 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 79 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 80 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 81 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 82 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 83 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 84 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 85 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 86 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 87 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 88 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 89 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 90 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 91 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 92 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 93 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 94 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 95 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 96 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 97 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 98 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 99 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 100 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 101 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 102 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 103 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 104 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 105 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 106 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 107 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 108 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 109 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 110 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 111 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 112 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 113 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 114 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 115 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 116 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 117 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 118 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 119 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 120 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 121 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 122 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 123 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 124}; 125 126 127ISA::ISA(Params *p) 128 : SimObject(p), 129 system(NULL), 130 pmu(p->pmu), 131 lookUpMiscReg(NUM_MISCREGS, {0,0}) 132{ 133 SCTLR sctlr; 134 sctlr = 0; 135 miscRegs[MISCREG_SCTLR_RST] = sctlr; 136 137 // Hook up a dummy device if we haven't been configured with a 138 // real PMU. By using a dummy device, we don't need to check that 139 // the PMU exist every time we try to access a PMU register. 140 if (!pmu) 141 pmu = &dummyDevice; 142 143 // Give all ISA devices a pointer to this ISA 144 pmu->setISA(this); 145 146 system = dynamic_cast<ArmSystem *>(p->system); 147 148 // Cache system-level properties 149 if (FullSystem && system) { 150 haveSecurity = system->haveSecurity(); 151 haveLPAE = system->haveLPAE(); 152 haveVirtualization = system->haveVirtualization(); 153 haveLargeAsid64 = system->haveLargeAsid64(); 154 physAddrRange64 = system->physAddrRange64(); 155 } else { 156 haveSecurity = haveLPAE = haveVirtualization = false; 157 haveLargeAsid64 = false; 158 physAddrRange64 = 32; // dummy value 159 } 160 161 /** Fill in the miscReg translation table */ 162 for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 163 struct MiscRegLUTEntry new_entry; 164 165 uint32_t select = MiscRegSwitch[i].index; 166 new_entry = MiscRegSwitch[i].entry; 167 168 lookUpMiscReg[select] = new_entry; 169 } 170 171 preUnflattenMiscReg(); 172 173 clear(); 174} 175 176const ArmISAParams * 177ISA::params() const 178{ 179 return dynamic_cast<const Params *>(_params); 180} 181 182void 183ISA::clear() 184{ 185 const Params *p(params()); 186 187 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 188 memset(miscRegs, 0, sizeof(miscRegs)); 189 190 // Initialize configurable default values 191 miscRegs[MISCREG_MIDR] = p->midr; 192 miscRegs[MISCREG_MIDR_EL1] = p->midr; 193 miscRegs[MISCREG_VPIDR] = p->midr; 194 195 if (FullSystem && system->highestELIs64()) { 196 // Initialize AArch64 state 197 clear64(p); 198 return; 199 } 200 201 // Initialize AArch32 state... 202 203 CPSR cpsr = 0; 204 cpsr.mode = MODE_USER; 205 miscRegs[MISCREG_CPSR] = cpsr; 206 updateRegMap(cpsr); 207 208 SCTLR sctlr = 0; 209 sctlr.te = (bool) sctlr_rst.te; 210 sctlr.nmfi = (bool) sctlr_rst.nmfi; 211 sctlr.v = (bool) sctlr_rst.v; 212 sctlr.u = 1; 213 sctlr.xp = 1; 214 sctlr.rao2 = 1; 215 sctlr.rao3 = 1; 216 sctlr.rao4 = 0xf; // SCTLR[6:3] 217 sctlr.uci = 1; 218 sctlr.dze = 1; 219 miscRegs[MISCREG_SCTLR_NS] = sctlr; 220 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 221 miscRegs[MISCREG_HCPTR] = 0; 222 223 // Start with an event in the mailbox 224 miscRegs[MISCREG_SEV_MAILBOX] = 1; 225 226 // Separate Instruction and Data TLBs 227 miscRegs[MISCREG_TLBTR] = 1; 228 229 MVFR0 mvfr0 = 0; 230 mvfr0.advSimdRegisters = 2; 231 mvfr0.singlePrecision = 2; 232 mvfr0.doublePrecision = 2; 233 mvfr0.vfpExceptionTrapping = 0; 234 mvfr0.divide = 1; 235 mvfr0.squareRoot = 1; 236 mvfr0.shortVectors = 1; 237 mvfr0.roundingModes = 1; 238 miscRegs[MISCREG_MVFR0] = mvfr0; 239 240 MVFR1 mvfr1 = 0; 241 mvfr1.flushToZero = 1; 242 mvfr1.defaultNaN = 1; 243 mvfr1.advSimdLoadStore = 1; 244 mvfr1.advSimdInteger = 1; 245 mvfr1.advSimdSinglePrecision = 1; 246 mvfr1.advSimdHalfPrecision = 1; 247 mvfr1.vfpHalfPrecision = 1; 248 miscRegs[MISCREG_MVFR1] = mvfr1; 249 250 // Reset values of PRRR and NMRR are implementation dependent 251 252 // @todo: PRRR and NMRR in secure state? 253 miscRegs[MISCREG_PRRR_NS] = 254 (1 << 19) | // 19 255 (0 << 18) | // 18 256 (0 << 17) | // 17 257 (1 << 16) | // 16 258 (2 << 14) | // 15:14 259 (0 << 12) | // 13:12 260 (2 << 10) | // 11:10 261 (2 << 8) | // 9:8 262 (2 << 6) | // 7:6 263 (2 << 4) | // 5:4 264 (1 << 2) | // 3:2 265 0; // 1:0 266 miscRegs[MISCREG_NMRR_NS] = 267 (1 << 30) | // 31:30 268 (0 << 26) | // 27:26 269 (0 << 24) | // 25:24 270 (3 << 22) | // 23:22 271 (2 << 20) | // 21:20 272 (0 << 18) | // 19:18 273 (0 << 16) | // 17:16 274 (1 << 14) | // 15:14 275 (0 << 12) | // 13:12 276 (2 << 10) | // 11:10 277 (0 << 8) | // 9:8 278 (3 << 6) | // 7:6 279 (2 << 4) | // 5:4 280 (0 << 2) | // 3:2 281 0; // 1:0 282 283 miscRegs[MISCREG_CPACR] = 0; 284 285 286 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 287 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 288 289 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 290 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 291 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 292 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 293 294 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 295 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 296 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 297 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 298 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 299 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 300 301 miscRegs[MISCREG_FPSID] = p->fpsid; 302 303 if (haveLPAE) { 304 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 305 ttbcr.eae = 0; 306 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 307 // Enforce consistency with system-level settings 308 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 309 } 310 311 if (haveSecurity) { 312 miscRegs[MISCREG_SCTLR_S] = sctlr; 313 miscRegs[MISCREG_SCR] = 0; 314 miscRegs[MISCREG_VBAR_S] = 0; 315 } else { 316 // we're always non-secure 317 miscRegs[MISCREG_SCR] = 1; 318 } 319 320 //XXX We need to initialize the rest of the state. 321} 322 323void 324ISA::clear64(const ArmISAParams *p) 325{ 326 CPSR cpsr = 0; 327 Addr rvbar = system->resetAddr64(); 328 switch (system->highestEL()) { 329 // Set initial EL to highest implemented EL using associated stack 330 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 331 // value 332 case EL3: 333 cpsr.mode = MODE_EL3H; 334 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 335 break; 336 case EL2: 337 cpsr.mode = MODE_EL2H; 338 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 339 break; 340 case EL1: 341 cpsr.mode = MODE_EL1H; 342 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 343 break; 344 default: 345 panic("Invalid highest implemented exception level"); 346 break; 347 } 348 349 // Initialize rest of CPSR 350 cpsr.daif = 0xf; // Mask all interrupts 351 cpsr.ss = 0; 352 cpsr.il = 0; 353 miscRegs[MISCREG_CPSR] = cpsr; 354 updateRegMap(cpsr); 355 356 // Initialize other control registers 357 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 358 if (haveSecurity) { 359 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 360 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 361 // @todo: uncomment this to enable Virtualization 362 // } else if (haveVirtualization) { 363 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 364 } else { 365 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 366 // Always non-secure 367 miscRegs[MISCREG_SCR_EL3] = 1; 368 } 369 370 // Initialize configurable id registers 371 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 372 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 373 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 374 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 375 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 376 377 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 378 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 379 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 380 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 381 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 382 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 383 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 384 385 miscRegs[MISCREG_ID_DFR0_EL1] = 386 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 387 388 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 389 390 // Enforce consistency with system-level settings... 391 392 // EL3 393 // (no AArch32/64 interprocessing support for now) 394 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 395 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 396 haveSecurity ? 0x1 : 0x0); 397 // EL2 398 // (no AArch32/64 interprocessing support for now) 399 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 400 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 401 haveVirtualization ? 0x1 : 0x0); 402 // Large ASID support 403 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 404 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 405 haveLargeAsid64 ? 0x2 : 0x0); 406 // Physical address size 407 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 408 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 409 encodePhysAddrRange64(physAddrRange64)); 410} 411 412MiscReg 413ISA::readMiscRegNoEffect(int misc_reg) const 414{ 415 assert(misc_reg < NumMiscRegs); 416 417 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 418 // registers are left unchanged 419 MiscReg val; 420 421 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 422 || flat_idx == MISCREG_SCTLR_EL1) { 423 if (flat_idx == MISCREG_SPSR) 424 flat_idx = flattenMiscIndex(MISCREG_SPSR); 425 if (flat_idx == MISCREG_SCTLR_EL1) 426 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 427 val = miscRegs[flat_idx]; 428 } else 429 if (lookUpMiscReg[flat_idx].upper > 0) 430 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 431 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 432 else 433 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 434 435 return val; 436} 437 438 439MiscReg 440ISA::readMiscReg(int misc_reg, ThreadContext *tc) 441{ 442 CPSR cpsr = 0; 443 PCState pc = 0; 444 SCR scr = 0; 445 446 if (misc_reg == MISCREG_CPSR) { 447 cpsr = miscRegs[misc_reg]; 448 pc = tc->pcState(); 449 cpsr.j = pc.jazelle() ? 1 : 0; 450 cpsr.t = pc.thumb() ? 1 : 0; 451 return cpsr; 452 } 453 454#ifndef NDEBUG 455 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 456 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 457 warn("Unimplemented system register %s read.\n", 458 miscRegName[misc_reg]); 459 else 460 panic("Unimplemented system register %s read.\n", 461 miscRegName[misc_reg]); 462 } 463#endif 464 465 switch (unflattenMiscReg(misc_reg)) { 466 case MISCREG_HCR: 467 { 468 if (!haveVirtualization) 469 return 0; 470 else 471 return readMiscRegNoEffect(MISCREG_HCR); 472 } 473 case MISCREG_CPACR: 474 { 475 const uint32_t ones = (uint32_t)(-1); 476 CPACR cpacrMask = 0; 477 // Only cp10, cp11, and ase are implemented, nothing else should 478 // be readable? (straight copy from the write code) 479 cpacrMask.cp10 = ones; 480 cpacrMask.cp11 = ones; 481 cpacrMask.asedis = ones; 482 483 // Security Extensions may limit the readability of CPACR 484 if (haveSecurity) { 485 scr = readMiscRegNoEffect(MISCREG_SCR); 486 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 487 if (scr.ns && (cpsr.mode != MODE_MON)) { 488 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 489 // NB: Skipping the full loop, here 490 if (!nsacr.cp10) cpacrMask.cp10 = 0; 491 if (!nsacr.cp11) cpacrMask.cp11 = 0; 492 } 493 } 494 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 495 val &= cpacrMask; 496 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 497 miscRegName[misc_reg], val); 498 return val; 499 } 500 case MISCREG_MPIDR: 501 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 502 scr = readMiscRegNoEffect(MISCREG_SCR); 503 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 504 return getMPIDR(system, tc); 505 } else { 506 return readMiscReg(MISCREG_VMPIDR, tc); 507 } 508 break; 509 case MISCREG_MPIDR_EL1: 510 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 511 return getMPIDR(system, tc) & 0xffffffff; 512 case MISCREG_VMPIDR: 513 // top bit defined as RES1 514 return readMiscRegNoEffect(misc_reg) | 0x80000000; 515 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 516 case MISCREG_REVIDR: // not implemented, so alias MIDR 517 case MISCREG_MIDR: 518 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 519 scr = readMiscRegNoEffect(MISCREG_SCR); 520 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 521 return readMiscRegNoEffect(misc_reg); 522 } else { 523 return readMiscRegNoEffect(MISCREG_VPIDR); 524 } 525 break; 526 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 527 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 528 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 529 case MISCREG_AIDR: // AUX ID set to 0 530 case MISCREG_TCMTR: // No TCM's 531 return 0; 532 533 case MISCREG_CLIDR: 534 warn_once("The clidr register always reports 0 caches.\n"); 535 warn_once("clidr LoUIS field of 0b001 to match current " 536 "ARM implementations.\n"); 537 return 0x00200000; 538 case MISCREG_CCSIDR: 539 warn_once("The ccsidr register isn't implemented and " 540 "always reads as 0.\n"); 541 break; 542 case MISCREG_CTR: 543 { 544 //all caches have the same line size in gem5 545 //4 byte words in ARM 546 unsigned lineSizeWords = 547 tc->getSystemPtr()->cacheLineSize() / 4; 548 unsigned log2LineSizeWords = 0; 549 550 while (lineSizeWords >>= 1) { 551 ++log2LineSizeWords; 552 } 553 554 CTR ctr = 0; 555 //log2 of minimun i-cache line size (words) 556 ctr.iCacheLineSize = log2LineSizeWords; 557 //b11 - gem5 uses pipt 558 ctr.l1IndexPolicy = 0x3; 559 //log2 of minimum d-cache line size (words) 560 ctr.dCacheLineSize = log2LineSizeWords; 561 //log2 of max reservation size (words) 562 ctr.erg = log2LineSizeWords; 563 //log2 of max writeback size (words) 564 ctr.cwg = log2LineSizeWords; 565 //b100 - gem5 format is ARMv7 566 ctr.format = 0x4; 567 568 return ctr; 569 } 570 case MISCREG_ACTLR: 571 warn("Not doing anything for miscreg ACTLR\n"); 572 break; 573 574 case MISCREG_PMXEVTYPER_PMCCFILTR: 575 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 576 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 577 case MISCREG_PMCR ... MISCREG_PMOVSSET: 578 return pmu->readMiscReg(misc_reg); 579 580 case MISCREG_CPSR_Q: 581 panic("shouldn't be reading this register seperately\n"); 582 case MISCREG_FPSCR_QC: 583 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 584 case MISCREG_FPSCR_EXC: 585 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 586 case MISCREG_FPSR: 587 { 588 const uint32_t ones = (uint32_t)(-1); 589 FPSCR fpscrMask = 0; 590 fpscrMask.ioc = ones; 591 fpscrMask.dzc = ones; 592 fpscrMask.ofc = ones; 593 fpscrMask.ufc = ones; 594 fpscrMask.ixc = ones; 595 fpscrMask.idc = ones; 596 fpscrMask.qc = ones; 597 fpscrMask.v = ones; 598 fpscrMask.c = ones; 599 fpscrMask.z = ones; 600 fpscrMask.n = ones; 601 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 602 } 603 case MISCREG_FPCR: 604 { 605 const uint32_t ones = (uint32_t)(-1); 606 FPSCR fpscrMask = 0; 607 fpscrMask.ioe = ones; 608 fpscrMask.dze = ones; 609 fpscrMask.ofe = ones; 610 fpscrMask.ufe = ones; 611 fpscrMask.ixe = ones; 612 fpscrMask.ide = ones; 613 fpscrMask.len = ones; 614 fpscrMask.stride = ones; 615 fpscrMask.rMode = ones; 616 fpscrMask.fz = ones; 617 fpscrMask.dn = ones; 618 fpscrMask.ahp = ones; 619 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 620 } 621 case MISCREG_NZCV: 622 { 623 CPSR cpsr = 0; 624 cpsr.nz = tc->readCCReg(CCREG_NZ); 625 cpsr.c = tc->readCCReg(CCREG_C); 626 cpsr.v = tc->readCCReg(CCREG_V); 627 return cpsr; 628 } 629 case MISCREG_DAIF: 630 { 631 CPSR cpsr = 0; 632 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 633 return cpsr; 634 } 635 case MISCREG_SP_EL0: 636 { 637 return tc->readIntReg(INTREG_SP0); 638 } 639 case MISCREG_SP_EL1: 640 { 641 return tc->readIntReg(INTREG_SP1); 642 } 643 case MISCREG_SP_EL2: 644 { 645 return tc->readIntReg(INTREG_SP2); 646 } 647 case MISCREG_SPSEL: 648 { 649 return miscRegs[MISCREG_CPSR] & 0x1; 650 } 651 case MISCREG_CURRENTEL: 652 { 653 return miscRegs[MISCREG_CPSR] & 0xc; 654 } 655 case MISCREG_L2CTLR: 656 { 657 // mostly unimplemented, just set NumCPUs field from sim and return 658 L2CTLR l2ctlr = 0; 659 // b00:1CPU to b11:4CPUs 660 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 661 return l2ctlr; 662 } 663 case MISCREG_DBGDIDR: 664 /* For now just implement the version number. 665 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 666 */ 667 return 0x5 << 16; 668 case MISCREG_DBGDSCRint: 669 return 0; 670 case MISCREG_ISR: 671 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 672 readMiscRegNoEffect(MISCREG_HCR), 673 readMiscRegNoEffect(MISCREG_CPSR), 674 readMiscRegNoEffect(MISCREG_SCR)); 675 case MISCREG_ISR_EL1: 676 return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 677 readMiscRegNoEffect(MISCREG_HCR_EL2), 678 readMiscRegNoEffect(MISCREG_CPSR), 679 readMiscRegNoEffect(MISCREG_SCR_EL3)); 680 case MISCREG_DCZID_EL0: 681 return 0x04; // DC ZVA clear 64-byte chunks 682 case MISCREG_HCPTR: 683 { 684 MiscReg val = readMiscRegNoEffect(misc_reg); 685 // The trap bit associated with CP14 is defined as RAZ 686 val &= ~(1 << 14); 687 // If a CP bit in NSACR is 0 then the corresponding bit in 688 // HCPTR is RAO/WI 689 bool secure_lookup = haveSecurity && 690 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 691 readMiscRegNoEffect(MISCREG_CPSR)); 692 if (!secure_lookup) { 693 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 694 val |= (mask ^ 0x7FFF) & 0xBFFF; 695 } 696 // Set the bits for unimplemented coprocessors to RAO/WI 697 val |= 0x33FF; 698 return (val); 699 } 700 case MISCREG_HDFAR: // alias for secure DFAR 701 return readMiscRegNoEffect(MISCREG_DFAR_S); 702 case MISCREG_HIFAR: // alias for secure IFAR 703 return readMiscRegNoEffect(MISCREG_IFAR_S); 704 case MISCREG_HVBAR: // bottom bits reserved 705 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 706 case MISCREG_SCTLR: // Some bits hardwired 707 // The FI field (bit 21) is common between S/NS versions of the register 708 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 709 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 710 case MISCREG_SCTLR_EL1: 711 // The FI field (bit 21) is common between S/NS versions of the register 712 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 713 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 714 case MISCREG_SCTLR_EL3: 715 // The FI field (bit 21) is common between S/NS versions of the register 716 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 717 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 718 case MISCREG_HSCTLR: // FI comes from SCTLR 719 { 720 uint32_t mask = 1 << 27; 721 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 722 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 723 } 724 case MISCREG_SCR: 725 { 726 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 727 if (cpsr.width) { 728 return readMiscRegNoEffect(MISCREG_SCR); 729 } else { 730 return readMiscRegNoEffect(MISCREG_SCR_EL3); 731 } 732 } 733 734 // Generic Timer registers 735 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 736 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 737 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 738 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 739 return getGenericTimer(tc).readMiscReg(misc_reg); 740 741 default: 742 break; 743 744 } 745 return readMiscRegNoEffect(misc_reg); 746} 747 748void 749ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 750{ 751 assert(misc_reg < NumMiscRegs); 752 753 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 754 // registers are left unchanged 755 756 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 757 758 if (flat_idx2 > 0) { 759 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 760 miscRegs[flat_idx2] = bits(val, 63, 32); 761 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 762 misc_reg, flat_idx, flat_idx2, val); 763 } else { 764 if (flat_idx == MISCREG_SPSR) 765 flat_idx = flattenMiscIndex(MISCREG_SPSR); 766 else if (flat_idx == MISCREG_SCTLR_EL1) 767 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 768 else 769 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 770 lookUpMiscReg[flat_idx].lower : flat_idx; 771 miscRegs[flat_idx] = val; 772 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 773 misc_reg, flat_idx, val); 774 } 775} 776 777void 778ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 779{ 780 781 MiscReg newVal = val; 782 int x; 783 bool secure_lookup; 784 bool hyp; 785 System *sys; 786 ThreadContext *oc; 787 uint8_t target_el; 788 uint16_t asid; 789 SCR scr; 790 791 if (misc_reg == MISCREG_CPSR) { 792 updateRegMap(val); 793 794 795 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 796 int old_mode = old_cpsr.mode; 797 CPSR cpsr = val; 798 if (old_mode != cpsr.mode) { 799 tc->getITBPtr()->invalidateMiscReg(); 800 tc->getDTBPtr()->invalidateMiscReg(); 801 } 802 803 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 804 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 805 PCState pc = tc->pcState(); 806 pc.nextThumb(cpsr.t); 807 pc.nextJazelle(cpsr.j); 808 809 // Follow slightly different semantics if a CheckerCPU object 810 // is connected 811 CheckerCPU *checker = tc->getCheckerCpuPtr(); 812 if (checker) { 813 tc->pcStateNoRecord(pc); 814 } else { 815 tc->pcState(pc); 816 } 817 } else { 818#ifndef NDEBUG 819 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 820 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 821 warn("Unimplemented system register %s write with %#x.\n", 822 miscRegName[misc_reg], val); 823 else 824 panic("Unimplemented system register %s write with %#x.\n", 825 miscRegName[misc_reg], val); 826 } 827#endif 828 switch (unflattenMiscReg(misc_reg)) { 829 case MISCREG_CPACR: 830 { 831 832 const uint32_t ones = (uint32_t)(-1); 833 CPACR cpacrMask = 0; 834 // Only cp10, cp11, and ase are implemented, nothing else should 835 // be writable 836 cpacrMask.cp10 = ones; 837 cpacrMask.cp11 = ones; 838 cpacrMask.asedis = ones; 839 840 // Security Extensions may limit the writability of CPACR 841 if (haveSecurity) { 842 scr = readMiscRegNoEffect(MISCREG_SCR); 843 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 844 if (scr.ns && (cpsr.mode != MODE_MON)) { 845 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 846 // NB: Skipping the full loop, here 847 if (!nsacr.cp10) cpacrMask.cp10 = 0; 848 if (!nsacr.cp11) cpacrMask.cp11 = 0; 849 } 850 } 851 852 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 853 newVal &= cpacrMask; 854 newVal |= old_val & ~cpacrMask; 855 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 856 miscRegName[misc_reg], newVal); 857 } 858 break; 859 case MISCREG_CPACR_EL1: 860 { 861 const uint32_t ones = (uint32_t)(-1); 862 CPACR cpacrMask = 0; 863 cpacrMask.tta = ones; 864 cpacrMask.fpen = ones; 865 newVal &= cpacrMask; 866 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 867 miscRegName[misc_reg], newVal); 868 } 869 break; 870 case MISCREG_CPTR_EL2: 871 { 872 const uint32_t ones = (uint32_t)(-1); 873 CPTR cptrMask = 0; 874 cptrMask.tcpac = ones; 875 cptrMask.tta = ones; 876 cptrMask.tfp = ones; 877 newVal &= cptrMask; 878 cptrMask = 0; 879 cptrMask.res1_13_12_el2 = ones; 880 cptrMask.res1_9_0_el2 = ones; 881 newVal |= cptrMask; 882 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 883 miscRegName[misc_reg], newVal); 884 } 885 break; 886 case MISCREG_CPTR_EL3: 887 { 888 const uint32_t ones = (uint32_t)(-1); 889 CPTR cptrMask = 0; 890 cptrMask.tcpac = ones; 891 cptrMask.tta = ones; 892 cptrMask.tfp = ones; 893 newVal &= cptrMask; 894 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 895 miscRegName[misc_reg], newVal); 896 } 897 break; 898 case MISCREG_CSSELR: 899 warn_once("The csselr register isn't implemented.\n"); 900 return; 901 902 case MISCREG_DC_ZVA_Xt: 903 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 904 return; 905 906 case MISCREG_FPSCR: 907 { 908 const uint32_t ones = (uint32_t)(-1); 909 FPSCR fpscrMask = 0; 910 fpscrMask.ioc = ones; 911 fpscrMask.dzc = ones; 912 fpscrMask.ofc = ones; 913 fpscrMask.ufc = ones; 914 fpscrMask.ixc = ones; 915 fpscrMask.idc = ones; 916 fpscrMask.ioe = ones; 917 fpscrMask.dze = ones; 918 fpscrMask.ofe = ones; 919 fpscrMask.ufe = ones; 920 fpscrMask.ixe = ones; 921 fpscrMask.ide = ones; 922 fpscrMask.len = ones; 923 fpscrMask.stride = ones; 924 fpscrMask.rMode = ones; 925 fpscrMask.fz = ones; 926 fpscrMask.dn = ones; 927 fpscrMask.ahp = ones; 928 fpscrMask.qc = ones; 929 fpscrMask.v = ones; 930 fpscrMask.c = ones; 931 fpscrMask.z = ones; 932 fpscrMask.n = ones; 933 newVal = (newVal & (uint32_t)fpscrMask) | 934 (readMiscRegNoEffect(MISCREG_FPSCR) & 935 ~(uint32_t)fpscrMask); 936 tc->getDecoderPtr()->setContext(newVal); 937 } 938 break; 939 case MISCREG_FPSR: 940 { 941 const uint32_t ones = (uint32_t)(-1); 942 FPSCR fpscrMask = 0; 943 fpscrMask.ioc = ones; 944 fpscrMask.dzc = ones; 945 fpscrMask.ofc = ones; 946 fpscrMask.ufc = ones; 947 fpscrMask.ixc = ones; 948 fpscrMask.idc = ones; 949 fpscrMask.qc = ones; 950 fpscrMask.v = ones; 951 fpscrMask.c = ones; 952 fpscrMask.z = ones; 953 fpscrMask.n = ones; 954 newVal = (newVal & (uint32_t)fpscrMask) | 955 (readMiscRegNoEffect(MISCREG_FPSCR) & 956 ~(uint32_t)fpscrMask); 957 misc_reg = MISCREG_FPSCR; 958 } 959 break; 960 case MISCREG_FPCR: 961 { 962 const uint32_t ones = (uint32_t)(-1); 963 FPSCR fpscrMask = 0; 964 fpscrMask.ioe = ones; 965 fpscrMask.dze = ones; 966 fpscrMask.ofe = ones; 967 fpscrMask.ufe = ones; 968 fpscrMask.ixe = ones; 969 fpscrMask.ide = ones; 970 fpscrMask.len = ones; 971 fpscrMask.stride = ones; 972 fpscrMask.rMode = ones; 973 fpscrMask.fz = ones; 974 fpscrMask.dn = ones; 975 fpscrMask.ahp = ones; 976 newVal = (newVal & (uint32_t)fpscrMask) | 977 (readMiscRegNoEffect(MISCREG_FPSCR) & 978 ~(uint32_t)fpscrMask); 979 misc_reg = MISCREG_FPSCR; 980 } 981 break; 982 case MISCREG_CPSR_Q: 983 { 984 assert(!(newVal & ~CpsrMaskQ)); 985 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 986 misc_reg = MISCREG_CPSR; 987 } 988 break; 989 case MISCREG_FPSCR_QC: 990 { 991 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 992 (newVal & FpscrQcMask); 993 misc_reg = MISCREG_FPSCR; 994 } 995 break; 996 case MISCREG_FPSCR_EXC: 997 { 998 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 999 (newVal & FpscrExcMask); 1000 misc_reg = MISCREG_FPSCR; 1001 } 1002 break; 1003 case MISCREG_FPEXC: 1004 { 1005 // vfpv3 architecture, section B.6.1 of DDI04068 1006 // bit 29 - valid only if fpexc[31] is 0 1007 const uint32_t fpexcMask = 0x60000000; 1008 newVal = (newVal & fpexcMask) | 1009 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1010 } 1011 break; 1012 case MISCREG_HCR: 1013 { 1014 if (!haveVirtualization) 1015 return; 1016 } 1017 break; 1018 case MISCREG_IFSR: 1019 { 1020 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1021 const uint32_t ifsrMask = 1022 mask(31, 13) | mask(11, 11) | mask(8, 6); 1023 newVal = newVal & ~ifsrMask; 1024 } 1025 break; 1026 case MISCREG_DFSR: 1027 { 1028 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1029 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1030 newVal = newVal & ~dfsrMask; 1031 } 1032 break; 1033 case MISCREG_AMAIR0: 1034 case MISCREG_AMAIR1: 1035 { 1036 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1037 // Valid only with LPAE 1038 if (!haveLPAE) 1039 return; 1040 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1041 } 1042 break; 1043 case MISCREG_SCR: 1044 tc->getITBPtr()->invalidateMiscReg(); 1045 tc->getDTBPtr()->invalidateMiscReg(); 1046 break; 1047 case MISCREG_SCTLR: 1048 { 1049 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1050 MiscRegIndex sctlr_idx; 1051 scr = readMiscRegNoEffect(MISCREG_SCR); 1052 if (haveSecurity && !scr.ns) { 1053 sctlr_idx = MISCREG_SCTLR_S; 1054 } else { 1055 sctlr_idx = MISCREG_SCTLR_NS; 1056 // The FI field (bit 21) is common between S/NS versions 1057 // of the register, we store this in the secure copy of 1058 // the reg 1059 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1060 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1061 } 1062 SCTLR sctlr = miscRegs[sctlr_idx]; 1063 SCTLR new_sctlr = newVal; 1064 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1065 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1066 tc->getITBPtr()->invalidateMiscReg(); 1067 tc->getDTBPtr()->invalidateMiscReg(); 1068 } 1069 case MISCREG_MIDR: 1070 case MISCREG_ID_PFR0: 1071 case MISCREG_ID_PFR1: 1072 case MISCREG_ID_DFR0: 1073 case MISCREG_ID_MMFR0: 1074 case MISCREG_ID_MMFR1: 1075 case MISCREG_ID_MMFR2: 1076 case MISCREG_ID_MMFR3: 1077 case MISCREG_ID_ISAR0: 1078 case MISCREG_ID_ISAR1: 1079 case MISCREG_ID_ISAR2: 1080 case MISCREG_ID_ISAR3: 1081 case MISCREG_ID_ISAR4: 1082 case MISCREG_ID_ISAR5: 1083 1084 case MISCREG_MPIDR: 1085 case MISCREG_FPSID: 1086 case MISCREG_TLBTR: 1087 case MISCREG_MVFR0: 1088 case MISCREG_MVFR1: 1089 1090 case MISCREG_ID_AA64AFR0_EL1: 1091 case MISCREG_ID_AA64AFR1_EL1: 1092 case MISCREG_ID_AA64DFR0_EL1: 1093 case MISCREG_ID_AA64DFR1_EL1: 1094 case MISCREG_ID_AA64ISAR0_EL1: 1095 case MISCREG_ID_AA64ISAR1_EL1: 1096 case MISCREG_ID_AA64MMFR0_EL1: 1097 case MISCREG_ID_AA64MMFR1_EL1: 1098 case MISCREG_ID_AA64PFR0_EL1: 1099 case MISCREG_ID_AA64PFR1_EL1: 1100 // ID registers are constants. 1101 return; 1102 1103 // TLBI all entries, EL0&1 inner sharable (ignored) 1104 case MISCREG_TLBIALLIS: 1105 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1106 assert32(tc); 1107 target_el = 1; // el 0 and 1 are handled together 1108 scr = readMiscReg(MISCREG_SCR, tc); 1109 secure_lookup = haveSecurity && !scr.ns; 1110 sys = tc->getSystemPtr(); 1111 for (x = 0; x < sys->numContexts(); x++) { 1112 oc = sys->getThreadContext(x); 1113 assert(oc->getITBPtr() && oc->getDTBPtr()); 1114 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1115 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1116 1117 // If CheckerCPU is connected, need to notify it of a flush 1118 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1119 if (checker) { 1120 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1121 target_el); 1122 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1123 target_el); 1124 } 1125 } 1126 return; 1127 // TLBI all entries, EL0&1, instruction side 1128 case MISCREG_ITLBIALL: 1129 assert32(tc); 1130 target_el = 1; // el 0 and 1 are handled together 1131 scr = readMiscReg(MISCREG_SCR, tc); 1132 secure_lookup = haveSecurity && !scr.ns; 1133 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1134 return; 1135 // TLBI all entries, EL0&1, data side 1136 case MISCREG_DTLBIALL: 1137 assert32(tc); 1138 target_el = 1; // el 0 and 1 are handled together 1139 scr = readMiscReg(MISCREG_SCR, tc); 1140 secure_lookup = haveSecurity && !scr.ns; 1141 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1142 return; 1143 // TLBI based on VA, EL0&1 inner sharable (ignored) 1144 case MISCREG_TLBIMVAIS: 1145 case MISCREG_TLBIMVA: 1146 assert32(tc); 1147 target_el = 1; // el 0 and 1 are handled together 1148 scr = readMiscReg(MISCREG_SCR, tc); 1149 secure_lookup = haveSecurity && !scr.ns; 1150 sys = tc->getSystemPtr(); 1151 for (x = 0; x < sys->numContexts(); x++) { 1152 oc = sys->getThreadContext(x); 1153 assert(oc->getITBPtr() && oc->getDTBPtr()); 1154 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1155 bits(newVal, 7,0), 1156 secure_lookup, target_el); 1157 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1158 bits(newVal, 7,0), 1159 secure_lookup, target_el); 1160 1161 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1162 if (checker) { 1163 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1164 bits(newVal, 7,0), secure_lookup, target_el); 1165 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1166 bits(newVal, 7,0), secure_lookup, target_el); 1167 } 1168 } 1169 return; 1170 // TLBI by ASID, EL0&1, inner sharable 1171 case MISCREG_TLBIASIDIS: 1172 case MISCREG_TLBIASID: 1173 assert32(tc); 1174 target_el = 1; // el 0 and 1 are handled together 1175 scr = readMiscReg(MISCREG_SCR, tc); 1176 secure_lookup = haveSecurity && !scr.ns; 1177 sys = tc->getSystemPtr(); 1178 for (x = 0; x < sys->numContexts(); x++) { 1179 oc = sys->getThreadContext(x); 1180 assert(oc->getITBPtr() && oc->getDTBPtr()); 1181 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1182 secure_lookup, target_el); 1183 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1184 secure_lookup, target_el); 1185 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1186 if (checker) { 1187 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1188 secure_lookup, target_el); 1189 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1190 secure_lookup, target_el); 1191 } 1192 } 1193 return; 1194 // TLBI by address, EL0&1, inner sharable (ignored) 1195 case MISCREG_TLBIMVAAIS: 1196 case MISCREG_TLBIMVAA: 1197 assert32(tc); 1198 target_el = 1; // el 0 and 1 are handled together 1199 scr = readMiscReg(MISCREG_SCR, tc); 1200 secure_lookup = haveSecurity && !scr.ns; 1201 hyp = 0; 1202 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1203 return; 1204 // TLBI by address, EL2, hypervisor mode 1205 case MISCREG_TLBIMVAH: 1206 case MISCREG_TLBIMVAHIS: 1207 assert32(tc); 1208 target_el = 1; // aarch32, use hyp bit 1209 scr = readMiscReg(MISCREG_SCR, tc); 1210 secure_lookup = haveSecurity && !scr.ns; 1211 hyp = 1; 1212 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1213 return; 1214 // TLBI by address and asid, EL0&1, instruction side only 1215 case MISCREG_ITLBIMVA: 1216 assert32(tc); 1217 target_el = 1; // el 0 and 1 are handled together 1218 scr = readMiscReg(MISCREG_SCR, tc); 1219 secure_lookup = haveSecurity && !scr.ns; 1220 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1221 bits(newVal, 7,0), secure_lookup, target_el); 1222 return; 1223 // TLBI by address and asid, EL0&1, data side only 1224 case MISCREG_DTLBIMVA: 1225 assert32(tc); 1226 target_el = 1; // el 0 and 1 are handled together 1227 scr = readMiscReg(MISCREG_SCR, tc); 1228 secure_lookup = haveSecurity && !scr.ns; 1229 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1230 bits(newVal, 7,0), secure_lookup, target_el); 1231 return; 1232 // TLBI by ASID, EL0&1, instrution side only 1233 case MISCREG_ITLBIASID: 1234 assert32(tc); 1235 target_el = 1; // el 0 and 1 are handled together 1236 scr = readMiscReg(MISCREG_SCR, tc); 1237 secure_lookup = haveSecurity && !scr.ns; 1238 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1239 target_el); 1240 return; 1241 // TLBI by ASID EL0&1 data size only 1242 case MISCREG_DTLBIASID: 1243 assert32(tc); 1244 target_el = 1; // el 0 and 1 are handled together 1245 scr = readMiscReg(MISCREG_SCR, tc); 1246 secure_lookup = haveSecurity && !scr.ns; 1247 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1248 target_el); 1249 return; 1250 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1251 case MISCREG_TLBIALLNSNH: 1252 case MISCREG_TLBIALLNSNHIS: 1253 assert32(tc); 1254 target_el = 1; // el 0 and 1 are handled together 1255 hyp = 0; 1256 tlbiALLN(tc, hyp, target_el); 1257 return; 1258 // TLBI all entries, EL2, hyp, 1259 case MISCREG_TLBIALLH: 1260 case MISCREG_TLBIALLHIS: 1261 assert32(tc); 1262 target_el = 1; // aarch32, use hyp bit 1263 hyp = 1; 1264 tlbiALLN(tc, hyp, target_el); 1265 return; 1266 // AArch64 TLBI: invalidate all entries EL3 1267 case MISCREG_TLBI_ALLE3IS: 1268 case MISCREG_TLBI_ALLE3: 1269 assert64(tc); 1270 target_el = 3; 1271 secure_lookup = true; 1272 tlbiALL(tc, secure_lookup, target_el); 1273 return; 1274 // @todo: uncomment this to enable Virtualization 1275 // case MISCREG_TLBI_ALLE2IS: 1276 // case MISCREG_TLBI_ALLE2: 1277 // TLBI all entries, EL0&1 1278 case MISCREG_TLBI_ALLE1IS: 1279 case MISCREG_TLBI_ALLE1: 1280 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1281 case MISCREG_TLBI_VMALLE1IS: 1282 case MISCREG_TLBI_VMALLE1: 1283 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1284 case MISCREG_TLBI_VMALLS12E1IS: 1285 case MISCREG_TLBI_VMALLS12E1: 1286 // @todo: handle VMID and stage 2 to enable Virtualization 1287 assert64(tc); 1288 target_el = 1; // el 0 and 1 are handled together 1289 scr = readMiscReg(MISCREG_SCR, tc); 1290 secure_lookup = haveSecurity && !scr.ns; 1291 tlbiALL(tc, secure_lookup, target_el); 1292 return; 1293 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1294 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1295 // from the last level of translation table walks 1296 // @todo: handle VMID to enable Virtualization 1297 // TLBI all entries, EL0&1 1298 case MISCREG_TLBI_VAE3IS_Xt: 1299 case MISCREG_TLBI_VAE3_Xt: 1300 // TLBI by VA, EL3 regime stage 1, last level walk 1301 case MISCREG_TLBI_VALE3IS_Xt: 1302 case MISCREG_TLBI_VALE3_Xt: 1303 assert64(tc); 1304 target_el = 3; 1305 asid = 0xbeef; // does not matter, tlbi is global 1306 secure_lookup = true; 1307 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1308 return; 1309 // TLBI by VA, EL2 1310 case MISCREG_TLBI_VAE2IS_Xt: 1311 case MISCREG_TLBI_VAE2_Xt: 1312 // TLBI by VA, EL2, stage1 last level walk 1313 case MISCREG_TLBI_VALE2IS_Xt: 1314 case MISCREG_TLBI_VALE2_Xt: 1315 assert64(tc); 1316 target_el = 2; 1317 asid = 0xbeef; // does not matter, tlbi is global 1318 scr = readMiscReg(MISCREG_SCR, tc); 1319 secure_lookup = haveSecurity && !scr.ns; 1320 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1321 return; 1322 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1323 case MISCREG_TLBI_VAE1IS_Xt: 1324 case MISCREG_TLBI_VAE1_Xt: 1325 case MISCREG_TLBI_VALE1IS_Xt: 1326 case MISCREG_TLBI_VALE1_Xt: 1327 assert64(tc); 1328 asid = bits(newVal, 63, 48); 1329 target_el = 1; // el 0 and 1 are handled together 1330 scr = readMiscReg(MISCREG_SCR, tc); 1331 secure_lookup = haveSecurity && !scr.ns; 1332 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1333 return; 1334 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1335 // @todo: handle VMID to enable Virtualization 1336 case MISCREG_TLBI_ASIDE1IS_Xt: 1337 case MISCREG_TLBI_ASIDE1_Xt: 1338 assert64(tc); 1339 target_el = 1; // el 0 and 1 are handled together 1340 scr = readMiscReg(MISCREG_SCR, tc); 1341 secure_lookup = haveSecurity && !scr.ns; 1342 sys = tc->getSystemPtr(); 1343 for (x = 0; x < sys->numContexts(); x++) { 1344 oc = sys->getThreadContext(x); 1345 assert(oc->getITBPtr() && oc->getDTBPtr()); 1346 asid = bits(newVal, 63, 48); 1347 if (!haveLargeAsid64) 1348 asid &= mask(8); 1349 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1350 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1351 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1352 if (checker) { 1353 checker->getITBPtr()->flushAsid(asid, 1354 secure_lookup, target_el); 1355 checker->getDTBPtr()->flushAsid(asid, 1356 secure_lookup, target_el); 1357 } 1358 } 1359 return; 1360 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1361 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1362 // entries from the last level of translation table walks 1363 // @todo: handle VMID to enable Virtualization 1364 case MISCREG_TLBI_VAAE1IS_Xt: 1365 case MISCREG_TLBI_VAAE1_Xt: 1366 case MISCREG_TLBI_VAALE1IS_Xt: 1367 case MISCREG_TLBI_VAALE1_Xt: 1368 assert64(tc); 1369 target_el = 1; // el 0 and 1 are handled together 1370 scr = readMiscReg(MISCREG_SCR, tc); 1371 secure_lookup = haveSecurity && !scr.ns; 1372 sys = tc->getSystemPtr(); 1373 for (x = 0; x < sys->numContexts(); x++) { 1374 // @todo: extra controls on TLBI broadcast? 1375 oc = sys->getThreadContext(x); 1376 assert(oc->getITBPtr() && oc->getDTBPtr()); 1377 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1378 oc->getITBPtr()->flushMva(va, 1379 secure_lookup, false, target_el); 1380 oc->getDTBPtr()->flushMva(va, 1381 secure_lookup, false, target_el); 1382 1383 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1384 if (checker) { 1385 checker->getITBPtr()->flushMva(va, 1386 secure_lookup, false, target_el); 1387 checker->getDTBPtr()->flushMva(va, 1388 secure_lookup, false, target_el); 1389 } 1390 } 1391 return; 1392 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1393 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1394 case MISCREG_TLBI_IPAS2LE1_Xt: 1395 case MISCREG_TLBI_IPAS2E1IS_Xt: 1396 case MISCREG_TLBI_IPAS2E1_Xt: 1397 assert64(tc); 1398 // @todo: implement these as part of Virtualization 1399 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1400 return; 1401 case MISCREG_ACTLR: 1402 warn("Not doing anything for write of miscreg ACTLR\n"); 1403 break; 1404 1405 case MISCREG_PMXEVTYPER_PMCCFILTR: 1406 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1407 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1408 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1409 pmu->setMiscReg(misc_reg, newVal); 1410 break; 1411 1412 1413 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1414 { 1415 HSTR hstrMask = 0; 1416 hstrMask.tjdbx = 1; 1417 newVal &= ~((uint32_t) hstrMask); 1418 break; 1419 } 1420 case MISCREG_HCPTR: 1421 { 1422 // If a CP bit in NSACR is 0 then the corresponding bit in 1423 // HCPTR is RAO/WI. Same applies to NSASEDIS 1424 secure_lookup = haveSecurity && 1425 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1426 readMiscRegNoEffect(MISCREG_CPSR)); 1427 if (!secure_lookup) { 1428 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1429 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1430 newVal = (newVal & ~mask) | (oldValue & mask); 1431 } 1432 break; 1433 } 1434 case MISCREG_HDFAR: // alias for secure DFAR 1435 misc_reg = MISCREG_DFAR_S; 1436 break; 1437 case MISCREG_HIFAR: // alias for secure IFAR 1438 misc_reg = MISCREG_IFAR_S; 1439 break; 1440 case MISCREG_ATS1CPR: 1441 case MISCREG_ATS1CPW: 1442 case MISCREG_ATS1CUR: 1443 case MISCREG_ATS1CUW: 1444 case MISCREG_ATS12NSOPR: 1445 case MISCREG_ATS12NSOPW: 1446 case MISCREG_ATS12NSOUR: 1447 case MISCREG_ATS12NSOUW: 1448 case MISCREG_ATS1HR: 1449 case MISCREG_ATS1HW: 1450 { 1451 unsigned flags = 0; 1452 BaseTLB::Mode mode = BaseTLB::Read; 1453 TLB::ArmTranslationType tranType = TLB::NormalTran; 1454 Fault fault; 1455 switch(misc_reg) { 1456 case MISCREG_ATS1CPR: 1457 flags = TLB::MustBeOne; 1458 tranType = TLB::S1CTran; 1459 mode = BaseTLB::Read; 1460 break; 1461 case MISCREG_ATS1CPW: 1462 flags = TLB::MustBeOne; 1463 tranType = TLB::S1CTran; 1464 mode = BaseTLB::Write; 1465 break; 1466 case MISCREG_ATS1CUR: 1467 flags = TLB::MustBeOne | TLB::UserMode; 1468 tranType = TLB::S1CTran; 1469 mode = BaseTLB::Read; 1470 break; 1471 case MISCREG_ATS1CUW: 1472 flags = TLB::MustBeOne | TLB::UserMode; 1473 tranType = TLB::S1CTran; 1474 mode = BaseTLB::Write; 1475 break; 1476 case MISCREG_ATS12NSOPR: 1477 if (!haveSecurity) 1478 panic("Security Extensions required for ATS12NSOPR"); 1479 flags = TLB::MustBeOne; 1480 tranType = TLB::S1S2NsTran; 1481 mode = BaseTLB::Read; 1482 break; 1483 case MISCREG_ATS12NSOPW: 1484 if (!haveSecurity) 1485 panic("Security Extensions required for ATS12NSOPW"); 1486 flags = TLB::MustBeOne; 1487 tranType = TLB::S1S2NsTran; 1488 mode = BaseTLB::Write; 1489 break; 1490 case MISCREG_ATS12NSOUR: 1491 if (!haveSecurity) 1492 panic("Security Extensions required for ATS12NSOUR"); 1493 flags = TLB::MustBeOne | TLB::UserMode; 1494 tranType = TLB::S1S2NsTran; 1495 mode = BaseTLB::Read; 1496 break; 1497 case MISCREG_ATS12NSOUW: 1498 if (!haveSecurity) 1499 panic("Security Extensions required for ATS12NSOUW"); 1500 flags = TLB::MustBeOne | TLB::UserMode; 1501 tranType = TLB::S1S2NsTran; 1502 mode = BaseTLB::Write; 1503 break; 1504 case MISCREG_ATS1HR: // only really useful from secure mode. 1505 flags = TLB::MustBeOne; 1506 tranType = TLB::HypMode; 1507 mode = BaseTLB::Read; 1508 break; 1509 case MISCREG_ATS1HW: 1510 flags = TLB::MustBeOne; 1511 tranType = TLB::HypMode; 1512 mode = BaseTLB::Write; 1513 break; 1514 } 1515 // If we're in timing mode then doing the translation in 1516 // functional mode then we're slightly distorting performance 1517 // results obtained from simulations. The translation should be 1518 // done in the same mode the core is running in. NOTE: This 1519 // can't be an atomic translation because that causes problems 1520 // with unexpected atomic snoop requests. 1521 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1522 Request req(0, val, 1, flags, Request::funcMasterId, 1523 tc->pcState().pc(), tc->contextId(), 1524 tc->threadId()); 1525 fault = tc->getDTBPtr()->translateFunctional(&req, tc, mode, tranType); 1526 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1527 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1528 1529 MiscReg newVal; 1530 if (fault == NoFault) { 1531 Addr paddr = req.getPaddr(); 1532 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1533 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1534 newVal = (paddr & mask(39, 12)) | 1535 (tc->getDTBPtr()->getAttr()); 1536 } else { 1537 newVal = (paddr & 0xfffff000) | 1538 (tc->getDTBPtr()->getAttr()); 1539 } 1540 DPRINTF(MiscRegs, 1541 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1542 val, newVal); 1543 } else { 1544 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1545 // Set fault bit and FSR 1546 FSR fsr = armFault->getFsr(tc); 1547 1548 newVal = ((fsr >> 9) & 1) << 11; 1549 if (newVal) { 1550 // LPAE - rearange fault status 1551 newVal |= ((fsr >> 0) & 0x3f) << 1; 1552 } else { 1553 // VMSA - rearange fault status 1554 newVal |= ((fsr >> 0) & 0xf) << 1; 1555 newVal |= ((fsr >> 10) & 0x1) << 5; 1556 newVal |= ((fsr >> 12) & 0x1) << 6; 1557 } 1558 newVal |= 0x1; // F bit 1559 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1560 newVal |= armFault->isStage2() ? 0x200 : 0; 1561 DPRINTF(MiscRegs, 1562 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1563 val, fsr, newVal); 1564 } 1565 setMiscRegNoEffect(MISCREG_PAR, newVal); 1566 return; 1567 } 1568 case MISCREG_TTBCR: 1569 { 1570 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1571 const uint32_t ones = (uint32_t)(-1); 1572 TTBCR ttbcrMask = 0; 1573 TTBCR ttbcrNew = newVal; 1574 1575 // ARM DDI 0406C.b, ARMv7-32 1576 ttbcrMask.n = ones; // T0SZ 1577 if (haveSecurity) { 1578 ttbcrMask.pd0 = ones; 1579 ttbcrMask.pd1 = ones; 1580 } 1581 ttbcrMask.epd0 = ones; 1582 ttbcrMask.irgn0 = ones; 1583 ttbcrMask.orgn0 = ones; 1584 ttbcrMask.sh0 = ones; 1585 ttbcrMask.ps = ones; // T1SZ 1586 ttbcrMask.a1 = ones; 1587 ttbcrMask.epd1 = ones; 1588 ttbcrMask.irgn1 = ones; 1589 ttbcrMask.orgn1 = ones; 1590 ttbcrMask.sh1 = ones; 1591 if (haveLPAE) 1592 ttbcrMask.eae = ones; 1593 1594 if (haveLPAE && ttbcrNew.eae) { 1595 newVal = newVal & ttbcrMask; 1596 } else { 1597 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1598 } 1599 } 1600 case MISCREG_TTBR0: 1601 case MISCREG_TTBR1: 1602 { 1603 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1604 if (haveLPAE) { 1605 if (ttbcr.eae) { 1606 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1607 // ARMv8 AArch32 bit 63-56 only 1608 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1609 newVal = (newVal & (~ttbrMask)); 1610 } 1611 } 1612 } 1613 case MISCREG_SCTLR_EL1: 1614 { 1615 tc->getITBPtr()->invalidateMiscReg(); 1616 tc->getDTBPtr()->invalidateMiscReg(); 1617 setMiscRegNoEffect(misc_reg, newVal); 1618 } 1619 case MISCREG_CONTEXTIDR: 1620 case MISCREG_PRRR: 1621 case MISCREG_NMRR: 1622 case MISCREG_MAIR0: 1623 case MISCREG_MAIR1: 1624 case MISCREG_DACR: 1625 case MISCREG_VTTBR: 1626 case MISCREG_SCR_EL3: 1627 case MISCREG_TCR_EL1: 1628 case MISCREG_TCR_EL2: 1629 case MISCREG_TCR_EL3: 1630 case MISCREG_SCTLR_EL2: 1631 case MISCREG_SCTLR_EL3: 1632 case MISCREG_TTBR0_EL1: 1633 case MISCREG_TTBR1_EL1: 1634 case MISCREG_TTBR0_EL2: 1635 case MISCREG_TTBR0_EL3: 1636 tc->getITBPtr()->invalidateMiscReg(); 1637 tc->getDTBPtr()->invalidateMiscReg(); 1638 break; 1639 case MISCREG_NZCV: 1640 { 1641 CPSR cpsr = val; 1642 1643 tc->setCCReg(CCREG_NZ, cpsr.nz); 1644 tc->setCCReg(CCREG_C, cpsr.c); 1645 tc->setCCReg(CCREG_V, cpsr.v); 1646 } 1647 break; 1648 case MISCREG_DAIF: 1649 { 1650 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1651 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1652 newVal = cpsr; 1653 misc_reg = MISCREG_CPSR; 1654 } 1655 break; 1656 case MISCREG_SP_EL0: 1657 tc->setIntReg(INTREG_SP0, newVal); 1658 break; 1659 case MISCREG_SP_EL1: 1660 tc->setIntReg(INTREG_SP1, newVal); 1661 break; 1662 case MISCREG_SP_EL2: 1663 tc->setIntReg(INTREG_SP2, newVal); 1664 break; 1665 case MISCREG_SPSEL: 1666 { 1667 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1668 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1669 newVal = cpsr; 1670 misc_reg = MISCREG_CPSR; 1671 } 1672 break; 1673 case MISCREG_CURRENTEL: 1674 { 1675 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1676 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1677 newVal = cpsr; 1678 misc_reg = MISCREG_CPSR; 1679 } 1680 break; 1681 case MISCREG_AT_S1E1R_Xt: 1682 case MISCREG_AT_S1E1W_Xt: 1683 case MISCREG_AT_S1E0R_Xt: 1684 case MISCREG_AT_S1E0W_Xt: 1685 case MISCREG_AT_S1E2R_Xt: 1686 case MISCREG_AT_S1E2W_Xt: 1687 case MISCREG_AT_S12E1R_Xt: 1688 case MISCREG_AT_S12E1W_Xt: 1689 case MISCREG_AT_S12E0R_Xt: 1690 case MISCREG_AT_S12E0W_Xt: 1691 case MISCREG_AT_S1E3R_Xt: 1692 case MISCREG_AT_S1E3W_Xt: 1693 { 1694 RequestPtr req = new Request; 1695 unsigned flags = 0; 1696 BaseTLB::Mode mode = BaseTLB::Read; 1697 TLB::ArmTranslationType tranType = TLB::NormalTran; 1698 Fault fault; 1699 switch(misc_reg) { 1700 case MISCREG_AT_S1E1R_Xt: 1701 flags = TLB::MustBeOne; 1702 tranType = TLB::S1CTran; 1703 mode = BaseTLB::Read; 1704 break; 1705 case MISCREG_AT_S1E1W_Xt: 1706 flags = TLB::MustBeOne; 1707 tranType = TLB::S1CTran; 1708 mode = BaseTLB::Write; 1709 break; 1710 case MISCREG_AT_S1E0R_Xt: 1711 flags = TLB::MustBeOne | TLB::UserMode; 1712 tranType = TLB::S1CTran; 1713 mode = BaseTLB::Read; 1714 break; 1715 case MISCREG_AT_S1E0W_Xt: 1716 flags = TLB::MustBeOne | TLB::UserMode; 1717 tranType = TLB::S1CTran; 1718 mode = BaseTLB::Write; 1719 break; 1720 case MISCREG_AT_S1E2R_Xt: 1721 flags = TLB::MustBeOne; 1722 tranType = TLB::HypMode; 1723 mode = BaseTLB::Read; 1724 break; 1725 case MISCREG_AT_S1E2W_Xt: 1726 flags = TLB::MustBeOne; 1727 tranType = TLB::HypMode; 1728 mode = BaseTLB::Write; 1729 break; 1730 case MISCREG_AT_S12E0R_Xt: 1731 flags = TLB::MustBeOne | TLB::UserMode; 1732 tranType = TLB::S1S2NsTran; 1733 mode = BaseTLB::Read; 1734 break; 1735 case MISCREG_AT_S12E0W_Xt: 1736 flags = TLB::MustBeOne | TLB::UserMode; 1737 tranType = TLB::S1S2NsTran; 1738 mode = BaseTLB::Write; 1739 break; 1740 case MISCREG_AT_S12E1R_Xt: 1741 flags = TLB::MustBeOne; 1742 tranType = TLB::S1S2NsTran; 1743 mode = BaseTLB::Read; 1744 break; 1745 case MISCREG_AT_S12E1W_Xt: 1746 flags = TLB::MustBeOne; 1747 tranType = TLB::S1S2NsTran; 1748 mode = BaseTLB::Write; 1749 break; 1750 case MISCREG_AT_S1E3R_Xt: 1751 flags = TLB::MustBeOne; 1752 tranType = TLB::HypMode; // There is no TZ mode defined. 1753 mode = BaseTLB::Read; 1754 break; 1755 case MISCREG_AT_S1E3W_Xt: 1756 flags = TLB::MustBeOne; 1757 tranType = TLB::HypMode; // There is no TZ mode defined. 1758 mode = BaseTLB::Write; 1759 break; 1760 } 1761 // If we're in timing mode then doing the translation in 1762 // functional mode then we're slightly distorting performance 1763 // results obtained from simulations. The translation should be 1764 // done in the same mode the core is running in. NOTE: This 1765 // can't be an atomic translation because that causes problems 1766 // with unexpected atomic snoop requests. 1767 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1768 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1769 tc->pcState().pc()); 1770 req->setThreadContext(tc->contextId(), tc->threadId()); 1771 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1772 tranType); 1773 1774 MiscReg newVal; 1775 if (fault == NoFault) { 1776 Addr paddr = req->getPaddr(); 1777 uint64_t attr = tc->getDTBPtr()->getAttr(); 1778 uint64_t attr1 = attr >> 56; 1779 if (!attr1 || attr1 ==0x44) { 1780 attr |= 0x100; 1781 attr &= ~ uint64_t(0x80); 1782 } 1783 newVal = (paddr & mask(47, 12)) | attr; 1784 DPRINTF(MiscRegs, 1785 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1786 val, newVal); 1787 } else { 1788 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1789 // Set fault bit and FSR 1790 FSR fsr = armFault->getFsr(tc); 1791 1792 newVal = ((fsr >> 9) & 1) << 11; 1793 // rearange fault status 1794 newVal |= ((fsr >> 0) & 0x3f) << 1; 1795 newVal |= 0x1; // F bit 1796 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1797 newVal |= armFault->isStage2() ? 0x200 : 0; 1798 DPRINTF(MiscRegs, 1799 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1800 val, fsr, newVal); 1801 } 1802 delete req; 1803 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1804 return; 1805 } 1806 case MISCREG_SPSR_EL3: 1807 case MISCREG_SPSR_EL2: 1808 case MISCREG_SPSR_EL1: 1809 // Force bits 23:21 to 0 1810 newVal = val & ~(0x7 << 21); 1811 break; 1812 case MISCREG_L2CTLR: 1813 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1814 miscRegName[misc_reg], uint32_t(val)); 1815 break; 1816 1817 // Generic Timer registers 1818 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 1819 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 1820 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 1821 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 1822 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 1823 break; 1824 } 1825 } 1826 setMiscRegNoEffect(misc_reg, newVal); 1827} 1828 1829void 1830ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint16_t asid, 1831 bool secure_lookup, uint8_t target_el) 1832{ 1833 if (!haveLargeAsid64) 1834 asid &= mask(8); 1835 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1836 System *sys = tc->getSystemPtr(); 1837 for (int x = 0; x < sys->numContexts(); x++) { 1838 ThreadContext *oc = sys->getThreadContext(x); 1839 assert(oc->getITBPtr() && oc->getDTBPtr()); 1840 oc->getITBPtr()->flushMvaAsid(va, asid, 1841 secure_lookup, target_el); 1842 oc->getDTBPtr()->flushMvaAsid(va, asid, 1843 secure_lookup, target_el); 1844 1845 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1846 if (checker) { 1847 checker->getITBPtr()->flushMvaAsid( 1848 va, asid, secure_lookup, target_el); 1849 checker->getDTBPtr()->flushMvaAsid( 1850 va, asid, secure_lookup, target_el); 1851 } 1852 } 1853} 1854 1855void 1856ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1857{ 1858 System *sys = tc->getSystemPtr(); 1859 for (int x = 0; x < sys->numContexts(); x++) { 1860 ThreadContext *oc = sys->getThreadContext(x); 1861 assert(oc->getITBPtr() && oc->getDTBPtr()); 1862 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1863 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1864 1865 // If CheckerCPU is connected, need to notify it of a flush 1866 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1867 if (checker) { 1868 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1869 target_el); 1870 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1871 target_el); 1872 } 1873 } 1874} 1875 1876void 1877ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1878{ 1879 System *sys = tc->getSystemPtr(); 1880 for (int x = 0; x < sys->numContexts(); x++) { 1881 ThreadContext *oc = sys->getThreadContext(x); 1882 assert(oc->getITBPtr() && oc->getDTBPtr()); 1883 oc->getITBPtr()->flushAllNs(hyp, target_el); 1884 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1885 1886 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1887 if (checker) { 1888 checker->getITBPtr()->flushAllNs(hyp, target_el); 1889 checker->getDTBPtr()->flushAllNs(hyp, target_el); 1890 } 1891 } 1892} 1893 1894void 1895ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 1896 uint8_t target_el) 1897{ 1898 System *sys = tc->getSystemPtr(); 1899 for (int x = 0; x < sys->numContexts(); x++) { 1900 ThreadContext *oc = sys->getThreadContext(x); 1901 assert(oc->getITBPtr() && oc->getDTBPtr()); 1902 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 1903 secure_lookup, hyp, target_el); 1904 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1905 secure_lookup, hyp, target_el); 1906 1907 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1908 if (checker) { 1909 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 1910 secure_lookup, hyp, target_el); 1911 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 1912 secure_lookup, hyp, target_el); 1913 } 1914 } 1915} 1916 1917BaseISADevice & 1918ISA::getGenericTimer(ThreadContext *tc) 1919{ 1920 // We only need to create an ISA interface the first time we try 1921 // to access the timer. 1922 if (timer) 1923 return *timer.get(); 1924 1925 assert(system); 1926 GenericTimer *generic_timer(system->getGenericTimer()); 1927 if (!generic_timer) { 1928 panic("Trying to get a generic timer from a system that hasn't " 1929 "been configured to use a generic timer.\n"); 1930 } 1931 1932 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 1933 return *timer.get(); 1934} 1935 1936} 1937 1938ArmISA::ISA * 1939ArmISAParams::create() 1940{ 1941 return new ArmISA::ISA(this); 1942} 1943