isa.cc revision 10508
1/* 2 * Copyright (c) 2010-2014 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/pmu.hh" 43#include "arch/arm/system.hh" 44#include "cpu/checker/cpu.hh" 45#include "cpu/base.hh" 46#include "debug/Arm.hh" 47#include "debug/MiscRegs.hh" 48#include "params/ArmISA.hh" 49#include "sim/faults.hh" 50#include "sim/stat_control.hh" 51#include "sim/system.hh" 52 53namespace ArmISA 54{ 55 56 57/** 58 * Some registers aliase with others, and therefore need to be translated. 59 * For each entry: 60 * The first value is the misc register that is to be looked up 61 * the second value is the lower part of the translation 62 * the third the upper part 63 */ 64const struct ISA::MiscRegInitializerEntry 65 ISA::MiscRegSwitch[miscRegTranslateMax] = { 66 {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}}, 67 {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}}, 68 {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}}, 69 {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}}, 70 {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}}, 71 {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}}, 72 {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}}, 73 {MISCREG_HCR_EL2, {MISCREG_HCR, 0}}, 74 {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}}, 75 {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}}, 76 {MISCREG_HACR_EL2, {MISCREG_HACR, 0}}, 77 {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}}, 78 {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}}, 79 {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}}, 80 {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}}, 81 {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}}, 82 {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}}, 83 {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}}, 84 {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}}, 85 {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}}, 86 {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}}, 87 {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}}, 88 {MISCREG_ESR_EL2, {MISCREG_HSR, 0}}, 89 {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}}, 90 {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}}, 91 {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}}, 92 {MISCREG_PAR_EL1, {MISCREG_PAR, 0}}, 93 {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}}, 94 {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}}, 95 {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}}, 96 {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}}, 97 {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}}, 98 {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}}, 99 {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}}, 100 {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}}, 101 {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}}, 102 {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}}, 103 {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}}, 104 {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}}, 105 {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}}, 106 {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}}, 107 {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}}, 108 {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}}, 109 {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}}, 110 {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}}, 111 {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}}, 112 {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}}, 113 {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}}, 114 {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}}, 115 {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}}, 116 {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}}, 117 {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}}, 118 {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}}, 119 {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}}, 120 {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}}, 121 {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}}, 122 {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}} 123}; 124 125 126ISA::ISA(Params *p) 127 : SimObject(p), 128 system(NULL), 129 pmu(p->pmu), 130 lookUpMiscReg(NUM_MISCREGS, {0,0}) 131{ 132 SCTLR sctlr; 133 sctlr = 0; 134 miscRegs[MISCREG_SCTLR_RST] = sctlr; 135 136 // Hook up a dummy device if we haven't been configured with a 137 // real PMU. By using a dummy device, we don't need to check that 138 // the PMU exist every time we try to access a PMU register. 139 if (!pmu) 140 pmu = &dummyDevice; 141 142 system = dynamic_cast<ArmSystem *>(p->system); 143 DPRINTFN("ISA system set to: %p %p\n", system, p->system); 144 145 // Cache system-level properties 146 if (FullSystem && system) { 147 haveSecurity = system->haveSecurity(); 148 haveLPAE = system->haveLPAE(); 149 haveVirtualization = system->haveVirtualization(); 150 haveLargeAsid64 = system->haveLargeAsid64(); 151 physAddrRange64 = system->physAddrRange64(); 152 } else { 153 haveSecurity = haveLPAE = haveVirtualization = false; 154 haveLargeAsid64 = false; 155 physAddrRange64 = 32; // dummy value 156 } 157 158 /** Fill in the miscReg translation table */ 159 for (uint32_t i = 0; i < miscRegTranslateMax; i++) { 160 struct MiscRegLUTEntry new_entry; 161 162 uint32_t select = MiscRegSwitch[i].index; 163 new_entry = MiscRegSwitch[i].entry; 164 165 lookUpMiscReg[select] = new_entry; 166 } 167 168 preUnflattenMiscReg(); 169 170 clear(); 171} 172 173const ArmISAParams * 174ISA::params() const 175{ 176 return dynamic_cast<const Params *>(_params); 177} 178 179void 180ISA::clear() 181{ 182 const Params *p(params()); 183 184 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 185 memset(miscRegs, 0, sizeof(miscRegs)); 186 187 // Initialize configurable default values 188 miscRegs[MISCREG_MIDR] = p->midr; 189 miscRegs[MISCREG_MIDR_EL1] = p->midr; 190 miscRegs[MISCREG_VPIDR] = p->midr; 191 192 if (FullSystem && system->highestELIs64()) { 193 // Initialize AArch64 state 194 clear64(p); 195 return; 196 } 197 198 // Initialize AArch32 state... 199 200 CPSR cpsr = 0; 201 cpsr.mode = MODE_USER; 202 miscRegs[MISCREG_CPSR] = cpsr; 203 updateRegMap(cpsr); 204 205 SCTLR sctlr = 0; 206 sctlr.te = (bool) sctlr_rst.te; 207 sctlr.nmfi = (bool) sctlr_rst.nmfi; 208 sctlr.v = (bool) sctlr_rst.v; 209 sctlr.u = 1; 210 sctlr.xp = 1; 211 sctlr.rao2 = 1; 212 sctlr.rao3 = 1; 213 sctlr.rao4 = 0xf; // SCTLR[6:3] 214 sctlr.uci = 1; 215 sctlr.dze = 1; 216 miscRegs[MISCREG_SCTLR_NS] = sctlr; 217 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 218 miscRegs[MISCREG_HCPTR] = 0; 219 220 // Start with an event in the mailbox 221 miscRegs[MISCREG_SEV_MAILBOX] = 1; 222 223 // Separate Instruction and Data TLBs 224 miscRegs[MISCREG_TLBTR] = 1; 225 226 MVFR0 mvfr0 = 0; 227 mvfr0.advSimdRegisters = 2; 228 mvfr0.singlePrecision = 2; 229 mvfr0.doublePrecision = 2; 230 mvfr0.vfpExceptionTrapping = 0; 231 mvfr0.divide = 1; 232 mvfr0.squareRoot = 1; 233 mvfr0.shortVectors = 1; 234 mvfr0.roundingModes = 1; 235 miscRegs[MISCREG_MVFR0] = mvfr0; 236 237 MVFR1 mvfr1 = 0; 238 mvfr1.flushToZero = 1; 239 mvfr1.defaultNaN = 1; 240 mvfr1.advSimdLoadStore = 1; 241 mvfr1.advSimdInteger = 1; 242 mvfr1.advSimdSinglePrecision = 1; 243 mvfr1.advSimdHalfPrecision = 1; 244 mvfr1.vfpHalfPrecision = 1; 245 miscRegs[MISCREG_MVFR1] = mvfr1; 246 247 // Reset values of PRRR and NMRR are implementation dependent 248 249 // @todo: PRRR and NMRR in secure state? 250 miscRegs[MISCREG_PRRR_NS] = 251 (1 << 19) | // 19 252 (0 << 18) | // 18 253 (0 << 17) | // 17 254 (1 << 16) | // 16 255 (2 << 14) | // 15:14 256 (0 << 12) | // 13:12 257 (2 << 10) | // 11:10 258 (2 << 8) | // 9:8 259 (2 << 6) | // 7:6 260 (2 << 4) | // 5:4 261 (1 << 2) | // 3:2 262 0; // 1:0 263 miscRegs[MISCREG_NMRR_NS] = 264 (1 << 30) | // 31:30 265 (0 << 26) | // 27:26 266 (0 << 24) | // 25:24 267 (3 << 22) | // 23:22 268 (2 << 20) | // 21:20 269 (0 << 18) | // 19:18 270 (0 << 16) | // 17:16 271 (1 << 14) | // 15:14 272 (0 << 12) | // 13:12 273 (2 << 10) | // 11:10 274 (0 << 8) | // 9:8 275 (3 << 6) | // 7:6 276 (2 << 4) | // 5:4 277 (0 << 2) | // 3:2 278 0; // 1:0 279 280 miscRegs[MISCREG_CPACR] = 0; 281 282 283 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 284 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 285 286 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 287 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 288 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 289 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 290 291 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 292 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 293 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 294 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 295 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 296 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 297 298 miscRegs[MISCREG_FPSID] = p->fpsid; 299 300 if (haveLPAE) { 301 TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 302 ttbcr.eae = 0; 303 miscRegs[MISCREG_TTBCR_NS] = ttbcr; 304 // Enforce consistency with system-level settings 305 miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 306 } 307 308 if (haveSecurity) { 309 miscRegs[MISCREG_SCTLR_S] = sctlr; 310 miscRegs[MISCREG_SCR] = 0; 311 miscRegs[MISCREG_VBAR_S] = 0; 312 } else { 313 // we're always non-secure 314 miscRegs[MISCREG_SCR] = 1; 315 } 316 317 //XXX We need to initialize the rest of the state. 318} 319 320void 321ISA::clear64(const ArmISAParams *p) 322{ 323 CPSR cpsr = 0; 324 Addr rvbar = system->resetAddr64(); 325 switch (system->highestEL()) { 326 // Set initial EL to highest implemented EL using associated stack 327 // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 328 // value 329 case EL3: 330 cpsr.mode = MODE_EL3H; 331 miscRegs[MISCREG_RVBAR_EL3] = rvbar; 332 break; 333 case EL2: 334 cpsr.mode = MODE_EL2H; 335 miscRegs[MISCREG_RVBAR_EL2] = rvbar; 336 break; 337 case EL1: 338 cpsr.mode = MODE_EL1H; 339 miscRegs[MISCREG_RVBAR_EL1] = rvbar; 340 break; 341 default: 342 panic("Invalid highest implemented exception level"); 343 break; 344 } 345 346 // Initialize rest of CPSR 347 cpsr.daif = 0xf; // Mask all interrupts 348 cpsr.ss = 0; 349 cpsr.il = 0; 350 miscRegs[MISCREG_CPSR] = cpsr; 351 updateRegMap(cpsr); 352 353 // Initialize other control registers 354 miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 355 if (haveSecurity) { 356 miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870; 357 miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 358 // @todo: uncomment this to enable Virtualization 359 // } else if (haveVirtualization) { 360 // miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870; 361 } else { 362 miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870; 363 // Always non-secure 364 miscRegs[MISCREG_SCR_EL3] = 1; 365 } 366 367 // Initialize configurable id registers 368 miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 369 miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 370 miscRegs[MISCREG_ID_AA64DFR0_EL1] = 371 (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 372 (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 373 374 miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 375 miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 376 miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 377 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 378 miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 379 miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1; 380 miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1; 381 382 miscRegs[MISCREG_ID_DFR0_EL1] = 383 (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 384 385 miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 386 387 // Enforce consistency with system-level settings... 388 389 // EL3 390 // (no AArch32/64 interprocessing support for now) 391 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 392 miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 393 haveSecurity ? 0x1 : 0x0); 394 // EL2 395 // (no AArch32/64 interprocessing support for now) 396 miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 397 miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 398 haveVirtualization ? 0x1 : 0x0); 399 // Large ASID support 400 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 401 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 402 haveLargeAsid64 ? 0x2 : 0x0); 403 // Physical address size 404 miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 405 miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 406 encodePhysAddrRange64(physAddrRange64)); 407} 408 409MiscReg 410ISA::readMiscRegNoEffect(int misc_reg) const 411{ 412 assert(misc_reg < NumMiscRegs); 413 414 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 415 // registers are left unchanged 416 MiscReg val; 417 418 if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR 419 || flat_idx == MISCREG_SCTLR_EL1) { 420 if (flat_idx == MISCREG_SPSR) 421 flat_idx = flattenMiscIndex(MISCREG_SPSR); 422 if (flat_idx == MISCREG_SCTLR_EL1) 423 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 424 val = miscRegs[flat_idx]; 425 } else 426 if (lookUpMiscReg[flat_idx].upper > 0) 427 val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32)) 428 | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32)); 429 else 430 val = miscRegs[lookUpMiscReg[flat_idx].lower]; 431 432 return val; 433} 434 435 436MiscReg 437ISA::readMiscReg(int misc_reg, ThreadContext *tc) 438{ 439 CPSR cpsr = 0; 440 PCState pc = 0; 441 SCR scr = 0; 442 443 if (misc_reg == MISCREG_CPSR) { 444 cpsr = miscRegs[misc_reg]; 445 pc = tc->pcState(); 446 cpsr.j = pc.jazelle() ? 1 : 0; 447 cpsr.t = pc.thumb() ? 1 : 0; 448 return cpsr; 449 } 450 451#ifndef NDEBUG 452 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 453 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 454 warn("Unimplemented system register %s read.\n", 455 miscRegName[misc_reg]); 456 else 457 panic("Unimplemented system register %s read.\n", 458 miscRegName[misc_reg]); 459 } 460#endif 461 462 switch (unflattenMiscReg(misc_reg)) { 463 case MISCREG_HCR: 464 { 465 if (!haveVirtualization) 466 return 0; 467 else 468 return readMiscRegNoEffect(MISCREG_HCR); 469 } 470 case MISCREG_CPACR: 471 { 472 const uint32_t ones = (uint32_t)(-1); 473 CPACR cpacrMask = 0; 474 // Only cp10, cp11, and ase are implemented, nothing else should 475 // be readable? (straight copy from the write code) 476 cpacrMask.cp10 = ones; 477 cpacrMask.cp11 = ones; 478 cpacrMask.asedis = ones; 479 480 // Security Extensions may limit the readability of CPACR 481 if (haveSecurity) { 482 scr = readMiscRegNoEffect(MISCREG_SCR); 483 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 484 if (scr.ns && (cpsr.mode != MODE_MON)) { 485 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 486 // NB: Skipping the full loop, here 487 if (!nsacr.cp10) cpacrMask.cp10 = 0; 488 if (!nsacr.cp11) cpacrMask.cp11 = 0; 489 } 490 } 491 MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 492 val &= cpacrMask; 493 DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 494 miscRegName[misc_reg], val); 495 return val; 496 } 497 case MISCREG_MPIDR: 498 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 499 scr = readMiscRegNoEffect(MISCREG_SCR); 500 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 501 return getMPIDR(system, tc); 502 } else { 503 return readMiscReg(MISCREG_VMPIDR, tc); 504 } 505 break; 506 case MISCREG_MPIDR_EL1: 507 // @todo in the absence of v8 virtualization support just return MPIDR_EL1 508 return getMPIDR(system, tc) & 0xffffffff; 509 case MISCREG_VMPIDR: 510 // top bit defined as RES1 511 return readMiscRegNoEffect(misc_reg) | 0x80000000; 512 case MISCREG_ID_AFR0: // not implemented, so alias MIDR 513 case MISCREG_REVIDR: // not implemented, so alias MIDR 514 case MISCREG_MIDR: 515 cpsr = readMiscRegNoEffect(MISCREG_CPSR); 516 scr = readMiscRegNoEffect(MISCREG_SCR); 517 if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 518 return readMiscRegNoEffect(misc_reg); 519 } else { 520 return readMiscRegNoEffect(MISCREG_VPIDR); 521 } 522 break; 523 case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 524 case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 525 case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 526 case MISCREG_AIDR: // AUX ID set to 0 527 case MISCREG_TCMTR: // No TCM's 528 return 0; 529 530 case MISCREG_CLIDR: 531 warn_once("The clidr register always reports 0 caches.\n"); 532 warn_once("clidr LoUIS field of 0b001 to match current " 533 "ARM implementations.\n"); 534 return 0x00200000; 535 case MISCREG_CCSIDR: 536 warn_once("The ccsidr register isn't implemented and " 537 "always reads as 0.\n"); 538 break; 539 case MISCREG_CTR: 540 { 541 //all caches have the same line size in gem5 542 //4 byte words in ARM 543 unsigned lineSizeWords = 544 tc->getSystemPtr()->cacheLineSize() / 4; 545 unsigned log2LineSizeWords = 0; 546 547 while (lineSizeWords >>= 1) { 548 ++log2LineSizeWords; 549 } 550 551 CTR ctr = 0; 552 //log2 of minimun i-cache line size (words) 553 ctr.iCacheLineSize = log2LineSizeWords; 554 //b11 - gem5 uses pipt 555 ctr.l1IndexPolicy = 0x3; 556 //log2 of minimum d-cache line size (words) 557 ctr.dCacheLineSize = log2LineSizeWords; 558 //log2 of max reservation size (words) 559 ctr.erg = log2LineSizeWords; 560 //log2 of max writeback size (words) 561 ctr.cwg = log2LineSizeWords; 562 //b100 - gem5 format is ARMv7 563 ctr.format = 0x4; 564 565 return ctr; 566 } 567 case MISCREG_ACTLR: 568 warn("Not doing anything for miscreg ACTLR\n"); 569 break; 570 571 case MISCREG_PMXEVTYPER_PMCCFILTR: 572 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 573 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 574 case MISCREG_PMCR ... MISCREG_PMOVSSET: 575 return pmu->readMiscReg(misc_reg); 576 577 case MISCREG_CPSR_Q: 578 panic("shouldn't be reading this register seperately\n"); 579 case MISCREG_FPSCR_QC: 580 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 581 case MISCREG_FPSCR_EXC: 582 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 583 case MISCREG_FPSR: 584 { 585 const uint32_t ones = (uint32_t)(-1); 586 FPSCR fpscrMask = 0; 587 fpscrMask.ioc = ones; 588 fpscrMask.dzc = ones; 589 fpscrMask.ofc = ones; 590 fpscrMask.ufc = ones; 591 fpscrMask.ixc = ones; 592 fpscrMask.idc = ones; 593 fpscrMask.qc = ones; 594 fpscrMask.v = ones; 595 fpscrMask.c = ones; 596 fpscrMask.z = ones; 597 fpscrMask.n = ones; 598 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 599 } 600 case MISCREG_FPCR: 601 { 602 const uint32_t ones = (uint32_t)(-1); 603 FPSCR fpscrMask = 0; 604 fpscrMask.ioe = ones; 605 fpscrMask.dze = ones; 606 fpscrMask.ofe = ones; 607 fpscrMask.ufe = ones; 608 fpscrMask.ixe = ones; 609 fpscrMask.ide = ones; 610 fpscrMask.len = ones; 611 fpscrMask.stride = ones; 612 fpscrMask.rMode = ones; 613 fpscrMask.fz = ones; 614 fpscrMask.dn = ones; 615 fpscrMask.ahp = ones; 616 return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 617 } 618 case MISCREG_NZCV: 619 { 620 CPSR cpsr = 0; 621 cpsr.nz = tc->readCCReg(CCREG_NZ); 622 cpsr.c = tc->readCCReg(CCREG_C); 623 cpsr.v = tc->readCCReg(CCREG_V); 624 return cpsr; 625 } 626 case MISCREG_DAIF: 627 { 628 CPSR cpsr = 0; 629 cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 630 return cpsr; 631 } 632 case MISCREG_SP_EL0: 633 { 634 return tc->readIntReg(INTREG_SP0); 635 } 636 case MISCREG_SP_EL1: 637 { 638 return tc->readIntReg(INTREG_SP1); 639 } 640 case MISCREG_SP_EL2: 641 { 642 return tc->readIntReg(INTREG_SP2); 643 } 644 case MISCREG_SPSEL: 645 { 646 return miscRegs[MISCREG_CPSR] & 0x1; 647 } 648 case MISCREG_CURRENTEL: 649 { 650 return miscRegs[MISCREG_CPSR] & 0xc; 651 } 652 case MISCREG_L2CTLR: 653 { 654 // mostly unimplemented, just set NumCPUs field from sim and return 655 L2CTLR l2ctlr = 0; 656 // b00:1CPU to b11:4CPUs 657 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 658 return l2ctlr; 659 } 660 case MISCREG_DBGDIDR: 661 /* For now just implement the version number. 662 * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 663 */ 664 return 0x5 << 16; 665 case MISCREG_DBGDSCRint: 666 return 0; 667 case MISCREG_ISR: 668 return tc->getCpuPtr()->getInterruptController()->getISR( 669 readMiscRegNoEffect(MISCREG_HCR), 670 readMiscRegNoEffect(MISCREG_CPSR), 671 readMiscRegNoEffect(MISCREG_SCR)); 672 case MISCREG_ISR_EL1: 673 return tc->getCpuPtr()->getInterruptController()->getISR( 674 readMiscRegNoEffect(MISCREG_HCR_EL2), 675 readMiscRegNoEffect(MISCREG_CPSR), 676 readMiscRegNoEffect(MISCREG_SCR_EL3)); 677 case MISCREG_DCZID_EL0: 678 return 0x04; // DC ZVA clear 64-byte chunks 679 case MISCREG_HCPTR: 680 { 681 MiscReg val = readMiscRegNoEffect(misc_reg); 682 // The trap bit associated with CP14 is defined as RAZ 683 val &= ~(1 << 14); 684 // If a CP bit in NSACR is 0 then the corresponding bit in 685 // HCPTR is RAO/WI 686 bool secure_lookup = haveSecurity && 687 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 688 readMiscRegNoEffect(MISCREG_CPSR)); 689 if (!secure_lookup) { 690 MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 691 val |= (mask ^ 0x7FFF) & 0xBFFF; 692 } 693 // Set the bits for unimplemented coprocessors to RAO/WI 694 val |= 0x33FF; 695 return (val); 696 } 697 case MISCREG_HDFAR: // alias for secure DFAR 698 return readMiscRegNoEffect(MISCREG_DFAR_S); 699 case MISCREG_HIFAR: // alias for secure IFAR 700 return readMiscRegNoEffect(MISCREG_IFAR_S); 701 case MISCREG_HVBAR: // bottom bits reserved 702 return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 703 case MISCREG_SCTLR: // Some bits hardwired 704 // The FI field (bit 21) is common between S/NS versions of the register 705 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 706 (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; // V8 SCTLR 707 case MISCREG_SCTLR_EL1: 708 // The FI field (bit 21) is common between S/NS versions of the register 709 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 710 (readMiscRegNoEffect(misc_reg) & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1 711 case MISCREG_SCTLR_EL3: 712 // The FI field (bit 21) is common between S/NS versions of the register 713 return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21)) | 714 (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3 715 case MISCREG_HSCTLR: // FI comes from SCTLR 716 { 717 uint32_t mask = 1 << 27; 718 return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) | 719 (readMiscRegNoEffect(MISCREG_SCTLR) & mask); 720 } 721 case MISCREG_SCR: 722 { 723 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 724 if (cpsr.width) { 725 return readMiscRegNoEffect(MISCREG_SCR); 726 } else { 727 return readMiscRegNoEffect(MISCREG_SCR_EL3); 728 } 729 } 730 // Generic Timer registers 731 case MISCREG_CNTFRQ: 732 case MISCREG_CNTFRQ_EL0: 733 inform_once("Read CNTFREQ_EL0 frequency\n"); 734 return getSystemCounter(tc)->freq(); 735 case MISCREG_CNTPCT: 736 case MISCREG_CNTPCT_EL0: 737 return getSystemCounter(tc)->value(); 738 case MISCREG_CNTVCT: 739 return getSystemCounter(tc)->value(); 740 case MISCREG_CNTVCT_EL0: 741 return getSystemCounter(tc)->value(); 742 case MISCREG_CNTP_CVAL: 743 case MISCREG_CNTP_CVAL_EL0: 744 return getArchTimer(tc, tc->cpuId())->compareValue(); 745 case MISCREG_CNTP_TVAL: 746 case MISCREG_CNTP_TVAL_EL0: 747 return getArchTimer(tc, tc->cpuId())->timerValue(); 748 case MISCREG_CNTP_CTL: 749 case MISCREG_CNTP_CTL_EL0: 750 return getArchTimer(tc, tc->cpuId())->control(); 751 // PL1 phys. timer, secure 752 // AArch64 753 // case MISCREG_CNTPS_CVAL_EL1: 754 // case MISCREG_CNTPS_TVAL_EL1: 755 // case MISCREG_CNTPS_CTL_EL1: 756 // PL2 phys. timer, non-secure 757 // AArch32 758 // case MISCREG_CNTHCTL: 759 // case MISCREG_CNTHP_CVAL: 760 // case MISCREG_CNTHP_TVAL: 761 // case MISCREG_CNTHP_CTL: 762 // AArch64 763 // case MISCREG_CNTHCTL_EL2: 764 // case MISCREG_CNTHP_CVAL_EL2: 765 // case MISCREG_CNTHP_TVAL_EL2: 766 // case MISCREG_CNTHP_CTL_EL2: 767 // Virtual timer 768 // AArch32 769 // case MISCREG_CNTV_CVAL: 770 // case MISCREG_CNTV_TVAL: 771 // case MISCREG_CNTV_CTL: 772 // AArch64 773 // case MISCREG_CNTV_CVAL_EL2: 774 // case MISCREG_CNTV_TVAL_EL2: 775 // case MISCREG_CNTV_CTL_EL2: 776 default: 777 break; 778 779 } 780 return readMiscRegNoEffect(misc_reg); 781} 782 783void 784ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 785{ 786 assert(misc_reg < NumMiscRegs); 787 788 int flat_idx = flattenMiscIndex(misc_reg); // Note: indexes of AArch64 789 // registers are left unchanged 790 791 int flat_idx2 = lookUpMiscReg[flat_idx].upper; 792 793 if (flat_idx2 > 0) { 794 miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0); 795 miscRegs[flat_idx2] = bits(val, 63, 32); 796 DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 797 misc_reg, flat_idx, flat_idx2, val); 798 } else { 799 if (flat_idx == MISCREG_SPSR) 800 flat_idx = flattenMiscIndex(MISCREG_SPSR); 801 else if (flat_idx == MISCREG_SCTLR_EL1) 802 flat_idx = flattenMiscIndex(MISCREG_SCTLR); 803 else 804 flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ? 805 lookUpMiscReg[flat_idx].lower : flat_idx; 806 miscRegs[flat_idx] = val; 807 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 808 misc_reg, flat_idx, val); 809 } 810} 811 812void 813ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 814{ 815 816 MiscReg newVal = val; 817 int x; 818 bool secure_lookup; 819 bool hyp; 820 System *sys; 821 ThreadContext *oc; 822 uint8_t target_el; 823 uint16_t asid; 824 SCR scr; 825 826 if (misc_reg == MISCREG_CPSR) { 827 updateRegMap(val); 828 829 830 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 831 int old_mode = old_cpsr.mode; 832 CPSR cpsr = val; 833 if (old_mode != cpsr.mode) { 834 tc->getITBPtr()->invalidateMiscReg(); 835 tc->getDTBPtr()->invalidateMiscReg(); 836 } 837 838 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 839 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 840 PCState pc = tc->pcState(); 841 pc.nextThumb(cpsr.t); 842 pc.nextJazelle(cpsr.j); 843 844 // Follow slightly different semantics if a CheckerCPU object 845 // is connected 846 CheckerCPU *checker = tc->getCheckerCpuPtr(); 847 if (checker) { 848 tc->pcStateNoRecord(pc); 849 } else { 850 tc->pcState(pc); 851 } 852 } else { 853#ifndef NDEBUG 854 if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 855 if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 856 warn("Unimplemented system register %s write with %#x.\n", 857 miscRegName[misc_reg], val); 858 else 859 panic("Unimplemented system register %s write with %#x.\n", 860 miscRegName[misc_reg], val); 861 } 862#endif 863 switch (unflattenMiscReg(misc_reg)) { 864 case MISCREG_CPACR: 865 { 866 867 const uint32_t ones = (uint32_t)(-1); 868 CPACR cpacrMask = 0; 869 // Only cp10, cp11, and ase are implemented, nothing else should 870 // be writable 871 cpacrMask.cp10 = ones; 872 cpacrMask.cp11 = ones; 873 cpacrMask.asedis = ones; 874 875 // Security Extensions may limit the writability of CPACR 876 if (haveSecurity) { 877 scr = readMiscRegNoEffect(MISCREG_SCR); 878 CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 879 if (scr.ns && (cpsr.mode != MODE_MON)) { 880 NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 881 // NB: Skipping the full loop, here 882 if (!nsacr.cp10) cpacrMask.cp10 = 0; 883 if (!nsacr.cp11) cpacrMask.cp11 = 0; 884 } 885 } 886 887 MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 888 newVal &= cpacrMask; 889 newVal |= old_val & ~cpacrMask; 890 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 891 miscRegName[misc_reg], newVal); 892 } 893 break; 894 case MISCREG_CPACR_EL1: 895 { 896 const uint32_t ones = (uint32_t)(-1); 897 CPACR cpacrMask = 0; 898 cpacrMask.tta = ones; 899 cpacrMask.fpen = ones; 900 newVal &= cpacrMask; 901 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 902 miscRegName[misc_reg], newVal); 903 } 904 break; 905 case MISCREG_CPTR_EL2: 906 { 907 const uint32_t ones = (uint32_t)(-1); 908 CPTR cptrMask = 0; 909 cptrMask.tcpac = ones; 910 cptrMask.tta = ones; 911 cptrMask.tfp = ones; 912 newVal &= cptrMask; 913 cptrMask = 0; 914 cptrMask.res1_13_12_el2 = ones; 915 cptrMask.res1_9_0_el2 = ones; 916 newVal |= cptrMask; 917 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 918 miscRegName[misc_reg], newVal); 919 } 920 break; 921 case MISCREG_CPTR_EL3: 922 { 923 const uint32_t ones = (uint32_t)(-1); 924 CPTR cptrMask = 0; 925 cptrMask.tcpac = ones; 926 cptrMask.tta = ones; 927 cptrMask.tfp = ones; 928 newVal &= cptrMask; 929 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 930 miscRegName[misc_reg], newVal); 931 } 932 break; 933 case MISCREG_CSSELR: 934 warn_once("The csselr register isn't implemented.\n"); 935 return; 936 937 case MISCREG_DC_ZVA_Xt: 938 warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 939 return; 940 941 case MISCREG_FPSCR: 942 { 943 const uint32_t ones = (uint32_t)(-1); 944 FPSCR fpscrMask = 0; 945 fpscrMask.ioc = ones; 946 fpscrMask.dzc = ones; 947 fpscrMask.ofc = ones; 948 fpscrMask.ufc = ones; 949 fpscrMask.ixc = ones; 950 fpscrMask.idc = ones; 951 fpscrMask.ioe = ones; 952 fpscrMask.dze = ones; 953 fpscrMask.ofe = ones; 954 fpscrMask.ufe = ones; 955 fpscrMask.ixe = ones; 956 fpscrMask.ide = ones; 957 fpscrMask.len = ones; 958 fpscrMask.stride = ones; 959 fpscrMask.rMode = ones; 960 fpscrMask.fz = ones; 961 fpscrMask.dn = ones; 962 fpscrMask.ahp = ones; 963 fpscrMask.qc = ones; 964 fpscrMask.v = ones; 965 fpscrMask.c = ones; 966 fpscrMask.z = ones; 967 fpscrMask.n = ones; 968 newVal = (newVal & (uint32_t)fpscrMask) | 969 (readMiscRegNoEffect(MISCREG_FPSCR) & 970 ~(uint32_t)fpscrMask); 971 tc->getDecoderPtr()->setContext(newVal); 972 } 973 break; 974 case MISCREG_FPSR: 975 { 976 const uint32_t ones = (uint32_t)(-1); 977 FPSCR fpscrMask = 0; 978 fpscrMask.ioc = ones; 979 fpscrMask.dzc = ones; 980 fpscrMask.ofc = ones; 981 fpscrMask.ufc = ones; 982 fpscrMask.ixc = ones; 983 fpscrMask.idc = ones; 984 fpscrMask.qc = ones; 985 fpscrMask.v = ones; 986 fpscrMask.c = ones; 987 fpscrMask.z = ones; 988 fpscrMask.n = ones; 989 newVal = (newVal & (uint32_t)fpscrMask) | 990 (readMiscRegNoEffect(MISCREG_FPSCR) & 991 ~(uint32_t)fpscrMask); 992 misc_reg = MISCREG_FPSCR; 993 } 994 break; 995 case MISCREG_FPCR: 996 { 997 const uint32_t ones = (uint32_t)(-1); 998 FPSCR fpscrMask = 0; 999 fpscrMask.ioe = ones; 1000 fpscrMask.dze = ones; 1001 fpscrMask.ofe = ones; 1002 fpscrMask.ufe = ones; 1003 fpscrMask.ixe = ones; 1004 fpscrMask.ide = ones; 1005 fpscrMask.len = ones; 1006 fpscrMask.stride = ones; 1007 fpscrMask.rMode = ones; 1008 fpscrMask.fz = ones; 1009 fpscrMask.dn = ones; 1010 fpscrMask.ahp = ones; 1011 newVal = (newVal & (uint32_t)fpscrMask) | 1012 (readMiscRegNoEffect(MISCREG_FPSCR) & 1013 ~(uint32_t)fpscrMask); 1014 misc_reg = MISCREG_FPSCR; 1015 } 1016 break; 1017 case MISCREG_CPSR_Q: 1018 { 1019 assert(!(newVal & ~CpsrMaskQ)); 1020 newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 1021 misc_reg = MISCREG_CPSR; 1022 } 1023 break; 1024 case MISCREG_FPSCR_QC: 1025 { 1026 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1027 (newVal & FpscrQcMask); 1028 misc_reg = MISCREG_FPSCR; 1029 } 1030 break; 1031 case MISCREG_FPSCR_EXC: 1032 { 1033 newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 1034 (newVal & FpscrExcMask); 1035 misc_reg = MISCREG_FPSCR; 1036 } 1037 break; 1038 case MISCREG_FPEXC: 1039 { 1040 // vfpv3 architecture, section B.6.1 of DDI04068 1041 // bit 29 - valid only if fpexc[31] is 0 1042 const uint32_t fpexcMask = 0x60000000; 1043 newVal = (newVal & fpexcMask) | 1044 (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 1045 } 1046 break; 1047 case MISCREG_HCR: 1048 { 1049 if (!haveVirtualization) 1050 return; 1051 } 1052 break; 1053 case MISCREG_IFSR: 1054 { 1055 // ARM ARM (ARM DDI 0406C.b) B4.1.96 1056 const uint32_t ifsrMask = 1057 mask(31, 13) | mask(11, 11) | mask(8, 6); 1058 newVal = newVal & ~ifsrMask; 1059 } 1060 break; 1061 case MISCREG_DFSR: 1062 { 1063 // ARM ARM (ARM DDI 0406C.b) B4.1.52 1064 const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 1065 newVal = newVal & ~dfsrMask; 1066 } 1067 break; 1068 case MISCREG_AMAIR0: 1069 case MISCREG_AMAIR1: 1070 { 1071 // ARM ARM (ARM DDI 0406C.b) B4.1.5 1072 // Valid only with LPAE 1073 if (!haveLPAE) 1074 return; 1075 DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 1076 } 1077 break; 1078 case MISCREG_SCR: 1079 tc->getITBPtr()->invalidateMiscReg(); 1080 tc->getDTBPtr()->invalidateMiscReg(); 1081 break; 1082 case MISCREG_SCTLR: 1083 { 1084 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 1085 MiscRegIndex sctlr_idx; 1086 scr = readMiscRegNoEffect(MISCREG_SCR); 1087 if (haveSecurity && !scr.ns) { 1088 sctlr_idx = MISCREG_SCTLR_S; 1089 } else { 1090 sctlr_idx = MISCREG_SCTLR_NS; 1091 // The FI field (bit 21) is common between S/NS versions 1092 // of the register, we store this in the secure copy of 1093 // the reg 1094 miscRegs[MISCREG_SCTLR_S] &= ~(1 << 21); 1095 miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21); 1096 } 1097 SCTLR sctlr = miscRegs[sctlr_idx]; 1098 SCTLR new_sctlr = newVal; 1099 new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 1100 miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 1101 tc->getITBPtr()->invalidateMiscReg(); 1102 tc->getDTBPtr()->invalidateMiscReg(); 1103 1104 if (new_sctlr.c) 1105 updateBootUncacheable(sctlr_idx, tc); 1106 return; 1107 } 1108 case MISCREG_MIDR: 1109 case MISCREG_ID_PFR0: 1110 case MISCREG_ID_PFR1: 1111 case MISCREG_ID_DFR0: 1112 case MISCREG_ID_MMFR0: 1113 case MISCREG_ID_MMFR1: 1114 case MISCREG_ID_MMFR2: 1115 case MISCREG_ID_MMFR3: 1116 case MISCREG_ID_ISAR0: 1117 case MISCREG_ID_ISAR1: 1118 case MISCREG_ID_ISAR2: 1119 case MISCREG_ID_ISAR3: 1120 case MISCREG_ID_ISAR4: 1121 case MISCREG_ID_ISAR5: 1122 1123 case MISCREG_MPIDR: 1124 case MISCREG_FPSID: 1125 case MISCREG_TLBTR: 1126 case MISCREG_MVFR0: 1127 case MISCREG_MVFR1: 1128 1129 case MISCREG_ID_AA64AFR0_EL1: 1130 case MISCREG_ID_AA64AFR1_EL1: 1131 case MISCREG_ID_AA64DFR0_EL1: 1132 case MISCREG_ID_AA64DFR1_EL1: 1133 case MISCREG_ID_AA64ISAR0_EL1: 1134 case MISCREG_ID_AA64ISAR1_EL1: 1135 case MISCREG_ID_AA64MMFR0_EL1: 1136 case MISCREG_ID_AA64MMFR1_EL1: 1137 case MISCREG_ID_AA64PFR0_EL1: 1138 case MISCREG_ID_AA64PFR1_EL1: 1139 // ID registers are constants. 1140 return; 1141 1142 // TLBI all entries, EL0&1 inner sharable (ignored) 1143 case MISCREG_TLBIALLIS: 1144 case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 1145 assert32(tc); 1146 target_el = 1; // el 0 and 1 are handled together 1147 scr = readMiscReg(MISCREG_SCR, tc); 1148 secure_lookup = haveSecurity && !scr.ns; 1149 sys = tc->getSystemPtr(); 1150 for (x = 0; x < sys->numContexts(); x++) { 1151 oc = sys->getThreadContext(x); 1152 assert(oc->getITBPtr() && oc->getDTBPtr()); 1153 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1154 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1155 1156 // If CheckerCPU is connected, need to notify it of a flush 1157 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1158 if (checker) { 1159 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1160 target_el); 1161 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1162 target_el); 1163 } 1164 } 1165 return; 1166 // TLBI all entries, EL0&1, instruction side 1167 case MISCREG_ITLBIALL: 1168 assert32(tc); 1169 target_el = 1; // el 0 and 1 are handled together 1170 scr = readMiscReg(MISCREG_SCR, tc); 1171 secure_lookup = haveSecurity && !scr.ns; 1172 tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1173 return; 1174 // TLBI all entries, EL0&1, data side 1175 case MISCREG_DTLBIALL: 1176 assert32(tc); 1177 target_el = 1; // el 0 and 1 are handled together 1178 scr = readMiscReg(MISCREG_SCR, tc); 1179 secure_lookup = haveSecurity && !scr.ns; 1180 tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1181 return; 1182 // TLBI based on VA, EL0&1 inner sharable (ignored) 1183 case MISCREG_TLBIMVAIS: 1184 case MISCREG_TLBIMVA: 1185 assert32(tc); 1186 target_el = 1; // el 0 and 1 are handled together 1187 scr = readMiscReg(MISCREG_SCR, tc); 1188 secure_lookup = haveSecurity && !scr.ns; 1189 sys = tc->getSystemPtr(); 1190 for (x = 0; x < sys->numContexts(); x++) { 1191 oc = sys->getThreadContext(x); 1192 assert(oc->getITBPtr() && oc->getDTBPtr()); 1193 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1194 bits(newVal, 7,0), 1195 secure_lookup, target_el); 1196 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1197 bits(newVal, 7,0), 1198 secure_lookup, target_el); 1199 1200 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1201 if (checker) { 1202 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1203 bits(newVal, 7,0), secure_lookup, target_el); 1204 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1205 bits(newVal, 7,0), secure_lookup, target_el); 1206 } 1207 } 1208 return; 1209 // TLBI by ASID, EL0&1, inner sharable 1210 case MISCREG_TLBIASIDIS: 1211 case MISCREG_TLBIASID: 1212 assert32(tc); 1213 target_el = 1; // el 0 and 1 are handled together 1214 scr = readMiscReg(MISCREG_SCR, tc); 1215 secure_lookup = haveSecurity && !scr.ns; 1216 sys = tc->getSystemPtr(); 1217 for (x = 0; x < sys->numContexts(); x++) { 1218 oc = sys->getThreadContext(x); 1219 assert(oc->getITBPtr() && oc->getDTBPtr()); 1220 oc->getITBPtr()->flushAsid(bits(newVal, 7,0), 1221 secure_lookup, target_el); 1222 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1223 secure_lookup, target_el); 1224 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1225 if (checker) { 1226 checker->getITBPtr()->flushAsid(bits(newVal, 7,0), 1227 secure_lookup, target_el); 1228 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0), 1229 secure_lookup, target_el); 1230 } 1231 } 1232 return; 1233 // TLBI by address, EL0&1, inner sharable (ignored) 1234 case MISCREG_TLBIMVAAIS: 1235 case MISCREG_TLBIMVAA: 1236 assert32(tc); 1237 target_el = 1; // el 0 and 1 are handled together 1238 scr = readMiscReg(MISCREG_SCR, tc); 1239 secure_lookup = haveSecurity && !scr.ns; 1240 hyp = 0; 1241 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1242 return; 1243 // TLBI by address, EL2, hypervisor mode 1244 case MISCREG_TLBIMVAH: 1245 case MISCREG_TLBIMVAHIS: 1246 assert32(tc); 1247 target_el = 1; // aarch32, use hyp bit 1248 scr = readMiscReg(MISCREG_SCR, tc); 1249 secure_lookup = haveSecurity && !scr.ns; 1250 hyp = 1; 1251 tlbiMVA(tc, newVal, secure_lookup, hyp, target_el); 1252 return; 1253 // TLBI by address and asid, EL0&1, instruction side only 1254 case MISCREG_ITLBIMVA: 1255 assert32(tc); 1256 target_el = 1; // el 0 and 1 are handled together 1257 scr = readMiscReg(MISCREG_SCR, tc); 1258 secure_lookup = haveSecurity && !scr.ns; 1259 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1260 bits(newVal, 7,0), secure_lookup, target_el); 1261 return; 1262 // TLBI by address and asid, EL0&1, data side only 1263 case MISCREG_DTLBIMVA: 1264 assert32(tc); 1265 target_el = 1; // el 0 and 1 are handled together 1266 scr = readMiscReg(MISCREG_SCR, tc); 1267 secure_lookup = haveSecurity && !scr.ns; 1268 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 1269 bits(newVal, 7,0), secure_lookup, target_el); 1270 return; 1271 // TLBI by ASID, EL0&1, instrution side only 1272 case MISCREG_ITLBIASID: 1273 assert32(tc); 1274 target_el = 1; // el 0 and 1 are handled together 1275 scr = readMiscReg(MISCREG_SCR, tc); 1276 secure_lookup = haveSecurity && !scr.ns; 1277 tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1278 target_el); 1279 return; 1280 // TLBI by ASID EL0&1 data size only 1281 case MISCREG_DTLBIASID: 1282 assert32(tc); 1283 target_el = 1; // el 0 and 1 are handled together 1284 scr = readMiscReg(MISCREG_SCR, tc); 1285 secure_lookup = haveSecurity && !scr.ns; 1286 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup, 1287 target_el); 1288 return; 1289 // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB 1290 case MISCREG_TLBIALLNSNH: 1291 case MISCREG_TLBIALLNSNHIS: 1292 assert32(tc); 1293 target_el = 1; // el 0 and 1 are handled together 1294 hyp = 0; 1295 tlbiALLN(tc, hyp, target_el); 1296 return; 1297 // TLBI all entries, EL2, hyp, 1298 case MISCREG_TLBIALLH: 1299 case MISCREG_TLBIALLHIS: 1300 assert32(tc); 1301 target_el = 1; // aarch32, use hyp bit 1302 hyp = 1; 1303 tlbiALLN(tc, hyp, target_el); 1304 return; 1305 // AArch64 TLBI: invalidate all entries EL3 1306 case MISCREG_TLBI_ALLE3IS: 1307 case MISCREG_TLBI_ALLE3: 1308 assert64(tc); 1309 target_el = 3; 1310 secure_lookup = true; 1311 tlbiALL(tc, secure_lookup, target_el); 1312 return; 1313 // @todo: uncomment this to enable Virtualization 1314 // case MISCREG_TLBI_ALLE2IS: 1315 // case MISCREG_TLBI_ALLE2: 1316 // TLBI all entries, EL0&1 1317 case MISCREG_TLBI_ALLE1IS: 1318 case MISCREG_TLBI_ALLE1: 1319 // AArch64 TLBI: invalidate all entries, stage 1, current VMID 1320 case MISCREG_TLBI_VMALLE1IS: 1321 case MISCREG_TLBI_VMALLE1: 1322 // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID 1323 case MISCREG_TLBI_VMALLS12E1IS: 1324 case MISCREG_TLBI_VMALLS12E1: 1325 // @todo: handle VMID and stage 2 to enable Virtualization 1326 assert64(tc); 1327 target_el = 1; // el 0 and 1 are handled together 1328 scr = readMiscReg(MISCREG_SCR, tc); 1329 secure_lookup = haveSecurity && !scr.ns; 1330 tlbiALL(tc, secure_lookup, target_el); 1331 return; 1332 // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID 1333 // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries 1334 // from the last level of translation table walks 1335 // @todo: handle VMID to enable Virtualization 1336 // TLBI all entries, EL0&1 1337 case MISCREG_TLBI_VAE3IS_Xt: 1338 case MISCREG_TLBI_VAE3_Xt: 1339 // TLBI by VA, EL3 regime stage 1, last level walk 1340 case MISCREG_TLBI_VALE3IS_Xt: 1341 case MISCREG_TLBI_VALE3_Xt: 1342 assert64(tc); 1343 target_el = 3; 1344 asid = 0xbeef; // does not matter, tlbi is global 1345 secure_lookup = true; 1346 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1347 return; 1348 // TLBI by VA, EL2 1349 case MISCREG_TLBI_VAE2IS_Xt: 1350 case MISCREG_TLBI_VAE2_Xt: 1351 // TLBI by VA, EL2, stage1 last level walk 1352 case MISCREG_TLBI_VALE2IS_Xt: 1353 case MISCREG_TLBI_VALE2_Xt: 1354 assert64(tc); 1355 target_el = 2; 1356 asid = 0xbeef; // does not matter, tlbi is global 1357 scr = readMiscReg(MISCREG_SCR, tc); 1358 secure_lookup = haveSecurity && !scr.ns; 1359 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1360 return; 1361 // TLBI by VA EL1 & 0, stage1, ASID, current VMID 1362 case MISCREG_TLBI_VAE1IS_Xt: 1363 case MISCREG_TLBI_VAE1_Xt: 1364 case MISCREG_TLBI_VALE1IS_Xt: 1365 case MISCREG_TLBI_VALE1_Xt: 1366 assert64(tc); 1367 asid = bits(newVal, 63, 48); 1368 target_el = 1; // el 0 and 1 are handled together 1369 scr = readMiscReg(MISCREG_SCR, tc); 1370 secure_lookup = haveSecurity && !scr.ns; 1371 tlbiVA(tc, newVal, asid, secure_lookup, target_el); 1372 return; 1373 // AArch64 TLBI: invalidate by ASID, stage 1, current VMID 1374 // @todo: handle VMID to enable Virtualization 1375 case MISCREG_TLBI_ASIDE1IS_Xt: 1376 case MISCREG_TLBI_ASIDE1_Xt: 1377 assert64(tc); 1378 target_el = 1; // el 0 and 1 are handled together 1379 scr = readMiscReg(MISCREG_SCR, tc); 1380 secure_lookup = haveSecurity && !scr.ns; 1381 sys = tc->getSystemPtr(); 1382 for (x = 0; x < sys->numContexts(); x++) { 1383 oc = sys->getThreadContext(x); 1384 assert(oc->getITBPtr() && oc->getDTBPtr()); 1385 asid = bits(newVal, 63, 48); 1386 if (haveLargeAsid64) 1387 asid &= mask(8); 1388 oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el); 1389 oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el); 1390 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1391 if (checker) { 1392 checker->getITBPtr()->flushAsid(asid, 1393 secure_lookup, target_el); 1394 checker->getDTBPtr()->flushAsid(asid, 1395 secure_lookup, target_el); 1396 } 1397 } 1398 return; 1399 // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID 1400 // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 1401 // entries from the last level of translation table walks 1402 // @todo: handle VMID to enable Virtualization 1403 case MISCREG_TLBI_VAAE1IS_Xt: 1404 case MISCREG_TLBI_VAAE1_Xt: 1405 case MISCREG_TLBI_VAALE1IS_Xt: 1406 case MISCREG_TLBI_VAALE1_Xt: 1407 assert64(tc); 1408 target_el = 1; // el 0 and 1 are handled together 1409 scr = readMiscReg(MISCREG_SCR, tc); 1410 secure_lookup = haveSecurity && !scr.ns; 1411 sys = tc->getSystemPtr(); 1412 for (x = 0; x < sys->numContexts(); x++) { 1413 // @todo: extra controls on TLBI broadcast? 1414 oc = sys->getThreadContext(x); 1415 assert(oc->getITBPtr() && oc->getDTBPtr()); 1416 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1417 oc->getITBPtr()->flushMva(va, 1418 secure_lookup, false, target_el); 1419 oc->getDTBPtr()->flushMva(va, 1420 secure_lookup, false, target_el); 1421 1422 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1423 if (checker) { 1424 checker->getITBPtr()->flushMva(va, 1425 secure_lookup, false, target_el); 1426 checker->getDTBPtr()->flushMva(va, 1427 secure_lookup, false, target_el); 1428 } 1429 } 1430 return; 1431 // AArch64 TLBI: invalidate by IPA, stage 2, current VMID 1432 case MISCREG_TLBI_IPAS2LE1IS_Xt: 1433 case MISCREG_TLBI_IPAS2LE1_Xt: 1434 case MISCREG_TLBI_IPAS2E1IS_Xt: 1435 case MISCREG_TLBI_IPAS2E1_Xt: 1436 assert64(tc); 1437 // @todo: implement these as part of Virtualization 1438 warn("Not doing anything for write of miscreg ITLB_IPAS2\n"); 1439 return; 1440 case MISCREG_ACTLR: 1441 warn("Not doing anything for write of miscreg ACTLR\n"); 1442 break; 1443 1444 case MISCREG_PMXEVTYPER_PMCCFILTR: 1445 case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 1446 case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 1447 case MISCREG_PMCR ... MISCREG_PMOVSSET: 1448 pmu->setMiscReg(misc_reg, newVal); 1449 break; 1450 1451 1452 case MISCREG_HSTR: // TJDBX, now redifined to be RES0 1453 { 1454 HSTR hstrMask = 0; 1455 hstrMask.tjdbx = 1; 1456 newVal &= ~((uint32_t) hstrMask); 1457 break; 1458 } 1459 case MISCREG_HCPTR: 1460 { 1461 // If a CP bit in NSACR is 0 then the corresponding bit in 1462 // HCPTR is RAO/WI. Same applies to NSASEDIS 1463 secure_lookup = haveSecurity && 1464 inSecureState(readMiscRegNoEffect(MISCREG_SCR), 1465 readMiscRegNoEffect(MISCREG_CPSR)); 1466 if (!secure_lookup) { 1467 MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 1468 MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 1469 newVal = (newVal & ~mask) | (oldValue & mask); 1470 } 1471 break; 1472 } 1473 case MISCREG_HDFAR: // alias for secure DFAR 1474 misc_reg = MISCREG_DFAR_S; 1475 break; 1476 case MISCREG_HIFAR: // alias for secure IFAR 1477 misc_reg = MISCREG_IFAR_S; 1478 break; 1479 case MISCREG_ATS1CPR: 1480 case MISCREG_ATS1CPW: 1481 case MISCREG_ATS1CUR: 1482 case MISCREG_ATS1CUW: 1483 case MISCREG_ATS12NSOPR: 1484 case MISCREG_ATS12NSOPW: 1485 case MISCREG_ATS12NSOUR: 1486 case MISCREG_ATS12NSOUW: 1487 case MISCREG_ATS1HR: 1488 case MISCREG_ATS1HW: 1489 { 1490 RequestPtr req = new Request; 1491 unsigned flags = 0; 1492 BaseTLB::Mode mode = BaseTLB::Read; 1493 TLB::ArmTranslationType tranType = TLB::NormalTran; 1494 Fault fault; 1495 switch(misc_reg) { 1496 case MISCREG_ATS1CPR: 1497 flags = TLB::MustBeOne; 1498 tranType = TLB::S1CTran; 1499 mode = BaseTLB::Read; 1500 break; 1501 case MISCREG_ATS1CPW: 1502 flags = TLB::MustBeOne; 1503 tranType = TLB::S1CTran; 1504 mode = BaseTLB::Write; 1505 break; 1506 case MISCREG_ATS1CUR: 1507 flags = TLB::MustBeOne | TLB::UserMode; 1508 tranType = TLB::S1CTran; 1509 mode = BaseTLB::Read; 1510 break; 1511 case MISCREG_ATS1CUW: 1512 flags = TLB::MustBeOne | TLB::UserMode; 1513 tranType = TLB::S1CTran; 1514 mode = BaseTLB::Write; 1515 break; 1516 case MISCREG_ATS12NSOPR: 1517 if (!haveSecurity) 1518 panic("Security Extensions required for ATS12NSOPR"); 1519 flags = TLB::MustBeOne; 1520 tranType = TLB::S1S2NsTran; 1521 mode = BaseTLB::Read; 1522 break; 1523 case MISCREG_ATS12NSOPW: 1524 if (!haveSecurity) 1525 panic("Security Extensions required for ATS12NSOPW"); 1526 flags = TLB::MustBeOne; 1527 tranType = TLB::S1S2NsTran; 1528 mode = BaseTLB::Write; 1529 break; 1530 case MISCREG_ATS12NSOUR: 1531 if (!haveSecurity) 1532 panic("Security Extensions required for ATS12NSOUR"); 1533 flags = TLB::MustBeOne | TLB::UserMode; 1534 tranType = TLB::S1S2NsTran; 1535 mode = BaseTLB::Read; 1536 break; 1537 case MISCREG_ATS12NSOUW: 1538 if (!haveSecurity) 1539 panic("Security Extensions required for ATS12NSOUW"); 1540 flags = TLB::MustBeOne | TLB::UserMode; 1541 tranType = TLB::S1S2NsTran; 1542 mode = BaseTLB::Write; 1543 break; 1544 case MISCREG_ATS1HR: // only really useful from secure mode. 1545 flags = TLB::MustBeOne; 1546 tranType = TLB::HypMode; 1547 mode = BaseTLB::Read; 1548 break; 1549 case MISCREG_ATS1HW: 1550 flags = TLB::MustBeOne; 1551 tranType = TLB::HypMode; 1552 mode = BaseTLB::Write; 1553 break; 1554 } 1555 // If we're in timing mode then doing the translation in 1556 // functional mode then we're slightly distorting performance 1557 // results obtained from simulations. The translation should be 1558 // done in the same mode the core is running in. NOTE: This 1559 // can't be an atomic translation because that causes problems 1560 // with unexpected atomic snoop requests. 1561 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1562 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1563 tc->pcState().pc()); 1564 req->setThreadContext(tc->contextId(), tc->threadId()); 1565 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType); 1566 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1567 HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 1568 1569 MiscReg newVal; 1570 if (fault == NoFault) { 1571 Addr paddr = req->getPaddr(); 1572 if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 1573 ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 1574 newVal = (paddr & mask(39, 12)) | 1575 (tc->getDTBPtr()->getAttr()); 1576 } else { 1577 newVal = (paddr & 0xfffff000) | 1578 (tc->getDTBPtr()->getAttr()); 1579 } 1580 DPRINTF(MiscRegs, 1581 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 1582 val, newVal); 1583 } else { 1584 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1585 // Set fault bit and FSR 1586 FSR fsr = armFault->getFsr(tc); 1587 1588 newVal = ((fsr >> 9) & 1) << 11; 1589 if (newVal) { 1590 // LPAE - rearange fault status 1591 newVal |= ((fsr >> 0) & 0x3f) << 1; 1592 } else { 1593 // VMSA - rearange fault status 1594 newVal |= ((fsr >> 0) & 0xf) << 1; 1595 newVal |= ((fsr >> 10) & 0x1) << 5; 1596 newVal |= ((fsr >> 12) & 0x1) << 6; 1597 } 1598 newVal |= 0x1; // F bit 1599 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1600 newVal |= armFault->isStage2() ? 0x200 : 0; 1601 DPRINTF(MiscRegs, 1602 "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 1603 val, fsr, newVal); 1604 } 1605 delete req; 1606 setMiscRegNoEffect(MISCREG_PAR, newVal); 1607 return; 1608 } 1609 case MISCREG_TTBCR: 1610 { 1611 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1612 const uint32_t ones = (uint32_t)(-1); 1613 TTBCR ttbcrMask = 0; 1614 TTBCR ttbcrNew = newVal; 1615 1616 // ARM DDI 0406C.b, ARMv7-32 1617 ttbcrMask.n = ones; // T0SZ 1618 if (haveSecurity) { 1619 ttbcrMask.pd0 = ones; 1620 ttbcrMask.pd1 = ones; 1621 } 1622 ttbcrMask.epd0 = ones; 1623 ttbcrMask.irgn0 = ones; 1624 ttbcrMask.orgn0 = ones; 1625 ttbcrMask.sh0 = ones; 1626 ttbcrMask.ps = ones; // T1SZ 1627 ttbcrMask.a1 = ones; 1628 ttbcrMask.epd1 = ones; 1629 ttbcrMask.irgn1 = ones; 1630 ttbcrMask.orgn1 = ones; 1631 ttbcrMask.sh1 = ones; 1632 if (haveLPAE) 1633 ttbcrMask.eae = ones; 1634 1635 if (haveLPAE && ttbcrNew.eae) { 1636 newVal = newVal & ttbcrMask; 1637 } else { 1638 newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 1639 } 1640 } 1641 case MISCREG_TTBR0: 1642 case MISCREG_TTBR1: 1643 { 1644 TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 1645 if (haveLPAE) { 1646 if (ttbcr.eae) { 1647 // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 1648 // ARMv8 AArch32 bit 63-56 only 1649 uint64_t ttbrMask = mask(63,56) | mask(47,40); 1650 newVal = (newVal & (~ttbrMask)); 1651 } 1652 } 1653 } 1654 case MISCREG_SCTLR_EL1: 1655 { 1656 tc->getITBPtr()->invalidateMiscReg(); 1657 tc->getDTBPtr()->invalidateMiscReg(); 1658 SCTLR new_sctlr = newVal; 1659 setMiscRegNoEffect(misc_reg, newVal); 1660 if (new_sctlr.c) 1661 updateBootUncacheable(misc_reg, tc); 1662 return; 1663 } 1664 case MISCREG_CONTEXTIDR: 1665 case MISCREG_PRRR: 1666 case MISCREG_NMRR: 1667 case MISCREG_MAIR0: 1668 case MISCREG_MAIR1: 1669 case MISCREG_DACR: 1670 case MISCREG_VTTBR: 1671 case MISCREG_SCR_EL3: 1672 case MISCREG_TCR_EL1: 1673 case MISCREG_TCR_EL2: 1674 case MISCREG_TCR_EL3: 1675 case MISCREG_SCTLR_EL2: 1676 case MISCREG_SCTLR_EL3: 1677 case MISCREG_TTBR0_EL1: 1678 case MISCREG_TTBR1_EL1: 1679 case MISCREG_TTBR0_EL2: 1680 case MISCREG_TTBR0_EL3: 1681 tc->getITBPtr()->invalidateMiscReg(); 1682 tc->getDTBPtr()->invalidateMiscReg(); 1683 break; 1684 case MISCREG_NZCV: 1685 { 1686 CPSR cpsr = val; 1687 1688 tc->setCCReg(CCREG_NZ, cpsr.nz); 1689 tc->setCCReg(CCREG_C, cpsr.c); 1690 tc->setCCReg(CCREG_V, cpsr.v); 1691 } 1692 break; 1693 case MISCREG_DAIF: 1694 { 1695 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1696 cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 1697 newVal = cpsr; 1698 misc_reg = MISCREG_CPSR; 1699 } 1700 break; 1701 case MISCREG_SP_EL0: 1702 tc->setIntReg(INTREG_SP0, newVal); 1703 break; 1704 case MISCREG_SP_EL1: 1705 tc->setIntReg(INTREG_SP1, newVal); 1706 break; 1707 case MISCREG_SP_EL2: 1708 tc->setIntReg(INTREG_SP2, newVal); 1709 break; 1710 case MISCREG_SPSEL: 1711 { 1712 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1713 cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 1714 newVal = cpsr; 1715 misc_reg = MISCREG_CPSR; 1716 } 1717 break; 1718 case MISCREG_CURRENTEL: 1719 { 1720 CPSR cpsr = miscRegs[MISCREG_CPSR]; 1721 cpsr.el = (uint8_t) ((CPSR) newVal).el; 1722 newVal = cpsr; 1723 misc_reg = MISCREG_CPSR; 1724 } 1725 break; 1726 case MISCREG_AT_S1E1R_Xt: 1727 case MISCREG_AT_S1E1W_Xt: 1728 case MISCREG_AT_S1E0R_Xt: 1729 case MISCREG_AT_S1E0W_Xt: 1730 case MISCREG_AT_S1E2R_Xt: 1731 case MISCREG_AT_S1E2W_Xt: 1732 case MISCREG_AT_S12E1R_Xt: 1733 case MISCREG_AT_S12E1W_Xt: 1734 case MISCREG_AT_S12E0R_Xt: 1735 case MISCREG_AT_S12E0W_Xt: 1736 case MISCREG_AT_S1E3R_Xt: 1737 case MISCREG_AT_S1E3W_Xt: 1738 { 1739 RequestPtr req = new Request; 1740 unsigned flags = 0; 1741 BaseTLB::Mode mode = BaseTLB::Read; 1742 TLB::ArmTranslationType tranType = TLB::NormalTran; 1743 Fault fault; 1744 switch(misc_reg) { 1745 case MISCREG_AT_S1E1R_Xt: 1746 flags = TLB::MustBeOne; 1747 tranType = TLB::S1CTran; 1748 mode = BaseTLB::Read; 1749 break; 1750 case MISCREG_AT_S1E1W_Xt: 1751 flags = TLB::MustBeOne; 1752 tranType = TLB::S1CTran; 1753 mode = BaseTLB::Write; 1754 break; 1755 case MISCREG_AT_S1E0R_Xt: 1756 flags = TLB::MustBeOne | TLB::UserMode; 1757 tranType = TLB::S1CTran; 1758 mode = BaseTLB::Read; 1759 break; 1760 case MISCREG_AT_S1E0W_Xt: 1761 flags = TLB::MustBeOne | TLB::UserMode; 1762 tranType = TLB::S1CTran; 1763 mode = BaseTLB::Write; 1764 break; 1765 case MISCREG_AT_S1E2R_Xt: 1766 flags = TLB::MustBeOne; 1767 tranType = TLB::HypMode; 1768 mode = BaseTLB::Read; 1769 break; 1770 case MISCREG_AT_S1E2W_Xt: 1771 flags = TLB::MustBeOne; 1772 tranType = TLB::HypMode; 1773 mode = BaseTLB::Write; 1774 break; 1775 case MISCREG_AT_S12E0R_Xt: 1776 flags = TLB::MustBeOne | TLB::UserMode; 1777 tranType = TLB::S1S2NsTran; 1778 mode = BaseTLB::Read; 1779 break; 1780 case MISCREG_AT_S12E0W_Xt: 1781 flags = TLB::MustBeOne | TLB::UserMode; 1782 tranType = TLB::S1S2NsTran; 1783 mode = BaseTLB::Write; 1784 break; 1785 case MISCREG_AT_S12E1R_Xt: 1786 flags = TLB::MustBeOne; 1787 tranType = TLB::S1S2NsTran; 1788 mode = BaseTLB::Read; 1789 break; 1790 case MISCREG_AT_S12E1W_Xt: 1791 flags = TLB::MustBeOne; 1792 tranType = TLB::S1S2NsTran; 1793 mode = BaseTLB::Write; 1794 break; 1795 case MISCREG_AT_S1E3R_Xt: 1796 flags = TLB::MustBeOne; 1797 tranType = TLB::HypMode; // There is no TZ mode defined. 1798 mode = BaseTLB::Read; 1799 break; 1800 case MISCREG_AT_S1E3W_Xt: 1801 flags = TLB::MustBeOne; 1802 tranType = TLB::HypMode; // There is no TZ mode defined. 1803 mode = BaseTLB::Write; 1804 break; 1805 } 1806 // If we're in timing mode then doing the translation in 1807 // functional mode then we're slightly distorting performance 1808 // results obtained from simulations. The translation should be 1809 // done in the same mode the core is running in. NOTE: This 1810 // can't be an atomic translation because that causes problems 1811 // with unexpected atomic snoop requests. 1812 warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 1813 req->setVirt(0, val, 1, flags, Request::funcMasterId, 1814 tc->pcState().pc()); 1815 req->setThreadContext(tc->contextId(), tc->threadId()); 1816 fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, 1817 tranType); 1818 1819 MiscReg newVal; 1820 if (fault == NoFault) { 1821 Addr paddr = req->getPaddr(); 1822 uint64_t attr = tc->getDTBPtr()->getAttr(); 1823 uint64_t attr1 = attr >> 56; 1824 if (!attr1 || attr1 ==0x44) { 1825 attr |= 0x100; 1826 attr &= ~ uint64_t(0x80); 1827 } 1828 newVal = (paddr & mask(47, 12)) | attr; 1829 DPRINTF(MiscRegs, 1830 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1831 val, newVal); 1832 } else { 1833 ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get()); 1834 // Set fault bit and FSR 1835 FSR fsr = armFault->getFsr(tc); 1836 1837 newVal = ((fsr >> 9) & 1) << 11; 1838 // rearange fault status 1839 newVal |= ((fsr >> 0) & 0x3f) << 1; 1840 newVal |= 0x1; // F bit 1841 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 1842 newVal |= armFault->isStage2() ? 0x200 : 0; 1843 DPRINTF(MiscRegs, 1844 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 1845 val, fsr, newVal); 1846 } 1847 delete req; 1848 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 1849 return; 1850 } 1851 case MISCREG_SPSR_EL3: 1852 case MISCREG_SPSR_EL2: 1853 case MISCREG_SPSR_EL1: 1854 // Force bits 23:21 to 0 1855 newVal = val & ~(0x7 << 21); 1856 break; 1857 case MISCREG_L2CTLR: 1858 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 1859 miscRegName[misc_reg], uint32_t(val)); 1860 break; 1861 1862 // Generic Timer registers 1863 case MISCREG_CNTFRQ: 1864 case MISCREG_CNTFRQ_EL0: 1865 getSystemCounter(tc)->setFreq(val); 1866 break; 1867 case MISCREG_CNTP_CVAL: 1868 case MISCREG_CNTP_CVAL_EL0: 1869 getArchTimer(tc, tc->cpuId())->setCompareValue(val); 1870 break; 1871 case MISCREG_CNTP_TVAL: 1872 case MISCREG_CNTP_TVAL_EL0: 1873 getArchTimer(tc, tc->cpuId())->setTimerValue(val); 1874 break; 1875 case MISCREG_CNTP_CTL: 1876 case MISCREG_CNTP_CTL_EL0: 1877 getArchTimer(tc, tc->cpuId())->setControl(val); 1878 break; 1879 // PL1 phys. timer, secure 1880 // AArch64 1881 case MISCREG_CNTPS_CVAL_EL1: 1882 case MISCREG_CNTPS_TVAL_EL1: 1883 case MISCREG_CNTPS_CTL_EL1: 1884 // PL2 phys. timer, non-secure 1885 // AArch32 1886 case MISCREG_CNTHCTL: 1887 case MISCREG_CNTHP_CVAL: 1888 case MISCREG_CNTHP_TVAL: 1889 case MISCREG_CNTHP_CTL: 1890 // AArch64 1891 case MISCREG_CNTHCTL_EL2: 1892 case MISCREG_CNTHP_CVAL_EL2: 1893 case MISCREG_CNTHP_TVAL_EL2: 1894 case MISCREG_CNTHP_CTL_EL2: 1895 // Virtual timer 1896 // AArch32 1897 case MISCREG_CNTV_CVAL: 1898 case MISCREG_CNTV_TVAL: 1899 case MISCREG_CNTV_CTL: 1900 // AArch64 1901 // case MISCREG_CNTV_CVAL_EL2: 1902 // case MISCREG_CNTV_TVAL_EL2: 1903 // case MISCREG_CNTV_CTL_EL2: 1904 break; 1905 } 1906 } 1907 setMiscRegNoEffect(misc_reg, newVal); 1908} 1909 1910void 1911ISA::updateBootUncacheable(int sctlr_idx, ThreadContext *tc) 1912{ 1913 System *sys; 1914 ThreadContext *oc; 1915 1916 // Check if all CPUs are booted with caches enabled 1917 // so we can stop enforcing coherency of some kernel 1918 // structures manually. 1919 sys = tc->getSystemPtr(); 1920 for (int x = 0; x < sys->numContexts(); x++) { 1921 oc = sys->getThreadContext(x); 1922 // @todo: double check this for security 1923 SCTLR other_sctlr = oc->readMiscRegNoEffect(sctlr_idx); 1924 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 1925 return; 1926 } 1927 1928 for (int x = 0; x < sys->numContexts(); x++) { 1929 oc = sys->getThreadContext(x); 1930 oc->getDTBPtr()->allCpusCaching(); 1931 oc->getITBPtr()->allCpusCaching(); 1932 1933 // If CheckerCPU is connected, need to notify it. 1934 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1935 if (checker) { 1936 checker->getDTBPtr()->allCpusCaching(); 1937 checker->getITBPtr()->allCpusCaching(); 1938 } 1939 } 1940} 1941 1942void 1943ISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup, 1944 uint8_t target_el) 1945{ 1946 if (haveLargeAsid64) 1947 asid &= mask(8); 1948 Addr va = ((Addr) bits(newVal, 43, 0)) << 12; 1949 System *sys = tc->getSystemPtr(); 1950 for (int x = 0; x < sys->numContexts(); x++) { 1951 ThreadContext *oc = sys->getThreadContext(x); 1952 assert(oc->getITBPtr() && oc->getDTBPtr()); 1953 oc->getITBPtr()->flushMvaAsid(va, asid, 1954 secure_lookup, target_el); 1955 oc->getDTBPtr()->flushMvaAsid(va, asid, 1956 secure_lookup, target_el); 1957 1958 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1959 if (checker) { 1960 checker->getITBPtr()->flushMvaAsid( 1961 va, asid, secure_lookup, target_el); 1962 checker->getDTBPtr()->flushMvaAsid( 1963 va, asid, secure_lookup, target_el); 1964 } 1965 } 1966} 1967 1968void 1969ISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el) 1970{ 1971 System *sys = tc->getSystemPtr(); 1972 for (int x = 0; x < sys->numContexts(); x++) { 1973 ThreadContext *oc = sys->getThreadContext(x); 1974 assert(oc->getITBPtr() && oc->getDTBPtr()); 1975 oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el); 1976 oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el); 1977 1978 // If CheckerCPU is connected, need to notify it of a flush 1979 CheckerCPU *checker = oc->getCheckerCpuPtr(); 1980 if (checker) { 1981 checker->getITBPtr()->flushAllSecurity(secure_lookup, 1982 target_el); 1983 checker->getDTBPtr()->flushAllSecurity(secure_lookup, 1984 target_el); 1985 } 1986 } 1987} 1988 1989void 1990ISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el) 1991{ 1992 System *sys = tc->getSystemPtr(); 1993 for (int x = 0; x < sys->numContexts(); x++) { 1994 ThreadContext *oc = sys->getThreadContext(x); 1995 assert(oc->getITBPtr() && oc->getDTBPtr()); 1996 oc->getITBPtr()->flushAllNs(hyp, target_el); 1997 oc->getDTBPtr()->flushAllNs(hyp, target_el); 1998 1999 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2000 if (checker) { 2001 checker->getITBPtr()->flushAllNs(hyp, target_el); 2002 checker->getDTBPtr()->flushAllNs(hyp, target_el); 2003 } 2004 } 2005} 2006 2007void 2008ISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp, 2009 uint8_t target_el) 2010{ 2011 System *sys = tc->getSystemPtr(); 2012 for (int x = 0; x < sys->numContexts(); x++) { 2013 ThreadContext *oc = sys->getThreadContext(x); 2014 assert(oc->getITBPtr() && oc->getDTBPtr()); 2015 oc->getITBPtr()->flushMva(mbits(newVal, 31,12), 2016 secure_lookup, hyp, target_el); 2017 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2018 secure_lookup, hyp, target_el); 2019 2020 CheckerCPU *checker = oc->getCheckerCpuPtr(); 2021 if (checker) { 2022 checker->getITBPtr()->flushMva(mbits(newVal, 31,12), 2023 secure_lookup, hyp, target_el); 2024 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12), 2025 secure_lookup, hyp, target_el); 2026 } 2027 } 2028} 2029 2030::GenericTimer::SystemCounter * 2031ISA::getSystemCounter(ThreadContext *tc) 2032{ 2033 ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())-> 2034 getSystemCounter(); 2035 if (cnt == NULL) { 2036 panic("System counter not available\n"); 2037 } 2038 return cnt; 2039} 2040 2041::GenericTimer::ArchTimer * 2042ISA::getArchTimer(ThreadContext *tc, int cpu_id) 2043{ 2044 ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())-> 2045 getArchTimer(cpu_id); 2046 if (timer == NULL) { 2047 panic("Architected timer not available\n"); 2048 } 2049 return timer; 2050} 2051 2052} 2053 2054ArmISA::ISA * 2055ArmISAParams::create() 2056{ 2057 return new ArmISA::ISA(this); 2058} 2059