isa.cc revision 10035:2a0fbecfeb14
1/* 2 * Copyright (c) 2010-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 * Ali Saidi 39 */ 40 41#include "arch/arm/isa.hh" 42#include "arch/arm/system.hh" 43#include "cpu/checker/cpu.hh" 44#include "debug/Arm.hh" 45#include "debug/MiscRegs.hh" 46#include "params/ArmISA.hh" 47#include "sim/faults.hh" 48#include "sim/stat_control.hh" 49#include "sim/system.hh" 50 51namespace ArmISA 52{ 53 54ISA::ISA(Params *p) 55 : SimObject(p) 56{ 57 SCTLR sctlr; 58 sctlr = 0; 59 miscRegs[MISCREG_SCTLR_RST] = sctlr; 60 clear(); 61} 62 63const ArmISAParams * 64ISA::params() const 65{ 66 return dynamic_cast<const Params *>(_params); 67} 68 69void 70ISA::clear() 71{ 72 const Params *p(params()); 73 74 SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 75 memset(miscRegs, 0, sizeof(miscRegs)); 76 CPSR cpsr = 0; 77 cpsr.mode = MODE_USER; 78 miscRegs[MISCREG_CPSR] = cpsr; 79 updateRegMap(cpsr); 80 81 SCTLR sctlr = 0; 82 sctlr.te = (bool)sctlr_rst.te; 83 sctlr.nmfi = (bool)sctlr_rst.nmfi; 84 sctlr.v = (bool)sctlr_rst.v; 85 sctlr.u = 1; 86 sctlr.xp = 1; 87 sctlr.rao2 = 1; 88 sctlr.rao3 = 1; 89 sctlr.rao4 = 1; 90 miscRegs[MISCREG_SCTLR] = sctlr; 91 miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 92 93 /* Start with an event in the mailbox */ 94 miscRegs[MISCREG_SEV_MAILBOX] = 1; 95 96 // Separate Instruction and Data TLBs. 97 miscRegs[MISCREG_TLBTR] = 1; 98 99 MVFR0 mvfr0 = 0; 100 mvfr0.advSimdRegisters = 2; 101 mvfr0.singlePrecision = 2; 102 mvfr0.doublePrecision = 2; 103 mvfr0.vfpExceptionTrapping = 0; 104 mvfr0.divide = 1; 105 mvfr0.squareRoot = 1; 106 mvfr0.shortVectors = 1; 107 mvfr0.roundingModes = 1; 108 miscRegs[MISCREG_MVFR0] = mvfr0; 109 110 MVFR1 mvfr1 = 0; 111 mvfr1.flushToZero = 1; 112 mvfr1.defaultNaN = 1; 113 mvfr1.advSimdLoadStore = 1; 114 mvfr1.advSimdInteger = 1; 115 mvfr1.advSimdSinglePrecision = 1; 116 mvfr1.advSimdHalfPrecision = 1; 117 mvfr1.vfpHalfPrecision = 1; 118 miscRegs[MISCREG_MVFR1] = mvfr1; 119 120 // Reset values of PRRR and NMRR are implementation dependent 121 122 miscRegs[MISCREG_PRRR] = 123 (1 << 19) | // 19 124 (0 << 18) | // 18 125 (0 << 17) | // 17 126 (1 << 16) | // 16 127 (2 << 14) | // 15:14 128 (0 << 12) | // 13:12 129 (2 << 10) | // 11:10 130 (2 << 8) | // 9:8 131 (2 << 6) | // 7:6 132 (2 << 4) | // 5:4 133 (1 << 2) | // 3:2 134 0; // 1:0 135 miscRegs[MISCREG_NMRR] = 136 (1 << 30) | // 31:30 137 (0 << 26) | // 27:26 138 (0 << 24) | // 25:24 139 (3 << 22) | // 23:22 140 (2 << 20) | // 21:20 141 (0 << 18) | // 19:18 142 (0 << 16) | // 17:16 143 (1 << 14) | // 15:14 144 (0 << 12) | // 13:12 145 (2 << 10) | // 11:10 146 (0 << 8) | // 9:8 147 (3 << 6) | // 7:6 148 (2 << 4) | // 5:4 149 (0 << 2) | // 3:2 150 0; // 1:0 151 152 miscRegs[MISCREG_CPACR] = 0; 153 154 // Initialize configurable default values 155 miscRegs[MISCREG_MIDR] = p->midr; 156 157 miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 158 miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 159 160 miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 161 miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 162 miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 163 miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 164 165 miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 166 miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 167 miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 168 miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 169 miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 170 miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 171 172 173 miscRegs[MISCREG_FPSID] = p->fpsid; 174 175 176 //XXX We need to initialize the rest of the state. 177} 178 179MiscReg 180ISA::readMiscRegNoEffect(int misc_reg) const 181{ 182 assert(misc_reg < NumMiscRegs); 183 184 int flat_idx; 185 if (misc_reg == MISCREG_SPSR) 186 flat_idx = flattenMiscIndex(misc_reg); 187 else 188 flat_idx = misc_reg; 189 MiscReg val = miscRegs[flat_idx]; 190 191 DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 192 misc_reg, flat_idx, val); 193 return val; 194} 195 196 197MiscReg 198ISA::readMiscReg(int misc_reg, ThreadContext *tc) 199{ 200 ArmSystem *arm_sys; 201 202 if (misc_reg == MISCREG_CPSR) { 203 CPSR cpsr = miscRegs[misc_reg]; 204 PCState pc = tc->pcState(); 205 cpsr.j = pc.jazelle() ? 1 : 0; 206 cpsr.t = pc.thumb() ? 1 : 0; 207 return cpsr; 208 } 209 if (misc_reg >= MISCREG_CP15_UNIMP_START) 210 panic("Unimplemented CP15 register %s read.\n", 211 miscRegName[misc_reg]); 212 213 switch (misc_reg) { 214 case MISCREG_MPIDR: 215 arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 216 assert(arm_sys); 217 218 if (arm_sys->multiProc) { 219 return 0x80000000 | // multiprocessor extensions available 220 tc->cpuId(); 221 } else { 222 return 0x80000000 | // multiprocessor extensions available 223 0x40000000 | // in up system 224 tc->cpuId(); 225 } 226 break; 227 case MISCREG_CLIDR: 228 warn_once("The clidr register always reports 0 caches.\n"); 229 warn_once("clidr LoUIS field of 0b001 to match current " 230 "ARM implementations.\n"); 231 return 0x00200000; 232 case MISCREG_CCSIDR: 233 warn_once("The ccsidr register isn't implemented and " 234 "always reads as 0.\n"); 235 break; 236 case MISCREG_CTR: 237 { 238 //all caches have the same line size in gem5 239 //4 byte words in ARM 240 unsigned lineSizeWords = 241 tc->getSystemPtr()->cacheLineSize() / 4; 242 unsigned log2LineSizeWords = 0; 243 244 while (lineSizeWords >>= 1) { 245 ++log2LineSizeWords; 246 } 247 248 CTR ctr = 0; 249 //log2 of minimun i-cache line size (words) 250 ctr.iCacheLineSize = log2LineSizeWords; 251 //b11 - gem5 uses pipt 252 ctr.l1IndexPolicy = 0x3; 253 //log2 of minimum d-cache line size (words) 254 ctr.dCacheLineSize = log2LineSizeWords; 255 //log2 of max reservation size (words) 256 ctr.erg = log2LineSizeWords; 257 //log2 of max writeback size (words) 258 ctr.cwg = log2LineSizeWords; 259 //b100 - gem5 format is ARMv7 260 ctr.format = 0x4; 261 262 return ctr; 263 } 264 case MISCREG_ACTLR: 265 warn("Not doing anything for miscreg ACTLR\n"); 266 break; 267 case MISCREG_PMCR: 268 case MISCREG_PMCCNTR: 269 case MISCREG_PMSELR: 270 warn("Not doing anything for read to miscreg %s\n", 271 miscRegName[misc_reg]); 272 break; 273 case MISCREG_CPSR_Q: 274 panic("shouldn't be reading this register seperately\n"); 275 case MISCREG_FPSCR_QC: 276 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 277 case MISCREG_FPSCR_EXC: 278 return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 279 case MISCREG_L2CTLR: 280 { 281 // mostly unimplemented, just set NumCPUs field from sim and return 282 L2CTLR l2ctlr = 0; 283 // b00:1CPU to b11:4CPUs 284 l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 285 return l2ctlr; 286 } 287 case MISCREG_DBGDIDR: 288 /* For now just implement the version number. 289 * Return 0 as we don't support debug architecture yet. 290 */ 291 return 0; 292 case MISCREG_DBGDSCR_INT: 293 return 0; 294 } 295 return readMiscRegNoEffect(misc_reg); 296} 297 298void 299ISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 300{ 301 assert(misc_reg < NumMiscRegs); 302 303 int flat_idx; 304 if (misc_reg == MISCREG_SPSR) 305 flat_idx = flattenMiscIndex(misc_reg); 306 else 307 flat_idx = misc_reg; 308 miscRegs[flat_idx] = val; 309 310 DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 311 flat_idx, val); 312} 313 314void 315ISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 316{ 317 318 MiscReg newVal = val; 319 int x; 320 System *sys; 321 ThreadContext *oc; 322 323 if (misc_reg == MISCREG_CPSR) { 324 updateRegMap(val); 325 326 327 CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 328 int old_mode = old_cpsr.mode; 329 CPSR cpsr = val; 330 if (old_mode != cpsr.mode) { 331 tc->getITBPtr()->invalidateMiscReg(); 332 tc->getDTBPtr()->invalidateMiscReg(); 333 } 334 335 DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 336 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 337 PCState pc = tc->pcState(); 338 pc.nextThumb(cpsr.t); 339 pc.nextJazelle(cpsr.j); 340 341 // Follow slightly different semantics if a CheckerCPU object 342 // is connected 343 CheckerCPU *checker = tc->getCheckerCpuPtr(); 344 if (checker) { 345 tc->pcStateNoRecord(pc); 346 } else { 347 tc->pcState(pc); 348 } 349 } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 350 misc_reg < MISCREG_CP15_END) { 351 panic("Unimplemented CP15 register %s wrote with %#x.\n", 352 miscRegName[misc_reg], val); 353 } else { 354 switch (misc_reg) { 355 case MISCREG_CPACR: 356 { 357 358 const uint32_t ones = (uint32_t)(-1); 359 CPACR cpacrMask = 0; 360 // Only cp10, cp11, and ase are implemented, nothing else should 361 // be writable 362 cpacrMask.cp10 = ones; 363 cpacrMask.cp11 = ones; 364 cpacrMask.asedis = ones; 365 newVal &= cpacrMask; 366 DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 367 miscRegName[misc_reg], newVal); 368 } 369 break; 370 case MISCREG_CSSELR: 371 warn_once("The csselr register isn't implemented.\n"); 372 return; 373 case MISCREG_FPSCR: 374 { 375 const uint32_t ones = (uint32_t)(-1); 376 FPSCR fpscrMask = 0; 377 fpscrMask.ioc = ones; 378 fpscrMask.dzc = ones; 379 fpscrMask.ofc = ones; 380 fpscrMask.ufc = ones; 381 fpscrMask.ixc = ones; 382 fpscrMask.idc = ones; 383 fpscrMask.len = ones; 384 fpscrMask.stride = ones; 385 fpscrMask.rMode = ones; 386 fpscrMask.fz = ones; 387 fpscrMask.dn = ones; 388 fpscrMask.ahp = ones; 389 fpscrMask.qc = ones; 390 fpscrMask.v = ones; 391 fpscrMask.c = ones; 392 fpscrMask.z = ones; 393 fpscrMask.n = ones; 394 newVal = (newVal & (uint32_t)fpscrMask) | 395 (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 396 tc->getDecoderPtr()->setContext(newVal); 397 } 398 break; 399 case MISCREG_CPSR_Q: 400 { 401 assert(!(newVal & ~CpsrMaskQ)); 402 newVal = miscRegs[MISCREG_CPSR] | newVal; 403 misc_reg = MISCREG_CPSR; 404 } 405 break; 406 case MISCREG_FPSCR_QC: 407 { 408 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 409 misc_reg = MISCREG_FPSCR; 410 } 411 break; 412 case MISCREG_FPSCR_EXC: 413 { 414 newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 415 misc_reg = MISCREG_FPSCR; 416 } 417 break; 418 case MISCREG_FPEXC: 419 { 420 // vfpv3 architecture, section B.6.1 of DDI04068 421 // bit 29 - valid only if fpexc[31] is 0 422 const uint32_t fpexcMask = 0x60000000; 423 newVal = (newVal & fpexcMask) | 424 (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 425 } 426 break; 427 case MISCREG_SCTLR: 428 { 429 DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 430 SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 431 SCTLR new_sctlr = newVal; 432 new_sctlr.nmfi = (bool)sctlr.nmfi; 433 miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 434 tc->getITBPtr()->invalidateMiscReg(); 435 tc->getDTBPtr()->invalidateMiscReg(); 436 437 // Check if all CPUs are booted with caches enabled 438 // so we can stop enforcing coherency of some kernel 439 // structures manually. 440 sys = tc->getSystemPtr(); 441 for (x = 0; x < sys->numContexts(); x++) { 442 oc = sys->getThreadContext(x); 443 SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 444 if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 445 return; 446 } 447 448 for (x = 0; x < sys->numContexts(); x++) { 449 oc = sys->getThreadContext(x); 450 oc->getDTBPtr()->allCpusCaching(); 451 oc->getITBPtr()->allCpusCaching(); 452 453 // If CheckerCPU is connected, need to notify it. 454 CheckerCPU *checker = oc->getCheckerCpuPtr(); 455 if (checker) { 456 checker->getDTBPtr()->allCpusCaching(); 457 checker->getITBPtr()->allCpusCaching(); 458 } 459 } 460 return; 461 } 462 463 case MISCREG_MIDR: 464 case MISCREG_ID_PFR0: 465 case MISCREG_ID_PFR1: 466 case MISCREG_ID_MMFR0: 467 case MISCREG_ID_MMFR1: 468 case MISCREG_ID_MMFR2: 469 case MISCREG_ID_MMFR3: 470 case MISCREG_ID_ISAR0: 471 case MISCREG_ID_ISAR1: 472 case MISCREG_ID_ISAR2: 473 case MISCREG_ID_ISAR3: 474 case MISCREG_ID_ISAR4: 475 case MISCREG_ID_ISAR5: 476 477 case MISCREG_MPIDR: 478 case MISCREG_FPSID: 479 case MISCREG_TLBTR: 480 case MISCREG_MVFR0: 481 case MISCREG_MVFR1: 482 // ID registers are constants. 483 return; 484 485 case MISCREG_TLBIALLIS: 486 case MISCREG_TLBIALL: 487 sys = tc->getSystemPtr(); 488 for (x = 0; x < sys->numContexts(); x++) { 489 oc = sys->getThreadContext(x); 490 assert(oc->getITBPtr() && oc->getDTBPtr()); 491 oc->getITBPtr()->flushAll(); 492 oc->getDTBPtr()->flushAll(); 493 494 // If CheckerCPU is connected, need to notify it of a flush 495 CheckerCPU *checker = oc->getCheckerCpuPtr(); 496 if (checker) { 497 checker->getITBPtr()->flushAll(); 498 checker->getDTBPtr()->flushAll(); 499 } 500 } 501 return; 502 case MISCREG_ITLBIALL: 503 tc->getITBPtr()->flushAll(); 504 return; 505 case MISCREG_DTLBIALL: 506 tc->getDTBPtr()->flushAll(); 507 return; 508 case MISCREG_TLBIMVAIS: 509 case MISCREG_TLBIMVA: 510 sys = tc->getSystemPtr(); 511 for (x = 0; x < sys->numContexts(); x++) { 512 oc = sys->getThreadContext(x); 513 assert(oc->getITBPtr() && oc->getDTBPtr()); 514 oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 515 bits(newVal, 7,0)); 516 oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 517 bits(newVal, 7,0)); 518 519 CheckerCPU *checker = oc->getCheckerCpuPtr(); 520 if (checker) { 521 checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 522 bits(newVal, 7,0)); 523 checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 524 bits(newVal, 7,0)); 525 } 526 } 527 return; 528 case MISCREG_TLBIASIDIS: 529 case MISCREG_TLBIASID: 530 sys = tc->getSystemPtr(); 531 for (x = 0; x < sys->numContexts(); x++) { 532 oc = sys->getThreadContext(x); 533 assert(oc->getITBPtr() && oc->getDTBPtr()); 534 oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 535 oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 536 CheckerCPU *checker = oc->getCheckerCpuPtr(); 537 if (checker) { 538 checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 539 checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 540 } 541 } 542 return; 543 case MISCREG_TLBIMVAAIS: 544 case MISCREG_TLBIMVAA: 545 sys = tc->getSystemPtr(); 546 for (x = 0; x < sys->numContexts(); x++) { 547 oc = sys->getThreadContext(x); 548 assert(oc->getITBPtr() && oc->getDTBPtr()); 549 oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 550 oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 551 552 CheckerCPU *checker = oc->getCheckerCpuPtr(); 553 if (checker) { 554 checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 555 checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 556 } 557 } 558 return; 559 case MISCREG_ITLBIMVA: 560 tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 561 bits(newVal, 7,0)); 562 return; 563 case MISCREG_DTLBIMVA: 564 tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 565 bits(newVal, 7,0)); 566 return; 567 case MISCREG_ITLBIASID: 568 tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 569 return; 570 case MISCREG_DTLBIASID: 571 tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 572 return; 573 case MISCREG_ACTLR: 574 warn("Not doing anything for write of miscreg ACTLR\n"); 575 break; 576 case MISCREG_PMCR: 577 { 578 // Performance counters not implemented. Instead, interpret 579 // a reset command to this register to reset the simulator 580 // statistics. 581 // PMCR_E | PMCR_P | PMCR_C 582 const int ResetAndEnableCounters = 0x7; 583 if (newVal == ResetAndEnableCounters) { 584 inform("Resetting all simobject stats\n"); 585 Stats::schedStatEvent(false, true); 586 break; 587 } 588 } 589 case MISCREG_PMCCNTR: 590 case MISCREG_PMSELR: 591 warn("Not doing anything for write to miscreg %s\n", 592 miscRegName[misc_reg]); 593 break; 594 case MISCREG_V2PCWPR: 595 case MISCREG_V2PCWPW: 596 case MISCREG_V2PCWUR: 597 case MISCREG_V2PCWUW: 598 case MISCREG_V2POWPR: 599 case MISCREG_V2POWPW: 600 case MISCREG_V2POWUR: 601 case MISCREG_V2POWUW: 602 { 603 RequestPtr req = new Request; 604 unsigned flags; 605 BaseTLB::Mode mode; 606 Fault fault; 607 switch(misc_reg) { 608 case MISCREG_V2PCWPR: 609 flags = TLB::MustBeOne; 610 mode = BaseTLB::Read; 611 break; 612 case MISCREG_V2PCWPW: 613 flags = TLB::MustBeOne; 614 mode = BaseTLB::Write; 615 break; 616 case MISCREG_V2PCWUR: 617 flags = TLB::MustBeOne | TLB::UserMode; 618 mode = BaseTLB::Read; 619 break; 620 case MISCREG_V2PCWUW: 621 flags = TLB::MustBeOne | TLB::UserMode; 622 mode = BaseTLB::Write; 623 break; 624 default: 625 panic("Security Extensions not implemented!"); 626 } 627 warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 628 req->setVirt(0, val, 1, flags, tc->pcState().pc(), 629 Request::funcMasterId); 630 fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 631 if (fault == NoFault) { 632 miscRegs[MISCREG_PAR] = 633 (req->getPaddr() & 0xfffff000) | 634 (tc->getDTBPtr()->getAttr() ); 635 DPRINTF(MiscRegs, 636 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 637 val, miscRegs[MISCREG_PAR]); 638 } 639 else { 640 // Set fault bit and FSR 641 FSR fsr = miscRegs[MISCREG_DFSR]; 642 miscRegs[MISCREG_PAR] = 643 (fsr.ext << 6) | 644 (fsr.fsHigh << 5) | 645 (fsr.fsLow << 1) | 646 0x1; // F bit 647 } 648 return; 649 } 650 case MISCREG_CONTEXTIDR: 651 case MISCREG_PRRR: 652 case MISCREG_NMRR: 653 case MISCREG_DACR: 654 tc->getITBPtr()->invalidateMiscReg(); 655 tc->getDTBPtr()->invalidateMiscReg(); 656 break; 657 case MISCREG_L2CTLR: 658 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 659 miscRegName[misc_reg], uint32_t(val)); 660 } 661 } 662 setMiscRegNoEffect(misc_reg, newVal); 663} 664 665} 666 667ArmISA::ISA * 668ArmISAParams::create() 669{ 670 return new ArmISA::ISA(this); 671} 672