isa.cc revision 9050
17405SAli.Saidi@ARM.com/* 28868SMatt.Horsnell@arm.com * Copyright (c) 2010-2012 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 429050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 438887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 448232Snate@binkert.org#include "debug/Arm.hh" 458232Snate@binkert.org#include "debug/MiscRegs.hh" 467678Sgblack@eecs.umich.edu#include "sim/faults.hh" 478059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 488284SAli.Saidi@ARM.com#include "sim/system.hh" 497405SAli.Saidi@ARM.com 507405SAli.Saidi@ARM.comnamespace ArmISA 517405SAli.Saidi@ARM.com{ 527405SAli.Saidi@ARM.com 537427Sgblack@eecs.umich.eduvoid 547427Sgblack@eecs.umich.eduISA::clear() 557427Sgblack@eecs.umich.edu{ 567427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 578299Schander.sudanthi@arm.com uint32_t midr = miscRegs[MISCREG_MIDR]; 587427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 597427Sgblack@eecs.umich.edu CPSR cpsr = 0; 607427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 617427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 627427Sgblack@eecs.umich.edu updateRegMap(cpsr); 637427Sgblack@eecs.umich.edu 647427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 657604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 667427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 677427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 687427Sgblack@eecs.umich.edu sctlr.u = 1; 697427Sgblack@eecs.umich.edu sctlr.xp = 1; 707427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 717427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 727427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 737427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 747427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 757427Sgblack@eecs.umich.edu 769050Schander.sudanthi@arm.com // Preserve MIDR across reset 778299Schander.sudanthi@arm.com miscRegs[MISCREG_MIDR] = midr; 788299Schander.sudanthi@arm.com 797427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 807427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 817427Sgblack@eecs.umich.edu 827427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 837427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 847427Sgblack@eecs.umich.edu 857427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 867427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 877427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 887427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 897427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 907427Sgblack@eecs.umich.edu mvfr0.divide = 1; 917427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 927427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 937427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 947427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 957427Sgblack@eecs.umich.edu 967427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 977427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 987427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 997427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1007427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1017427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1027427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1037427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1047427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1057427Sgblack@eecs.umich.edu 1067436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1077436Sdam.sunwoo@arm.com 1087436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1097436Sdam.sunwoo@arm.com (1 << 19) | // 19 1107436Sdam.sunwoo@arm.com (0 << 18) | // 18 1117436Sdam.sunwoo@arm.com (0 << 17) | // 17 1127436Sdam.sunwoo@arm.com (1 << 16) | // 16 1137436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1147436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1157436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1167436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1177436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1187436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1197436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1207436Sdam.sunwoo@arm.com 0; // 1:0 1217436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1227436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1237436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1247436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1257436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1267436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1277436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1287436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1297436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1307436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1317436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1327436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1337436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1347436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1357436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1367436Sdam.sunwoo@arm.com 0; // 1:0 1377436Sdam.sunwoo@arm.com 1387644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1397644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1408147SAli.Saidi@ARM.com 1418147SAli.Saidi@ARM.com // See section B4.1.84 of ARM ARM 1428147SAli.Saidi@ARM.com // All values are latest for ARMv7-A profile 1438520SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1448147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1458147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1468147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1478147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1488147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1498147SAli.Saidi@ARM.com 1507427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1517427Sgblack@eecs.umich.edu} 1527427Sgblack@eecs.umich.edu 1537405SAli.Saidi@ARM.comMiscReg 1547405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1557405SAli.Saidi@ARM.com{ 1567405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1577614Sminkyu.jeong@arm.com 1587614Sminkyu.jeong@arm.com int flat_idx; 1597614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1607614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1617614Sminkyu.jeong@arm.com else 1627614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1637614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1647614Sminkyu.jeong@arm.com 1657614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1667614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1677614Sminkyu.jeong@arm.com return val; 1687405SAli.Saidi@ARM.com} 1697405SAli.Saidi@ARM.com 1707405SAli.Saidi@ARM.com 1717405SAli.Saidi@ARM.comMiscReg 1727405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1737405SAli.Saidi@ARM.com{ 1749050Schander.sudanthi@arm.com ArmSystem *arm_sys; 1759050Schander.sudanthi@arm.com 1767405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1777405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1787720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1797720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1807720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1817405SAli.Saidi@ARM.com return cpsr; 1827405SAli.Saidi@ARM.com } 1837757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 1847405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1857405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1867757SAli.Saidi@ARM.com 1877405SAli.Saidi@ARM.com switch (misc_reg) { 1888284SAli.Saidi@ARM.com case MISCREG_MPIDR: 1899050Schander.sudanthi@arm.com arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 1909050Schander.sudanthi@arm.com assert(arm_sys); 1918873SAli.Saidi@ARM.com 1929050Schander.sudanthi@arm.com if (arm_sys->multiProc) { 1939050Schander.sudanthi@arm.com return 0x80000000 | // multiprocessor extensions available 1949050Schander.sudanthi@arm.com tc->cpuId(); 1959050Schander.sudanthi@arm.com } else { 1969050Schander.sudanthi@arm.com return 0x80000000 | // multiprocessor extensions available 1979050Schander.sudanthi@arm.com 0x40000000 | // in up system 1989050Schander.sudanthi@arm.com tc->cpuId(); 1999050Schander.sudanthi@arm.com } 2008284SAli.Saidi@ARM.com break; 2018468Swade.walker@arm.com case MISCREG_ID_MMFR0: 2028468Swade.walker@arm.com return 0x03; // VMSAv7 support 2038468Swade.walker@arm.com case MISCREG_ID_MMFR2: 2048468Swade.walker@arm.com return 0x01230000; // no HW access | WFI stalling | ISB and DSB 2058468Swade.walker@arm.com // | all TLB maintenance | no Harvard 2068284SAli.Saidi@ARM.com case MISCREG_ID_MMFR3: 2078284SAli.Saidi@ARM.com return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 2088284SAli.Saidi@ARM.com // BP Maint | Cache Maint Set/way | Cache Maint MVA 2097405SAli.Saidi@ARM.com case MISCREG_CLIDR: 2107731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 2118468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 2128468Swade.walker@arm.com "ARM implementations.\n"); 2138468Swade.walker@arm.com return 0x00200000; 2147405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 2157731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 2167405SAli.Saidi@ARM.com "always reads as 0.\n"); 2177405SAli.Saidi@ARM.com break; 2187405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2197588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 2207588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 2217588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2228299Schander.sudanthi@arm.com case MISCREG_ID_PFR1: 2238870SAli.Saidi@ARM.com return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 2247583SAli.Saidi@arm.com case MISCREG_CTR: 2257583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2267583SAli.Saidi@arm.com case MISCREG_ACTLR: 2277583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2287583SAli.Saidi@arm.com break; 2297583SAli.Saidi@arm.com case MISCREG_PMCR: 2307583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2317583SAli.Saidi@arm.com case MISCREG_PMSELR: 2328299Schander.sudanthi@arm.com warn("Not doing anything for read to miscreg %s\n", 2337583SAli.Saidi@arm.com miscRegName[misc_reg]); 2347583SAli.Saidi@arm.com break; 2358302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 2368302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 2377783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2387783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2397783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2407783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2418549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 2428868SMatt.Horsnell@arm.com { 2438868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 2448868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 2458868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 2468868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2478868SMatt.Horsnell@arm.com return l2ctlr; 2488868SMatt.Horsnell@arm.com } 2498868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 2508868SMatt.Horsnell@arm.com /* For now just implement the version number. 2518868SMatt.Horsnell@arm.com * Return 0 as we don't support debug architecture yet. 2528868SMatt.Horsnell@arm.com */ 2538868SMatt.Horsnell@arm.com return 0; 2548868SMatt.Horsnell@arm.com case MISCREG_DBGDSCR_INT: 2558868SMatt.Horsnell@arm.com return 0; 2567405SAli.Saidi@ARM.com } 2577405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2587405SAli.Saidi@ARM.com} 2597405SAli.Saidi@ARM.com 2607405SAli.Saidi@ARM.comvoid 2617405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2627405SAli.Saidi@ARM.com{ 2637405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2647614Sminkyu.jeong@arm.com 2657614Sminkyu.jeong@arm.com int flat_idx; 2667614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2677614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2687614Sminkyu.jeong@arm.com else 2697614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2707614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2717614Sminkyu.jeong@arm.com 2727614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2737614Sminkyu.jeong@arm.com flat_idx, val); 2747405SAli.Saidi@ARM.com} 2757405SAli.Saidi@ARM.com 2767405SAli.Saidi@ARM.comvoid 2777405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2787405SAli.Saidi@ARM.com{ 2797749SAli.Saidi@ARM.com 2807405SAli.Saidi@ARM.com MiscReg newVal = val; 2818284SAli.Saidi@ARM.com int x; 2828284SAli.Saidi@ARM.com System *sys; 2838284SAli.Saidi@ARM.com ThreadContext *oc; 2848284SAli.Saidi@ARM.com 2857405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2867405SAli.Saidi@ARM.com updateRegMap(val); 2877749SAli.Saidi@ARM.com 2887749SAli.Saidi@ARM.com 2897749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2907749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 2917405SAli.Saidi@ARM.com CPSR cpsr = val; 2927749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 2937749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 2947749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 2957749SAli.Saidi@ARM.com } 2967749SAli.Saidi@ARM.com 2977614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2987614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2997720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3007720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 3017720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 3028887Sgeoffrey.blake@arm.com 3038887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 3048887Sgeoffrey.blake@arm.com // is connected 3058887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 3068887Sgeoffrey.blake@arm.com if (checker) { 3078887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 3088887Sgeoffrey.blake@arm.com } else { 3098887Sgeoffrey.blake@arm.com tc->pcState(pc); 3108887Sgeoffrey.blake@arm.com } 3117408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3127405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 3137405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 3147405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 3157408Sgblack@eecs.umich.edu } else { 3167408Sgblack@eecs.umich.edu switch (misc_reg) { 3177408Sgblack@eecs.umich.edu case MISCREG_CPACR: 3187408Sgblack@eecs.umich.edu { 3198206SWilliam.Wang@arm.com 3208206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 3218206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 3228206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 3238206SWilliam.Wang@arm.com // be writable 3248206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 3258206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 3268206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 3278206SWilliam.Wang@arm.com newVal &= cpacrMask; 3288206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3298206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 3307408Sgblack@eecs.umich.edu } 3317408Sgblack@eecs.umich.edu break; 3327408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3337731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 3348206SWilliam.Wang@arm.com return; 3357408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3367408Sgblack@eecs.umich.edu { 3377408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3387408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3397408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3407408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3417408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3427408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3437408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3447408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3457408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3467408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3477408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3487408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3497408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3507408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3517408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3527408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3537408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3547408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3557408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3567408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3577408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3587408Sgblack@eecs.umich.edu } 3597408Sgblack@eecs.umich.edu break; 3608302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 3618302SAli.Saidi@ARM.com { 3628302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 3638302SAli.Saidi@ARM.com newVal = miscRegs[MISCREG_CPSR] | newVal; 3648302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 3658302SAli.Saidi@ARM.com } 3668302SAli.Saidi@ARM.com break; 3677783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 3687783SGiacomo.Gabrielli@arm.com { 3697783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3707783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3717783SGiacomo.Gabrielli@arm.com } 3727783SGiacomo.Gabrielli@arm.com break; 3737783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 3747783SGiacomo.Gabrielli@arm.com { 3757783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3767783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3777783SGiacomo.Gabrielli@arm.com } 3787783SGiacomo.Gabrielli@arm.com break; 3797408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3807408Sgblack@eecs.umich.edu { 3818206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 3828206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 3837408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3847408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3857408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3867408Sgblack@eecs.umich.edu } 3877408Sgblack@eecs.umich.edu break; 3887408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3897408Sgblack@eecs.umich.edu { 3907408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3917408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3927408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3937408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3947408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3957749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3967749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3978527SAli.Saidi@ARM.com 3988527SAli.Saidi@ARM.com // Check if all CPUs are booted with caches enabled 3998527SAli.Saidi@ARM.com // so we can stop enforcing coherency of some kernel 4008527SAli.Saidi@ARM.com // structures manually. 4018527SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4028527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4038527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4048527SAli.Saidi@ARM.com SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 4058527SAli.Saidi@ARM.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 4068527SAli.Saidi@ARM.com return; 4078527SAli.Saidi@ARM.com } 4088527SAli.Saidi@ARM.com 4098527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4108527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4118527SAli.Saidi@ARM.com oc->getDTBPtr()->allCpusCaching(); 4128527SAli.Saidi@ARM.com oc->getITBPtr()->allCpusCaching(); 4138887Sgeoffrey.blake@arm.com 4148887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it. 4158887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4168733Sgeoffrey.blake@arm.com if (checker) { 4178733Sgeoffrey.blake@arm.com checker->getDTBPtr()->allCpusCaching(); 4188733Sgeoffrey.blake@arm.com checker->getITBPtr()->allCpusCaching(); 4198733Sgeoffrey.blake@arm.com } 4208527SAli.Saidi@ARM.com } 4217408Sgblack@eecs.umich.edu return; 4227408Sgblack@eecs.umich.edu } 4237408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 4247408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 4257408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 4267408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 4277408Sgblack@eecs.umich.edu case MISCREG_FPSID: 4287408Sgblack@eecs.umich.edu return; 4297408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 4307408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 4318284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4328284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4338284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4348284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4358284SAli.Saidi@ARM.com oc->getITBPtr()->flushAll(); 4368284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAll(); 4378887Sgeoffrey.blake@arm.com 4388887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 4398887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4408733Sgeoffrey.blake@arm.com if (checker) { 4418733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAll(); 4428733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAll(); 4438733Sgeoffrey.blake@arm.com } 4448284SAli.Saidi@ARM.com } 4457408Sgblack@eecs.umich.edu return; 4467408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 4477408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 4487408Sgblack@eecs.umich.edu return; 4497408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 4507408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 4517408Sgblack@eecs.umich.edu return; 4527408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 4537408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 4548284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4558284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4568284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4578284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4588284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4598284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4608284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4618284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4628887Sgeoffrey.blake@arm.com 4638887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4648733Sgeoffrey.blake@arm.com if (checker) { 4658733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4668733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 4678733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4688733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 4698733Sgeoffrey.blake@arm.com } 4708284SAli.Saidi@ARM.com } 4717408Sgblack@eecs.umich.edu return; 4727408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 4737408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 4748284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4758284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4768284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4778284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4788284SAli.Saidi@ARM.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4798284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4808887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4818733Sgeoffrey.blake@arm.com if (checker) { 4828733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4838733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4848733Sgeoffrey.blake@arm.com } 4858284SAli.Saidi@ARM.com } 4867408Sgblack@eecs.umich.edu return; 4877408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 4887408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 4898284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4908284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4918284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4928284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4938284SAli.Saidi@ARM.com oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4948284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4958887Sgeoffrey.blake@arm.com 4968887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4978733Sgeoffrey.blake@arm.com if (checker) { 4988733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4998733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 5008733Sgeoffrey.blake@arm.com } 5018284SAli.Saidi@ARM.com } 5027408Sgblack@eecs.umich.edu return; 5037408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 5047408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5057408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5067408Sgblack@eecs.umich.edu return; 5077408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 5087408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5097408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5107408Sgblack@eecs.umich.edu return; 5117408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 5127408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5137408Sgblack@eecs.umich.edu return; 5147408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 5157408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5167405SAli.Saidi@ARM.com return; 5177583SAli.Saidi@arm.com case MISCREG_ACTLR: 5187583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 5197583SAli.Saidi@arm.com break; 5207583SAli.Saidi@arm.com case MISCREG_PMCR: 5218059SAli.Saidi@ARM.com { 5228059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 5238059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 5248059SAli.Saidi@ARM.com // statistics. 5258059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 5268059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 5278059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 5288059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 5298059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 5308059SAli.Saidi@ARM.com break; 5318059SAli.Saidi@ARM.com } 5328059SAli.Saidi@ARM.com } 5337583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 5347583SAli.Saidi@arm.com case MISCREG_PMSELR: 5357583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 5367583SAli.Saidi@arm.com miscRegName[misc_reg]); 5377583SAli.Saidi@arm.com break; 5387436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 5397436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 5407436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5417436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5427436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 5437436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 5447436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 5457436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 5467436Sdam.sunwoo@arm.com { 5477436Sdam.sunwoo@arm.com RequestPtr req = new Request; 5487436Sdam.sunwoo@arm.com unsigned flags; 5497436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 5507436Sdam.sunwoo@arm.com Fault fault; 5517436Sdam.sunwoo@arm.com switch(misc_reg) { 5527436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 5537436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 5547436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 5557436Sdam.sunwoo@arm.com break; 5567436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 5577436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 5587436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 5597436Sdam.sunwoo@arm.com break; 5607436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5617436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5627436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 5637436Sdam.sunwoo@arm.com break; 5647436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5657436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5667436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 5677436Sdam.sunwoo@arm.com break; 5687442Ssaidi@eecs.umich.edu default: 5697436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 5707436Sdam.sunwoo@arm.com } 5718208SAli.Saidi@ARM.com warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 5728832SAli.Saidi@ARM.com req->setVirt(0, val, 1, flags, tc->pcState().pc(), 5738832SAli.Saidi@ARM.com Request::funcMasterId); 5747436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 5757436Sdam.sunwoo@arm.com if (fault == NoFault) { 5767436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5777436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 5787436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 5797436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 5807436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 5817436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 5827436Sdam.sunwoo@arm.com } 5837436Sdam.sunwoo@arm.com else { 5847436Sdam.sunwoo@arm.com // Set fault bit and FSR 5857436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 5867436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5877436Sdam.sunwoo@arm.com (fsr.ext << 6) | 5887436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 5897436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 5907436Sdam.sunwoo@arm.com 0x1; // F bit 5917436Sdam.sunwoo@arm.com } 5927436Sdam.sunwoo@arm.com return; 5937436Sdam.sunwoo@arm.com } 5947749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 5957749SAli.Saidi@ARM.com case MISCREG_PRRR: 5967749SAli.Saidi@ARM.com case MISCREG_NMRR: 5977749SAli.Saidi@ARM.com case MISCREG_DACR: 5987749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 5997749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 6007749SAli.Saidi@ARM.com break; 6018208SAli.Saidi@ARM.com case MISCREG_CPSR_MODE: 6028208SAli.Saidi@ARM.com // This miscreg is used by copy*Regs to set the CPSR mode 6038208SAli.Saidi@ARM.com // without updating other CPSR variables. It's used to 6048208SAli.Saidi@ARM.com // make sure the register map is in such a state that we can 6058208SAli.Saidi@ARM.com // see all of the registers for the copy. 6068208SAli.Saidi@ARM.com updateRegMap(val); 6078208SAli.Saidi@ARM.com return; 6088549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6098549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 6108549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 6117405SAli.Saidi@ARM.com } 6127405SAli.Saidi@ARM.com } 6137405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 6147405SAli.Saidi@ARM.com} 6157405SAli.Saidi@ARM.com 6167405SAli.Saidi@ARM.com} 617