isa.cc revision 8887
12391SN/A/* 22391SN/A * Copyright (c) 2010-2012 ARM Limited 32391SN/A * All rights reserved 42391SN/A * 52391SN/A * The license below extends only to copyright in the software and shall 62391SN/A * not be construed as granting a license to any other intellectual 72391SN/A * property including but not limited to intellectual property relating 82391SN/A * to a hardware implementation of the functionality of the software 92391SN/A * licensed hereunder. You may use the software subject to the license 102391SN/A * terms below provided that you ensure that this notice is replicated 112391SN/A * unmodified and in its entirety in all distributions of the software, 122391SN/A * modified or unmodified, in source code or in binary form. 132391SN/A * 142391SN/A * Redistribution and use in source and binary forms, with or without 152391SN/A * modification, are permitted provided that the following conditions are 162391SN/A * met: redistributions of source code must retain the above copyright 172391SN/A * notice, this list of conditions and the following disclaimer; 182391SN/A * redistributions in binary form must reproduce the above copyright 192391SN/A * notice, this list of conditions and the following disclaimer in the 202391SN/A * documentation and/or other materials provided with the distribution; 212391SN/A * neither the name of the copyright holders nor the names of its 222391SN/A * contributors may be used to endorse or promote products derived from 232391SN/A * this software without specific prior written permission. 242391SN/A * 252391SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 262391SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 272665Ssaidi@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 282665Ssaidi@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 292914Ssaidi@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 302391SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 312391SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 322391SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 332391SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 342391SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 352391SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 362391SN/A * 372391SN/A * Authors: Gabe Black 382391SN/A * Ali Saidi 392391SN/A */ 402391SN/A 412391SN/A#include "arch/arm/isa.hh" 423348Sbinkertn@umich.edu#include "cpu/checker/cpu.hh" 432391SN/A#include "debug/Arm.hh" 445399Ssaidi@eecs.umich.edu#include "debug/MiscRegs.hh" 452391SN/A#include "sim/faults.hh" 463879Ssaidi@eecs.umich.edu#include "sim/stat_control.hh" 472394SN/A#include "sim/system.hh" 482415SN/A 493348Sbinkertn@umich.edunamespace ArmISA 502394SN/A{ 512391SN/A 522423SN/Avoid 532391SN/AISA::clear() 544762Snate@binkert.org{ 555477Snate@binkert.org SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 565477Snate@binkert.org uint32_t midr = miscRegs[MISCREG_MIDR]; 575477Snate@binkert.org memset(miscRegs, 0, sizeof(miscRegs)); 582391SN/A CPSR cpsr = 0; 594762Snate@binkert.org cpsr.mode = MODE_USER; 602391SN/A miscRegs[MISCREG_CPSR] = cpsr; 612391SN/A updateRegMap(cpsr); 625477Snate@binkert.org 635477Snate@binkert.org SCTLR sctlr = 0; 645477Snate@binkert.org sctlr.te = (bool)sctlr_rst.te; 652391SN/A sctlr.nmfi = (bool)sctlr_rst.nmfi; 664918Snate@binkert.org sctlr.v = (bool)sctlr_rst.v; 674918Snate@binkert.org sctlr.u = 1; 682391SN/A sctlr.xp = 1; 693012Ssaidi@eecs.umich.edu sctlr.rao2 = 1; 702391SN/A sctlr.rao3 = 1; 712391SN/A sctlr.rao4 = 1; 722391SN/A miscRegs[MISCREG_SCTLR] = sctlr; 732391SN/A miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 743751Sgblack@eecs.umich.edu 754762Snate@binkert.org // Preserve MIDR accross reset 764762Snate@binkert.org miscRegs[MISCREG_MIDR] = midr; 772391SN/A 782391SN/A /* Start with an event in the mailbox */ 792541SN/A miscRegs[MISCREG_SEV_MAILBOX] = 1; 802541SN/A 812541SN/A // Separate Instruction and Data TLBs. 824470Sstever@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 834470Sstever@eecs.umich.edu 844470Sstever@eecs.umich.edu MVFR0 mvfr0 = 0; 854470Sstever@eecs.umich.edu mvfr0.advSimdRegisters = 2; 864467Sstever@eecs.umich.edu mvfr0.singlePrecision = 2; 874467Sstever@eecs.umich.edu mvfr0.doublePrecision = 2; 884467Sstever@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 894467Sstever@eecs.umich.edu mvfr0.divide = 1; 902541SN/A mvfr0.squareRoot = 1; 912541SN/A mvfr0.shortVectors = 1; 922391SN/A mvfr0.roundingModes = 1; 932391SN/A miscRegs[MISCREG_MVFR0] = mvfr0; 943012Ssaidi@eecs.umich.edu 954762Snate@binkert.org MVFR1 mvfr1 = 0; 962416SN/A mvfr1.flushToZero = 1; 972391SN/A mvfr1.defaultNaN = 1; 982391SN/A mvfr1.advSimdLoadStore = 1; 992391SN/A mvfr1.advSimdInteger = 1; 1002391SN/A mvfr1.advSimdSinglePrecision = 1; 1012391SN/A mvfr1.advSimdHalfPrecision = 1; 1023012Ssaidi@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1034040Ssaidi@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1042391SN/A 1053012Ssaidi@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1062391SN/A 1072391SN/A // Reset values of PRRR and NMRR are implementation dependent 1082391SN/A 1092408SN/A miscRegs[MISCREG_PRRR] = 1102408SN/A (1 << 19) | // 19 1112408SN/A (0 << 18) | // 18 1122409SN/A (0 << 17) | // 17 1132409SN/A (1 << 16) | // 16 1142408SN/A (2 << 14) | // 15:14 1152408SN/A (0 << 12) | // 13:12 1163012Ssaidi@eecs.umich.edu (2 << 10) | // 11:10 1173349Sbinkertn@umich.edu (2 << 8) | // 9:8 1183012Ssaidi@eecs.umich.edu (2 << 6) | // 7:6 1195399Ssaidi@eecs.umich.edu (2 << 4) | // 5:4 1205399Ssaidi@eecs.umich.edu (1 << 2) | // 3:2 1215399Ssaidi@eecs.umich.edu 0; // 1:0 1225399Ssaidi@eecs.umich.edu miscRegs[MISCREG_NMRR] = 1233012Ssaidi@eecs.umich.edu (1 << 30) | // 31:30 1242413SN/A (0 << 26) | // 27:26 1253170Sstever@eecs.umich.edu (0 << 24) | // 25:24 1263170Sstever@eecs.umich.edu (3 << 22) | // 23:22 1273170Sstever@eecs.umich.edu (2 << 20) | // 21:20 1283170Sstever@eecs.umich.edu (0 << 18) | // 19:18 1293170Sstever@eecs.umich.edu (0 << 16) | // 17:16 1304626Sstever@eecs.umich.edu (1 << 14) | // 15:14 1313170Sstever@eecs.umich.edu (0 << 12) | // 13:12 1324626Sstever@eecs.umich.edu (2 << 10) | // 11:10 1333170Sstever@eecs.umich.edu (0 << 8) | // 9:8 1343170Sstever@eecs.umich.edu (3 << 6) | // 7:6 1353170Sstever@eecs.umich.edu (2 << 4) | // 5:4 1363170Sstever@eecs.umich.edu (0 << 2) | // 3:2 1373170Sstever@eecs.umich.edu 0; // 1:0 1383170Sstever@eecs.umich.edu 1393170Sstever@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 1403170Sstever@eecs.umich.edu miscRegs[MISCREG_FPSID] = 0x410430A0; 1413170Sstever@eecs.umich.edu 1425714Shsul@eecs.umich.edu // See section B4.1.84 of ARM ARM 1435714Shsul@eecs.umich.edu // All values are latest for ARMv7-A profile 1443170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1453170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1463170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1473170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1483170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1493170Sstever@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1505714Shsul@eecs.umich.edu 1515714Shsul@eecs.umich.edu //XXX We need to initialize the rest of the state. 1523170Sstever@eecs.umich.edu} 1533170Sstever@eecs.umich.edu 1543170Sstever@eecs.umich.eduMiscReg 1553170Sstever@eecs.umich.eduISA::readMiscRegNoEffect(int misc_reg) 1563170Sstever@eecs.umich.edu{ 1573170Sstever@eecs.umich.edu assert(misc_reg < NumMiscRegs); 1583170Sstever@eecs.umich.edu 1593170Sstever@eecs.umich.edu int flat_idx; 1603170Sstever@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 1614626Sstever@eecs.umich.edu flat_idx = flattenMiscIndex(misc_reg); 1623170Sstever@eecs.umich.edu else 1634626Sstever@eecs.umich.edu flat_idx = misc_reg; 1643170Sstever@eecs.umich.edu MiscReg val = miscRegs[flat_idx]; 1654626Sstever@eecs.umich.edu 1663170Sstever@eecs.umich.edu DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1673170Sstever@eecs.umich.edu misc_reg, flat_idx, val); 1683170Sstever@eecs.umich.edu return val; 1693170Sstever@eecs.umich.edu} 1703170Sstever@eecs.umich.edu 1713170Sstever@eecs.umich.edu 1723170Sstever@eecs.umich.eduMiscReg 1733170Sstever@eecs.umich.eduISA::readMiscReg(int misc_reg, ThreadContext *tc) 1743170Sstever@eecs.umich.edu{ 1753170Sstever@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 1763170Sstever@eecs.umich.edu CPSR cpsr = miscRegs[misc_reg]; 1773170Sstever@eecs.umich.edu PCState pc = tc->pcState(); 1783170Sstever@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1793170Sstever@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1803170Sstever@eecs.umich.edu return cpsr; 1813170Sstever@eecs.umich.edu } 1823170Sstever@eecs.umich.edu if (misc_reg >= MISCREG_CP15_UNIMP_START) 1833170Sstever@eecs.umich.edu panic("Unimplemented CP15 register %s read.\n", 1843170Sstever@eecs.umich.edu miscRegName[misc_reg]); 1853170Sstever@eecs.umich.edu 1865714Shsul@eecs.umich.edu switch (misc_reg) { 1875714Shsul@eecs.umich.edu case MISCREG_MPIDR: 1883170Sstever@eecs.umich.edu 1893170Sstever@eecs.umich.edu return 0x80000000 | // multiprocessor extensions available 1903170Sstever@eecs.umich.edu tc->cpuId(); 1913170Sstever@eecs.umich.edu break; 1925714Shsul@eecs.umich.edu case MISCREG_ID_MMFR0: 1935714Shsul@eecs.umich.edu return 0x03; // VMSAv7 support 1943170Sstever@eecs.umich.edu case MISCREG_ID_MMFR2: 1953170Sstever@eecs.umich.edu return 0x01230000; // no HW access | WFI stalling | ISB and DSB 1963170Sstever@eecs.umich.edu // | all TLB maintenance | no Harvard 1973170Sstever@eecs.umich.edu case MISCREG_ID_MMFR3: 1983170Sstever@eecs.umich.edu return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 1993170Sstever@eecs.umich.edu // BP Maint | Cache Maint Set/way | Cache Maint MVA 2003170Sstever@eecs.umich.edu case MISCREG_CLIDR: 2013170Sstever@eecs.umich.edu warn_once("The clidr register always reports 0 caches.\n"); 2023170Sstever@eecs.umich.edu warn_once("clidr LoUIS field of 0b001 to match current " 2034040Ssaidi@eecs.umich.edu "ARM implementations.\n"); 2043170Sstever@eecs.umich.edu return 0x00200000; 2053170Sstever@eecs.umich.edu case MISCREG_CCSIDR: 2063170Sstever@eecs.umich.edu warn_once("The ccsidr register isn't implemented and " 2073170Sstever@eecs.umich.edu "always reads as 0.\n"); 2083170Sstever@eecs.umich.edu break; 2094626Sstever@eecs.umich.edu case MISCREG_ID_PFR0: 2104626Sstever@eecs.umich.edu warn("Returning thumbEE disabled for now since we don't support CP14" 2114626Sstever@eecs.umich.edu "config registers and jumping to ThumbEE vectors\n"); 2124626Sstever@eecs.umich.edu return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2134626Sstever@eecs.umich.edu case MISCREG_ID_PFR1: 2144626Sstever@eecs.umich.edu return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 2154626Sstever@eecs.umich.edu case MISCREG_CTR: 2164626Sstever@eecs.umich.edu return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2174626Sstever@eecs.umich.edu case MISCREG_ACTLR: 2184626Sstever@eecs.umich.edu warn("Not doing anything for miscreg ACTLR\n"); 2194626Sstever@eecs.umich.edu break; 2204626Sstever@eecs.umich.edu case MISCREG_PMCR: 2214626Sstever@eecs.umich.edu case MISCREG_PMCCNTR: 2224626Sstever@eecs.umich.edu case MISCREG_PMSELR: 2234626Sstever@eecs.umich.edu warn("Not doing anything for read to miscreg %s\n", 2244626Sstever@eecs.umich.edu miscRegName[misc_reg]); 2254626Sstever@eecs.umich.edu break; 2264626Sstever@eecs.umich.edu case MISCREG_CPSR_Q: 2274626Sstever@eecs.umich.edu panic("shouldn't be reading this register seperately\n"); 2284626Sstever@eecs.umich.edu case MISCREG_FPSCR_QC: 2294626Sstever@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2304626Sstever@eecs.umich.edu case MISCREG_FPSCR_EXC: 2314626Sstever@eecs.umich.edu return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2324626Sstever@eecs.umich.edu case MISCREG_L2CTLR: 2334626Sstever@eecs.umich.edu { 2344626Sstever@eecs.umich.edu // mostly unimplemented, just set NumCPUs field from sim and return 2354626Sstever@eecs.umich.edu L2CTLR l2ctlr = 0; 2364626Sstever@eecs.umich.edu // b00:1CPU to b11:4CPUs 2374626Sstever@eecs.umich.edu l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2384626Sstever@eecs.umich.edu return l2ctlr; 2394626Sstever@eecs.umich.edu } 2402413SN/A case MISCREG_DBGDIDR: 2414040Ssaidi@eecs.umich.edu /* For now just implement the version number. 2424040Ssaidi@eecs.umich.edu * Return 0 as we don't support debug architecture yet. 2432414SN/A */ 2444626Sstever@eecs.umich.edu return 0; 2454626Sstever@eecs.umich.edu case MISCREG_DBGDSCR_INT: 2464626Sstever@eecs.umich.edu return 0; 2474626Sstever@eecs.umich.edu } 2483175Srdreslin@umich.edu return readMiscRegNoEffect(misc_reg); 2494626Sstever@eecs.umich.edu} 2504626Sstever@eecs.umich.edu 2514626Sstever@eecs.umich.eduvoid 2524626Sstever@eecs.umich.eduISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2534040Ssaidi@eecs.umich.edu{ 2544040Ssaidi@eecs.umich.edu assert(misc_reg < NumMiscRegs); 2554040Ssaidi@eecs.umich.edu 2564040Ssaidi@eecs.umich.edu int flat_idx; 2574040Ssaidi@eecs.umich.edu if (misc_reg == MISCREG_SPSR) 2585477Snate@binkert.org flat_idx = flattenMiscIndex(misc_reg); 2595477Snate@binkert.org else 2604040Ssaidi@eecs.umich.edu flat_idx = misc_reg; 2614040Ssaidi@eecs.umich.edu miscRegs[flat_idx] = val; 2624040Ssaidi@eecs.umich.edu 2634040Ssaidi@eecs.umich.edu DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2644040Ssaidi@eecs.umich.edu flat_idx, val); 2654052Ssaidi@eecs.umich.edu} 2664626Sstever@eecs.umich.edu 2674040Ssaidi@eecs.umich.eduvoid 2684040Ssaidi@eecs.umich.eduISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2694040Ssaidi@eecs.umich.edu{ 2704052Ssaidi@eecs.umich.edu 2714626Sstever@eecs.umich.edu MiscReg newVal = val; 2724626Sstever@eecs.umich.edu int x; 2734040Ssaidi@eecs.umich.edu System *sys; 2744052Ssaidi@eecs.umich.edu ThreadContext *oc; 2754626Sstever@eecs.umich.edu 2764626Sstever@eecs.umich.edu if (misc_reg == MISCREG_CPSR) { 2774040Ssaidi@eecs.umich.edu updateRegMap(val); 2784040Ssaidi@eecs.umich.edu 2794040Ssaidi@eecs.umich.edu 2804040Ssaidi@eecs.umich.edu CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2814040Ssaidi@eecs.umich.edu int old_mode = old_cpsr.mode; 2824626Sstever@eecs.umich.edu CPSR cpsr = val; 2834040Ssaidi@eecs.umich.edu if (old_mode != cpsr.mode) { 2844626Sstever@eecs.umich.edu tc->getITBPtr()->invalidateMiscReg(); 2854626Sstever@eecs.umich.edu tc->getDTBPtr()->invalidateMiscReg(); 2864626Sstever@eecs.umich.edu } 2874626Sstever@eecs.umich.edu 2884626Sstever@eecs.umich.edu DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2894040Ssaidi@eecs.umich.edu miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2905477Snate@binkert.org PCState pc = tc->pcState(); 2915477Snate@binkert.org pc.nextThumb(cpsr.t); 2924626Sstever@eecs.umich.edu pc.nextJazelle(cpsr.j); 2934626Sstever@eecs.umich.edu 2944626Sstever@eecs.umich.edu // Follow slightly different semantics if a CheckerCPU object 2955477Snate@binkert.org // is connected 2965477Snate@binkert.org CheckerCPU *checker = tc->getCheckerCpuPtr(); 2974626Sstever@eecs.umich.edu if (checker) { 2984626Sstever@eecs.umich.edu tc->pcStateNoRecord(pc); 2994626Sstever@eecs.umich.edu } else { 3004626Sstever@eecs.umich.edu tc->pcState(pc); 3014626Sstever@eecs.umich.edu } 3024626Sstever@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3034626Sstever@eecs.umich.edu misc_reg < MISCREG_CP15_END) { 3044040Ssaidi@eecs.umich.edu panic("Unimplemented CP15 register %s wrote with %#x.\n", 3052413SN/A miscRegName[misc_reg], val); 3062413SN/A } else { 3072420SN/A switch (misc_reg) { 3084626Sstever@eecs.umich.edu case MISCREG_CPACR: 3094626Sstever@eecs.umich.edu { 3104626Sstever@eecs.umich.edu 3114626Sstever@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3122413SN/A CPACR cpacrMask = 0; 3132413SN/A // Only cp10, cp11, and ase are implemented, nothing else should 3144626Sstever@eecs.umich.edu // be writable 3154626Sstever@eecs.umich.edu cpacrMask.cp10 = ones; 3164626Sstever@eecs.umich.edu cpacrMask.cp11 = ones; 3174626Sstever@eecs.umich.edu cpacrMask.asedis = ones; 3184626Sstever@eecs.umich.edu newVal &= cpacrMask; 3194626Sstever@eecs.umich.edu DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3204626Sstever@eecs.umich.edu miscRegName[misc_reg], newVal); 3215222Sksewell@umich.edu } 3224626Sstever@eecs.umich.edu break; 3234626Sstever@eecs.umich.edu case MISCREG_CSSELR: 3245314Sstever@gmail.com warn_once("The csselr register isn't implemented.\n"); 3255477Snate@binkert.org return; 3265477Snate@binkert.org case MISCREG_FPSCR: 3274626Sstever@eecs.umich.edu { 3285314Sstever@gmail.com const uint32_t ones = (uint32_t)(-1); 3295314Sstever@gmail.com FPSCR fpscrMask = 0; 3305477Snate@binkert.org fpscrMask.ioc = ones; 3315477Snate@binkert.org fpscrMask.dzc = ones; 3324626Sstever@eecs.umich.edu fpscrMask.ofc = ones; 3335314Sstever@gmail.com fpscrMask.ufc = ones; 3345314Sstever@gmail.com fpscrMask.ixc = ones; 3355315Sstever@gmail.com fpscrMask.idc = ones; 3365315Sstever@gmail.com fpscrMask.len = ones; 3375315Sstever@gmail.com fpscrMask.stride = ones; 3385315Sstever@gmail.com fpscrMask.rMode = ones; 3395314Sstever@gmail.com fpscrMask.fz = ones; 3405315Sstever@gmail.com fpscrMask.dn = ones; 3415314Sstever@gmail.com fpscrMask.ahp = ones; 3424626Sstever@eecs.umich.edu fpscrMask.qc = ones; 3434626Sstever@eecs.umich.edu fpscrMask.v = ones; 3444626Sstever@eecs.umich.edu fpscrMask.c = ones; 3454626Sstever@eecs.umich.edu fpscrMask.z = ones; 3464490Sstever@eecs.umich.edu fpscrMask.n = ones; 3474490Sstever@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3484626Sstever@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3492413SN/A } 3502738Sstever@eecs.umich.edu break; 3512413SN/A case MISCREG_CPSR_Q: 3524468Sstever@eecs.umich.edu { 3534468Sstever@eecs.umich.edu assert(!(newVal & ~CpsrMaskQ)); 3544468Sstever@eecs.umich.edu newVal = miscRegs[MISCREG_CPSR] | newVal; 3554468Sstever@eecs.umich.edu misc_reg = MISCREG_CPSR; 3564468Sstever@eecs.umich.edu } 3574468Sstever@eecs.umich.edu break; 3584468Sstever@eecs.umich.edu case MISCREG_FPSCR_QC: 3594467Sstever@eecs.umich.edu { 3602462SN/A newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3612462SN/A misc_reg = MISCREG_FPSCR; 3624467Sstever@eecs.umich.edu } 3634467Sstever@eecs.umich.edu break; 3644467Sstever@eecs.umich.edu case MISCREG_FPSCR_EXC: 3654467Sstever@eecs.umich.edu { 3664467Sstever@eecs.umich.edu newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3674467Sstever@eecs.umich.edu misc_reg = MISCREG_FPSCR; 3684467Sstever@eecs.umich.edu } 3694467Sstever@eecs.umich.edu break; 3704467Sstever@eecs.umich.edu case MISCREG_FPEXC: 3714467Sstever@eecs.umich.edu { 3724467Sstever@eecs.umich.edu // vfpv3 architecture, section B.6.1 of DDI04068 3734467Sstever@eecs.umich.edu // bit 29 - valid only if fpexc[31] is 0 3744467Sstever@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3754467Sstever@eecs.umich.edu newVal = (newVal & fpexcMask) | 3762413SN/A (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3772413SN/A } 3784467Sstever@eecs.umich.edu break; 3792413SN/A case MISCREG_SCTLR: 3802413SN/A { 3812413SN/A DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3822413SN/A SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3832413SN/A SCTLR new_sctlr = newVal; 3842640Sstever@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3852640Sstever@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3865606Snate@binkert.org tc->getITBPtr()->invalidateMiscReg(); 3872413SN/A tc->getDTBPtr()->invalidateMiscReg(); 3882413SN/A 3892413SN/A // Check if all CPUs are booted with caches enabled 3902413SN/A // so we can stop enforcing coherency of some kernel 3912413SN/A // structures manually. 3922413SN/A sys = tc->getSystemPtr(); 3932413SN/A for (x = 0; x < sys->numContexts(); x++) { 3942413SN/A oc = sys->getThreadContext(x); 3952413SN/A SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 3962522SN/A if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 3974475Sstever@eecs.umich.edu return; 3982413SN/A } 3992522SN/A 4002497SN/A for (x = 0; x < sys->numContexts(); x++) { 4012497SN/A oc = sys->getThreadContext(x); 4022497SN/A oc->getDTBPtr()->allCpusCaching(); 4034475Sstever@eecs.umich.edu oc->getITBPtr()->allCpusCaching(); 4042497SN/A 4054475Sstever@eecs.umich.edu // If CheckerCPU is connected, need to notify it. 4062522SN/A CheckerCPU *checker = oc->getCheckerCpuPtr(); 4074762Snate@binkert.org if (checker) { 4082413SN/A checker->getDTBPtr()->allCpusCaching(); 4092413SN/A checker->getITBPtr()->allCpusCaching(); 4102415SN/A } 4112415SN/A } 4122415SN/A return; 4132415SN/A } 4142415SN/A case MISCREG_TLBTR: 4152413SN/A case MISCREG_MVFR0: 4162413SN/A case MISCREG_MVFR1: 4173349Sbinkertn@umich.edu case MISCREG_MPIDR: 4182413SN/A case MISCREG_FPSID: 4194626Sstever@eecs.umich.edu return; 4202413SN/A case MISCREG_TLBIALLIS: 4212413SN/A case MISCREG_TLBIALL: 4222413SN/A sys = tc->getSystemPtr(); 4233349Sbinkertn@umich.edu for (x = 0; x < sys->numContexts(); x++) { 4242413SN/A oc = sys->getThreadContext(x); 4255314Sstever@gmail.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4265314Sstever@gmail.com oc->getITBPtr()->flushAll(); 4274929Sstever@gmail.com oc->getDTBPtr()->flushAll(); 4284929Sstever@gmail.com 4294929Sstever@gmail.com // If CheckerCPU is connected, need to notify it of a flush 4304929Sstever@gmail.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4314929Sstever@gmail.com if (checker) { 4324929Sstever@gmail.com checker->getITBPtr()->flushAll(); 4335314Sstever@gmail.com checker->getDTBPtr()->flushAll(); 4345314Sstever@gmail.com } 4352413SN/A } 4362413SN/A return; 4372914Ssaidi@eecs.umich.edu case MISCREG_ITLBIALL: 4382914Ssaidi@eecs.umich.edu tc->getITBPtr()->flushAll(); 4392914Ssaidi@eecs.umich.edu return; 4404467Sstever@eecs.umich.edu case MISCREG_DTLBIALL: 4414467Sstever@eecs.umich.edu tc->getDTBPtr()->flushAll(); 4424467Sstever@eecs.umich.edu return; 4434467Sstever@eecs.umich.edu case MISCREG_TLBIMVAIS: 4444467Sstever@eecs.umich.edu case MISCREG_TLBIMVA: 4452914Ssaidi@eecs.umich.edu sys = tc->getSystemPtr(); 4462914Ssaidi@eecs.umich.edu for (x = 0; x < sys->numContexts(); x++) { 4472914Ssaidi@eecs.umich.edu oc = sys->getThreadContext(x); 4482914Ssaidi@eecs.umich.edu assert(oc->getITBPtr() && oc->getDTBPtr()); 4492914Ssaidi@eecs.umich.edu oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4502914Ssaidi@eecs.umich.edu bits(newVal, 7,0)); 4512413SN/A oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4522391SN/A bits(newVal, 7,0)); 4532391SN/A 4542391SN/A CheckerCPU *checker = oc->getCheckerCpuPtr(); 4555477Snate@binkert.org if (checker) { 4565477Snate@binkert.org checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4575477Snate@binkert.org bits(newVal, 7,0)); 4582391SN/A checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4592391SN/A bits(newVal, 7,0)); 4602391SN/A } 4612391SN/A } 4622391SN/A return; 4632391SN/A case MISCREG_TLBIASIDIS: 4642391SN/A case MISCREG_TLBIASID: 4652391SN/A sys = tc->getSystemPtr(); 4662391SN/A for (x = 0; x < sys->numContexts(); x++) { 4672391SN/A oc = sys->getThreadContext(x); 4682391SN/A assert(oc->getITBPtr() && oc->getDTBPtr()); 4692391SN/A oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4702391SN/A oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4712391SN/A CheckerCPU *checker = oc->getCheckerCpuPtr(); 4722391SN/A if (checker) { 4732391SN/A checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4742391SN/A checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4752391SN/A } 4764762Snate@binkert.org } 4774762Snate@binkert.org return; 4782391SN/A case MISCREG_TLBIMVAAIS: 4792391SN/A case MISCREG_TLBIMVAA: 4802391SN/A sys = tc->getSystemPtr(); 4812391SN/A for (x = 0; x < sys->numContexts(); x++) { 4822391SN/A oc = sys->getThreadContext(x); 4832391SN/A assert(oc->getITBPtr() && oc->getDTBPtr()); 4842391SN/A oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4852391SN/A oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4862391SN/A 4872391SN/A CheckerCPU *checker = oc->getCheckerCpuPtr(); 4882391SN/A if (checker) { 4892391SN/A checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4905477Snate@binkert.org checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4915477Snate@binkert.org } 4925477Snate@binkert.org } 4932391SN/A return; 4942391SN/A case MISCREG_ITLBIMVA: 4952391SN/A tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4962391SN/A bits(newVal, 7,0)); 4972391SN/A return; 4982391SN/A case MISCREG_DTLBIMVA: 4992391SN/A tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5002391SN/A bits(newVal, 7,0)); 5012391SN/A return; 5022391SN/A case MISCREG_ITLBIASID: 5032391SN/A tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5042391SN/A return; 5052391SN/A case MISCREG_DTLBIASID: 5062391SN/A tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5072391SN/A return; 5082391SN/A case MISCREG_ACTLR: 5092391SN/A warn("Not doing anything for write of miscreg ACTLR\n"); 5102391SN/A break; 5112391SN/A case MISCREG_PMCR: 5122391SN/A { 5132391SN/A // Performance counters not implemented. Instead, interpret 5142391SN/A // a reset command to this register to reset the simulator 5152391SN/A // statistics. 5162391SN/A // PMCR_E | PMCR_P | PMCR_C 5172391SN/A const int ResetAndEnableCounters = 0x7; 5183012Ssaidi@eecs.umich.edu if (newVal == ResetAndEnableCounters) { 5193012Ssaidi@eecs.umich.edu inform("Resetting all simobject stats\n"); 5203012Ssaidi@eecs.umich.edu Stats::schedStatEvent(false, true); 5214762Snate@binkert.org break; 5222391SN/A } 5234762Snate@binkert.org } 5244762Snate@binkert.org case MISCREG_PMCCNTR: 5252391SN/A case MISCREG_PMSELR: 5263012Ssaidi@eecs.umich.edu warn("Not doing anything for write to miscreg %s\n", 5272391SN/A miscRegName[misc_reg]); 5282391SN/A break; 5292391SN/A case MISCREG_V2PCWPR: 5302391SN/A case MISCREG_V2PCWPW: 5312391SN/A case MISCREG_V2PCWUR: 5322391SN/A case MISCREG_V2PCWUW: 5332391SN/A case MISCREG_V2POWPR: 5342391SN/A case MISCREG_V2POWPW: 5352391SN/A case MISCREG_V2POWUR: 5362391SN/A case MISCREG_V2POWUW: 5374762Snate@binkert.org { 5382391SN/A RequestPtr req = new Request; 5394762Snate@binkert.org unsigned flags; 5404762Snate@binkert.org BaseTLB::Mode mode; 5412391SN/A Fault fault; 5422391SN/A switch(misc_reg) { 5434762Snate@binkert.org case MISCREG_V2PCWPR: 5444762Snate@binkert.org flags = TLB::MustBeOne; 5452391SN/A mode = BaseTLB::Read; 5462391SN/A break; 5472391SN/A case MISCREG_V2PCWPW: 5482391SN/A flags = TLB::MustBeOne; 5492391SN/A mode = BaseTLB::Write; 5502391SN/A break; 5513012Ssaidi@eecs.umich.edu case MISCREG_V2PCWUR: 5522391SN/A flags = TLB::MustBeOne | TLB::UserMode; 5532391SN/A mode = BaseTLB::Read; 5542391SN/A break; 5552391SN/A case MISCREG_V2PCWUW: 5562391SN/A flags = TLB::MustBeOne | TLB::UserMode; 5572391SN/A mode = BaseTLB::Write; 5582391SN/A break; 5592391SN/A default: 5602391SN/A panic("Security Extensions not implemented!"); 5612391SN/A } 5622391SN/A warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 5632391SN/A req->setVirt(0, val, 1, flags, tc->pcState().pc(), 5642391SN/A Request::funcMasterId); 5652391SN/A fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 5664762Snate@binkert.org if (fault == NoFault) { 5674762Snate@binkert.org miscRegs[MISCREG_PAR] = 5682391SN/A (req->getPaddr() & 0xfffff000) | 5694762Snate@binkert.org (tc->getDTBPtr()->getAttr() ); 5702391SN/A DPRINTF(MiscRegs, 571 "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 572 val, miscRegs[MISCREG_PAR]); 573 } 574 else { 575 // Set fault bit and FSR 576 FSR fsr = miscRegs[MISCREG_DFSR]; 577 miscRegs[MISCREG_PAR] = 578 (fsr.ext << 6) | 579 (fsr.fsHigh << 5) | 580 (fsr.fsLow << 1) | 581 0x1; // F bit 582 } 583 return; 584 } 585 case MISCREG_CONTEXTIDR: 586 case MISCREG_PRRR: 587 case MISCREG_NMRR: 588 case MISCREG_DACR: 589 tc->getITBPtr()->invalidateMiscReg(); 590 tc->getDTBPtr()->invalidateMiscReg(); 591 break; 592 case MISCREG_CPSR_MODE: 593 // This miscreg is used by copy*Regs to set the CPSR mode 594 // without updating other CPSR variables. It's used to 595 // make sure the register map is in such a state that we can 596 // see all of the registers for the copy. 597 updateRegMap(val); 598 return; 599 case MISCREG_L2CTLR: 600 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 601 miscRegName[misc_reg], uint32_t(val)); 602 } 603 } 604 setMiscRegNoEffect(misc_reg, newVal); 605} 606 607} 608