isa.cc revision 8870
17405SAli.Saidi@ARM.com/* 28868SMatt.Horsnell@arm.com * Copyright (c) 2010-2012 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 428733Sgeoffrey.blake@arm.com#include "config/use_checker.hh" 438232Snate@binkert.org#include "debug/Arm.hh" 448232Snate@binkert.org#include "debug/MiscRegs.hh" 457678Sgblack@eecs.umich.edu#include "sim/faults.hh" 468059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 478284SAli.Saidi@ARM.com#include "sim/system.hh" 487405SAli.Saidi@ARM.com 498733Sgeoffrey.blake@arm.com#if USE_CHECKER 508733Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 518733Sgeoffrey.blake@arm.com#endif 528733Sgeoffrey.blake@arm.com 537405SAli.Saidi@ARM.comnamespace ArmISA 547405SAli.Saidi@ARM.com{ 557405SAli.Saidi@ARM.com 567427Sgblack@eecs.umich.eduvoid 577427Sgblack@eecs.umich.eduISA::clear() 587427Sgblack@eecs.umich.edu{ 597427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 608299Schander.sudanthi@arm.com uint32_t midr = miscRegs[MISCREG_MIDR]; 617427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 627427Sgblack@eecs.umich.edu CPSR cpsr = 0; 637427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 647427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 657427Sgblack@eecs.umich.edu updateRegMap(cpsr); 667427Sgblack@eecs.umich.edu 677427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 687604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 697427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 707427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 717427Sgblack@eecs.umich.edu sctlr.u = 1; 727427Sgblack@eecs.umich.edu sctlr.xp = 1; 737427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 747427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 757427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 767427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 777427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 787427Sgblack@eecs.umich.edu 798299Schander.sudanthi@arm.com // Preserve MIDR accross reset 808299Schander.sudanthi@arm.com miscRegs[MISCREG_MIDR] = midr; 818299Schander.sudanthi@arm.com 827427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 837427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 847427Sgblack@eecs.umich.edu 857427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 867427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 877427Sgblack@eecs.umich.edu 887427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 897427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 907427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 917427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 927427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 937427Sgblack@eecs.umich.edu mvfr0.divide = 1; 947427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 957427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 967427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 977427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 987427Sgblack@eecs.umich.edu 997427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1007427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1017427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1027427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1037427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1047427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1057427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1067427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1077427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1087427Sgblack@eecs.umich.edu 1097427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1107427Sgblack@eecs.umich.edu 1117436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1127436Sdam.sunwoo@arm.com 1137436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1147436Sdam.sunwoo@arm.com (1 << 19) | // 19 1157436Sdam.sunwoo@arm.com (0 << 18) | // 18 1167436Sdam.sunwoo@arm.com (0 << 17) | // 17 1177436Sdam.sunwoo@arm.com (1 << 16) | // 16 1187436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1197436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1207436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1217436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1227436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1237436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1247436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1257436Sdam.sunwoo@arm.com 0; // 1:0 1267436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1277436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1287436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1297436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1307436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1317436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1327436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1337436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1347436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1357436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1367436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1377436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1387436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1397436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1407436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1417436Sdam.sunwoo@arm.com 0; // 1:0 1427436Sdam.sunwoo@arm.com 1437644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1447644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1458147SAli.Saidi@ARM.com 1468147SAli.Saidi@ARM.com // See section B4.1.84 of ARM ARM 1478147SAli.Saidi@ARM.com // All values are latest for ARMv7-A profile 1488520SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1498147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1508147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1518147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1528147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1538147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1548147SAli.Saidi@ARM.com 1557427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1567427Sgblack@eecs.umich.edu} 1577427Sgblack@eecs.umich.edu 1587405SAli.Saidi@ARM.comMiscReg 1597405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1607405SAli.Saidi@ARM.com{ 1617405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1627614Sminkyu.jeong@arm.com 1637614Sminkyu.jeong@arm.com int flat_idx; 1647614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1657614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1667614Sminkyu.jeong@arm.com else 1677614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1687614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1697614Sminkyu.jeong@arm.com 1707614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1717614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1727614Sminkyu.jeong@arm.com return val; 1737405SAli.Saidi@ARM.com} 1747405SAli.Saidi@ARM.com 1757405SAli.Saidi@ARM.com 1767405SAli.Saidi@ARM.comMiscReg 1777405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1787405SAli.Saidi@ARM.com{ 1797405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1807405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1817720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1827720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1837720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1847405SAli.Saidi@ARM.com return cpsr; 1857405SAli.Saidi@ARM.com } 1867757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 1877405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1887405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1897757SAli.Saidi@ARM.com 1907405SAli.Saidi@ARM.com switch (misc_reg) { 1918284SAli.Saidi@ARM.com case MISCREG_MPIDR: 1928284SAli.Saidi@ARM.com return tc->cpuId(); 1938284SAli.Saidi@ARM.com break; 1948468Swade.walker@arm.com case MISCREG_ID_MMFR0: 1958468Swade.walker@arm.com return 0x03; // VMSAv7 support 1968468Swade.walker@arm.com case MISCREG_ID_MMFR2: 1978468Swade.walker@arm.com return 0x01230000; // no HW access | WFI stalling | ISB and DSB 1988468Swade.walker@arm.com // | all TLB maintenance | no Harvard 1998284SAli.Saidi@ARM.com case MISCREG_ID_MMFR3: 2008284SAli.Saidi@ARM.com return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 2018284SAli.Saidi@ARM.com // BP Maint | Cache Maint Set/way | Cache Maint MVA 2027405SAli.Saidi@ARM.com case MISCREG_CLIDR: 2037731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 2048468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 2058468Swade.walker@arm.com "ARM implementations.\n"); 2068468Swade.walker@arm.com return 0x00200000; 2077405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 2087731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 2097405SAli.Saidi@ARM.com "always reads as 0.\n"); 2107405SAli.Saidi@ARM.com break; 2117405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2127588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 2137588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 2147588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2158299Schander.sudanthi@arm.com case MISCREG_ID_PFR1: 2168870SAli.Saidi@ARM.com return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4 2177583SAli.Saidi@arm.com case MISCREG_CTR: 2187583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2197583SAli.Saidi@arm.com case MISCREG_ACTLR: 2207583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2217583SAli.Saidi@arm.com break; 2227583SAli.Saidi@arm.com case MISCREG_PMCR: 2237583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2247583SAli.Saidi@arm.com case MISCREG_PMSELR: 2258299Schander.sudanthi@arm.com warn("Not doing anything for read to miscreg %s\n", 2267583SAli.Saidi@arm.com miscRegName[misc_reg]); 2277583SAli.Saidi@arm.com break; 2288302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 2298302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 2307783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2317783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2327783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2337783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2348549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 2358868SMatt.Horsnell@arm.com { 2368868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 2378868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 2388868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 2398868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2408868SMatt.Horsnell@arm.com return l2ctlr; 2418868SMatt.Horsnell@arm.com } 2428868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 2438868SMatt.Horsnell@arm.com /* For now just implement the version number. 2448868SMatt.Horsnell@arm.com * Return 0 as we don't support debug architecture yet. 2458868SMatt.Horsnell@arm.com */ 2468868SMatt.Horsnell@arm.com return 0; 2478868SMatt.Horsnell@arm.com case MISCREG_DBGDSCR_INT: 2488868SMatt.Horsnell@arm.com return 0; 2497405SAli.Saidi@ARM.com } 2507405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2517405SAli.Saidi@ARM.com} 2527405SAli.Saidi@ARM.com 2537405SAli.Saidi@ARM.comvoid 2547405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2557405SAli.Saidi@ARM.com{ 2567405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2577614Sminkyu.jeong@arm.com 2587614Sminkyu.jeong@arm.com int flat_idx; 2597614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2607614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2617614Sminkyu.jeong@arm.com else 2627614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2637614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2647614Sminkyu.jeong@arm.com 2657614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2667614Sminkyu.jeong@arm.com flat_idx, val); 2677405SAli.Saidi@ARM.com} 2687405SAli.Saidi@ARM.com 2697405SAli.Saidi@ARM.comvoid 2707405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2717405SAli.Saidi@ARM.com{ 2727749SAli.Saidi@ARM.com 2737405SAli.Saidi@ARM.com MiscReg newVal = val; 2748284SAli.Saidi@ARM.com int x; 2758284SAli.Saidi@ARM.com System *sys; 2768284SAli.Saidi@ARM.com ThreadContext *oc; 2778284SAli.Saidi@ARM.com 2787405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2797405SAli.Saidi@ARM.com updateRegMap(val); 2807749SAli.Saidi@ARM.com 2817749SAli.Saidi@ARM.com 2827749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2837749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 2847405SAli.Saidi@ARM.com CPSR cpsr = val; 2857749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 2867749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 2877749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 2887749SAli.Saidi@ARM.com } 2897749SAli.Saidi@ARM.com 2907614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2917614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2927720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2937720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 2947720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 2958733Sgeoffrey.blake@arm.com#if USE_CHECKER 2968733Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 2978733Sgeoffrey.blake@arm.com#else 2987720Sgblack@eecs.umich.edu tc->pcState(pc); 2998733Sgeoffrey.blake@arm.com#endif //USE_CHECKER 3007408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3017405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 3027405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 3037405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 3047408Sgblack@eecs.umich.edu } else { 3057408Sgblack@eecs.umich.edu switch (misc_reg) { 3067408Sgblack@eecs.umich.edu case MISCREG_CPACR: 3077408Sgblack@eecs.umich.edu { 3088206SWilliam.Wang@arm.com 3098206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 3108206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 3118206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 3128206SWilliam.Wang@arm.com // be writable 3138206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 3148206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 3158206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 3168206SWilliam.Wang@arm.com newVal &= cpacrMask; 3178206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3188206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 3197408Sgblack@eecs.umich.edu } 3207408Sgblack@eecs.umich.edu break; 3217408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3227731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 3238206SWilliam.Wang@arm.com return; 3247408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3257408Sgblack@eecs.umich.edu { 3267408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3277408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3287408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3297408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3307408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3317408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3327408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3337408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3347408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3357408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3367408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3377408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3387408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3397408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3407408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3417408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3427408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3437408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3447408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3457408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3467408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3477408Sgblack@eecs.umich.edu } 3487408Sgblack@eecs.umich.edu break; 3498302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 3508302SAli.Saidi@ARM.com { 3518302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 3528302SAli.Saidi@ARM.com newVal = miscRegs[MISCREG_CPSR] | newVal; 3538302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 3548302SAli.Saidi@ARM.com } 3558302SAli.Saidi@ARM.com break; 3567783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 3577783SGiacomo.Gabrielli@arm.com { 3587783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3597783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3607783SGiacomo.Gabrielli@arm.com } 3617783SGiacomo.Gabrielli@arm.com break; 3627783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 3637783SGiacomo.Gabrielli@arm.com { 3647783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3657783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3667783SGiacomo.Gabrielli@arm.com } 3677783SGiacomo.Gabrielli@arm.com break; 3687408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3697408Sgblack@eecs.umich.edu { 3708206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 3718206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 3727408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3737408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3747408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3757408Sgblack@eecs.umich.edu } 3767408Sgblack@eecs.umich.edu break; 3777408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3787408Sgblack@eecs.umich.edu { 3797408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3807408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3817408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3827408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3837408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3847749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3857749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3868527SAli.Saidi@ARM.com 3878527SAli.Saidi@ARM.com // Check if all CPUs are booted with caches enabled 3888527SAli.Saidi@ARM.com // so we can stop enforcing coherency of some kernel 3898527SAli.Saidi@ARM.com // structures manually. 3908527SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 3918527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 3928527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 3938527SAli.Saidi@ARM.com SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 3948527SAli.Saidi@ARM.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 3958527SAli.Saidi@ARM.com return; 3968527SAli.Saidi@ARM.com } 3978527SAli.Saidi@ARM.com 3988527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 3998527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4008527SAli.Saidi@ARM.com oc->getDTBPtr()->allCpusCaching(); 4018527SAli.Saidi@ARM.com oc->getITBPtr()->allCpusCaching(); 4028733Sgeoffrey.blake@arm.com#if USE_CHECKER 4038733Sgeoffrey.blake@arm.com CheckerCPU *checker = 4048733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 4058733Sgeoffrey.blake@arm.com if (checker) { 4068733Sgeoffrey.blake@arm.com checker->getDTBPtr()->allCpusCaching(); 4078733Sgeoffrey.blake@arm.com checker->getITBPtr()->allCpusCaching(); 4088733Sgeoffrey.blake@arm.com } 4098733Sgeoffrey.blake@arm.com#endif 4108527SAli.Saidi@ARM.com } 4117408Sgblack@eecs.umich.edu return; 4127408Sgblack@eecs.umich.edu } 4137408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 4147408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 4157408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 4167408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 4177408Sgblack@eecs.umich.edu case MISCREG_FPSID: 4187408Sgblack@eecs.umich.edu return; 4197408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 4207408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 4218284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4228284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4238284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4248284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4258284SAli.Saidi@ARM.com oc->getITBPtr()->flushAll(); 4268284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAll(); 4278733Sgeoffrey.blake@arm.com#if USE_CHECKER 4288733Sgeoffrey.blake@arm.com CheckerCPU *checker = 4298733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 4308733Sgeoffrey.blake@arm.com if (checker) { 4318733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAll(); 4328733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAll(); 4338733Sgeoffrey.blake@arm.com } 4348733Sgeoffrey.blake@arm.com#endif 4358284SAli.Saidi@ARM.com } 4367408Sgblack@eecs.umich.edu return; 4377408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 4387408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 4397408Sgblack@eecs.umich.edu return; 4407408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 4417408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 4427408Sgblack@eecs.umich.edu return; 4437408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 4447408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 4458284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4468284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4478284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4488284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4498284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4508284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4518284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4528284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4538733Sgeoffrey.blake@arm.com#if USE_CHECKER 4548733Sgeoffrey.blake@arm.com CheckerCPU *checker = 4558733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 4568733Sgeoffrey.blake@arm.com if (checker) { 4578733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4588733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 4598733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4608733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 4618733Sgeoffrey.blake@arm.com } 4628733Sgeoffrey.blake@arm.com#endif 4638284SAli.Saidi@ARM.com } 4647408Sgblack@eecs.umich.edu return; 4657408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 4667408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 4678284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4688284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4698284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4708284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4718284SAli.Saidi@ARM.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4728284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4738733Sgeoffrey.blake@arm.com#if USE_CHECKER 4748733Sgeoffrey.blake@arm.com CheckerCPU *checker = 4758733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 4768733Sgeoffrey.blake@arm.com if (checker) { 4778733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4788733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4798733Sgeoffrey.blake@arm.com } 4808733Sgeoffrey.blake@arm.com#endif 4818284SAli.Saidi@ARM.com } 4827408Sgblack@eecs.umich.edu return; 4837408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 4847408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 4858284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4868284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4878284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4888284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4898284SAli.Saidi@ARM.com oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4908284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4918733Sgeoffrey.blake@arm.com#if USE_CHECKER 4928733Sgeoffrey.blake@arm.com CheckerCPU *checker = 4938733Sgeoffrey.blake@arm.com dynamic_cast<CheckerCPU*>(oc->getCheckerCpuPtr()); 4948733Sgeoffrey.blake@arm.com if (checker) { 4958733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4968733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4978733Sgeoffrey.blake@arm.com } 4988733Sgeoffrey.blake@arm.com#endif 4998284SAli.Saidi@ARM.com } 5007408Sgblack@eecs.umich.edu return; 5017408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 5027408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5037408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5047408Sgblack@eecs.umich.edu return; 5057408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 5067408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5077408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5087408Sgblack@eecs.umich.edu return; 5097408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 5107408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5117408Sgblack@eecs.umich.edu return; 5127408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 5137408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5147405SAli.Saidi@ARM.com return; 5157583SAli.Saidi@arm.com case MISCREG_ACTLR: 5167583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 5177583SAli.Saidi@arm.com break; 5187583SAli.Saidi@arm.com case MISCREG_PMCR: 5198059SAli.Saidi@ARM.com { 5208059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 5218059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 5228059SAli.Saidi@ARM.com // statistics. 5238059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 5248059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 5258059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 5268059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 5278059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 5288059SAli.Saidi@ARM.com break; 5298059SAli.Saidi@ARM.com } 5308059SAli.Saidi@ARM.com } 5317583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 5327583SAli.Saidi@arm.com case MISCREG_PMSELR: 5337583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 5347583SAli.Saidi@arm.com miscRegName[misc_reg]); 5357583SAli.Saidi@arm.com break; 5367436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 5377436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 5387436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5397436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5407436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 5417436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 5427436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 5437436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 5447436Sdam.sunwoo@arm.com { 5457436Sdam.sunwoo@arm.com RequestPtr req = new Request; 5467436Sdam.sunwoo@arm.com unsigned flags; 5477436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 5487436Sdam.sunwoo@arm.com Fault fault; 5497436Sdam.sunwoo@arm.com switch(misc_reg) { 5507436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 5517436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 5527436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 5537436Sdam.sunwoo@arm.com break; 5547436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 5557436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 5567436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 5577436Sdam.sunwoo@arm.com break; 5587436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5597436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5607436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 5617436Sdam.sunwoo@arm.com break; 5627436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5637436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5647436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 5657436Sdam.sunwoo@arm.com break; 5667442Ssaidi@eecs.umich.edu default: 5677436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 5687436Sdam.sunwoo@arm.com } 5698208SAli.Saidi@ARM.com warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 5708832SAli.Saidi@ARM.com req->setVirt(0, val, 1, flags, tc->pcState().pc(), 5718832SAli.Saidi@ARM.com Request::funcMasterId); 5727436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 5737436Sdam.sunwoo@arm.com if (fault == NoFault) { 5747436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5757436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 5767436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 5777436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 5787436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 5797436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 5807436Sdam.sunwoo@arm.com } 5817436Sdam.sunwoo@arm.com else { 5827436Sdam.sunwoo@arm.com // Set fault bit and FSR 5837436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 5847436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5857436Sdam.sunwoo@arm.com (fsr.ext << 6) | 5867436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 5877436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 5887436Sdam.sunwoo@arm.com 0x1; // F bit 5897436Sdam.sunwoo@arm.com } 5907436Sdam.sunwoo@arm.com return; 5917436Sdam.sunwoo@arm.com } 5927749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 5937749SAli.Saidi@ARM.com case MISCREG_PRRR: 5947749SAli.Saidi@ARM.com case MISCREG_NMRR: 5957749SAli.Saidi@ARM.com case MISCREG_DACR: 5967749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 5977749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 5987749SAli.Saidi@ARM.com break; 5998208SAli.Saidi@ARM.com case MISCREG_CPSR_MODE: 6008208SAli.Saidi@ARM.com // This miscreg is used by copy*Regs to set the CPSR mode 6018208SAli.Saidi@ARM.com // without updating other CPSR variables. It's used to 6028208SAli.Saidi@ARM.com // make sure the register map is in such a state that we can 6038208SAli.Saidi@ARM.com // see all of the registers for the copy. 6048208SAli.Saidi@ARM.com updateRegMap(val); 6058208SAli.Saidi@ARM.com return; 6068549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6078549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 6088549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 6097405SAli.Saidi@ARM.com } 6107405SAli.Saidi@ARM.com } 6117405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 6127405SAli.Saidi@ARM.com} 6137405SAli.Saidi@ARM.com 6147405SAli.Saidi@ARM.com} 615