isa.cc revision 8549
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 428232Snate@binkert.org#include "debug/Arm.hh" 438232Snate@binkert.org#include "debug/MiscRegs.hh" 447678Sgblack@eecs.umich.edu#include "sim/faults.hh" 458059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 468284SAli.Saidi@ARM.com#include "sim/system.hh" 477405SAli.Saidi@ARM.com 487405SAli.Saidi@ARM.comnamespace ArmISA 497405SAli.Saidi@ARM.com{ 507405SAli.Saidi@ARM.com 517427Sgblack@eecs.umich.eduvoid 527427Sgblack@eecs.umich.eduISA::clear() 537427Sgblack@eecs.umich.edu{ 547427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 558299Schander.sudanthi@arm.com uint32_t midr = miscRegs[MISCREG_MIDR]; 567427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 577427Sgblack@eecs.umich.edu CPSR cpsr = 0; 587427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 597427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 607427Sgblack@eecs.umich.edu updateRegMap(cpsr); 617427Sgblack@eecs.umich.edu 627427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 637604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 647427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 657427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 667427Sgblack@eecs.umich.edu sctlr.u = 1; 677427Sgblack@eecs.umich.edu sctlr.xp = 1; 687427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 697427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 707427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 717427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 727427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 737427Sgblack@eecs.umich.edu 748299Schander.sudanthi@arm.com // Preserve MIDR accross reset 758299Schander.sudanthi@arm.com miscRegs[MISCREG_MIDR] = midr; 768299Schander.sudanthi@arm.com 777427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 787427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 797427Sgblack@eecs.umich.edu 807427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 817427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 827427Sgblack@eecs.umich.edu 837427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 847427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 857427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 867427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 877427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 887427Sgblack@eecs.umich.edu mvfr0.divide = 1; 897427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 907427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 917427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 927427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 937427Sgblack@eecs.umich.edu 947427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 957427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 967427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 977427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 987427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 997427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1007427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1017427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1027427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1037427Sgblack@eecs.umich.edu 1047427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1057427Sgblack@eecs.umich.edu 1067436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1077436Sdam.sunwoo@arm.com 1087436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1097436Sdam.sunwoo@arm.com (1 << 19) | // 19 1107436Sdam.sunwoo@arm.com (0 << 18) | // 18 1117436Sdam.sunwoo@arm.com (0 << 17) | // 17 1127436Sdam.sunwoo@arm.com (1 << 16) | // 16 1137436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1147436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1157436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1167436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1177436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1187436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1197436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1207436Sdam.sunwoo@arm.com 0; // 1:0 1217436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1227436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1237436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1247436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1257436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1267436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1277436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1287436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1297436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1307436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1317436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1327436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1337436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1347436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1357436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1367436Sdam.sunwoo@arm.com 0; // 1:0 1377436Sdam.sunwoo@arm.com 1387644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1397644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1408147SAli.Saidi@ARM.com 1418147SAli.Saidi@ARM.com // See section B4.1.84 of ARM ARM 1428147SAli.Saidi@ARM.com // All values are latest for ARMv7-A profile 1438520SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR0] = 0x02101111; 1448147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1458147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1468147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1478147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1488147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1498147SAli.Saidi@ARM.com 1507427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1517427Sgblack@eecs.umich.edu} 1527427Sgblack@eecs.umich.edu 1537405SAli.Saidi@ARM.comMiscReg 1547405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1557405SAli.Saidi@ARM.com{ 1567405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1577614Sminkyu.jeong@arm.com 1587614Sminkyu.jeong@arm.com int flat_idx; 1597614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1607614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1617614Sminkyu.jeong@arm.com else 1627614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1637614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1647614Sminkyu.jeong@arm.com 1657614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1667614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1677614Sminkyu.jeong@arm.com return val; 1687405SAli.Saidi@ARM.com} 1697405SAli.Saidi@ARM.com 1707405SAli.Saidi@ARM.com 1717405SAli.Saidi@ARM.comMiscReg 1727405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1737405SAli.Saidi@ARM.com{ 1747405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1757405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1767720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1777720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1787720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1797405SAli.Saidi@ARM.com return cpsr; 1807405SAli.Saidi@ARM.com } 1817757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 1827405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1837405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1847757SAli.Saidi@ARM.com 1857405SAli.Saidi@ARM.com switch (misc_reg) { 1868284SAli.Saidi@ARM.com case MISCREG_MPIDR: 1878284SAli.Saidi@ARM.com return tc->cpuId(); 1888284SAli.Saidi@ARM.com break; 1898468Swade.walker@arm.com case MISCREG_ID_MMFR0: 1908468Swade.walker@arm.com return 0x03; // VMSAv7 support 1918468Swade.walker@arm.com case MISCREG_ID_MMFR2: 1928468Swade.walker@arm.com return 0x01230000; // no HW access | WFI stalling | ISB and DSB 1938468Swade.walker@arm.com // | all TLB maintenance | no Harvard 1948284SAli.Saidi@ARM.com case MISCREG_ID_MMFR3: 1958284SAli.Saidi@ARM.com return 0xF0102211; // SuperSec | Coherent TLB | Bcast Maint | 1968284SAli.Saidi@ARM.com // BP Maint | Cache Maint Set/way | Cache Maint MVA 1977405SAli.Saidi@ARM.com case MISCREG_CLIDR: 1987731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 1998468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 2008468Swade.walker@arm.com "ARM implementations.\n"); 2018468Swade.walker@arm.com return 0x00200000; 2027405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 2037731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 2047405SAli.Saidi@ARM.com "always reads as 0.\n"); 2057405SAli.Saidi@ARM.com break; 2067405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2077588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 2087588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 2097588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2108299Schander.sudanthi@arm.com case MISCREG_ID_PFR1: 2118299Schander.sudanthi@arm.com warn("reading unimplmented register ID_PFR1"); 2128299Schander.sudanthi@arm.com return 0; 2137583SAli.Saidi@arm.com case MISCREG_CTR: 2147583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2157583SAli.Saidi@arm.com case MISCREG_ACTLR: 2167583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2177583SAli.Saidi@arm.com break; 2187583SAli.Saidi@arm.com case MISCREG_PMCR: 2197583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2207583SAli.Saidi@arm.com case MISCREG_PMSELR: 2218299Schander.sudanthi@arm.com warn("Not doing anything for read to miscreg %s\n", 2227583SAli.Saidi@arm.com miscRegName[misc_reg]); 2237583SAli.Saidi@arm.com break; 2248302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 2258302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 2267783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2277783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2287783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2297783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2308549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 2318549Sdaniel.johnson@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 2328549Sdaniel.johnson@arm.com L2CTLR l2ctlr = 0; 2338549Sdaniel.johnson@arm.com // b00:1CPU to b11:4CPUs 2348549Sdaniel.johnson@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2358549Sdaniel.johnson@arm.com return l2ctlr; 2367405SAli.Saidi@ARM.com } 2377405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2387405SAli.Saidi@ARM.com} 2397405SAli.Saidi@ARM.com 2407405SAli.Saidi@ARM.comvoid 2417405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2427405SAli.Saidi@ARM.com{ 2437405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2447614Sminkyu.jeong@arm.com 2457614Sminkyu.jeong@arm.com int flat_idx; 2467614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2477614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2487614Sminkyu.jeong@arm.com else 2497614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2507614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2517614Sminkyu.jeong@arm.com 2527614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2537614Sminkyu.jeong@arm.com flat_idx, val); 2547405SAli.Saidi@ARM.com} 2557405SAli.Saidi@ARM.com 2567405SAli.Saidi@ARM.comvoid 2577405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2587405SAli.Saidi@ARM.com{ 2597749SAli.Saidi@ARM.com 2607405SAli.Saidi@ARM.com MiscReg newVal = val; 2618284SAli.Saidi@ARM.com int x; 2628284SAli.Saidi@ARM.com System *sys; 2638284SAli.Saidi@ARM.com ThreadContext *oc; 2648284SAli.Saidi@ARM.com 2657405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2667405SAli.Saidi@ARM.com updateRegMap(val); 2677749SAli.Saidi@ARM.com 2687749SAli.Saidi@ARM.com 2697749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2707749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 2717405SAli.Saidi@ARM.com CPSR cpsr = val; 2727749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 2737749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 2747749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 2757749SAli.Saidi@ARM.com } 2767749SAli.Saidi@ARM.com 2777614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2787614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2797720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2807720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 2817720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 2827720Sgblack@eecs.umich.edu tc->pcState(pc); 2837408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2847405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2857405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 2867405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 2877408Sgblack@eecs.umich.edu } else { 2887408Sgblack@eecs.umich.edu switch (misc_reg) { 2897408Sgblack@eecs.umich.edu case MISCREG_CPACR: 2907408Sgblack@eecs.umich.edu { 2918206SWilliam.Wang@arm.com 2928206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 2938206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 2948206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 2958206SWilliam.Wang@arm.com // be writable 2968206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 2978206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 2988206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 2998206SWilliam.Wang@arm.com newVal &= cpacrMask; 3008206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3018206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 3027408Sgblack@eecs.umich.edu } 3037408Sgblack@eecs.umich.edu break; 3047408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3057731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 3068206SWilliam.Wang@arm.com return; 3077408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3087408Sgblack@eecs.umich.edu { 3097408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3107408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3117408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3127408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3137408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3147408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3157408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3167408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3177408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3187408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3197408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3207408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3217408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3227408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3237408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3247408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3257408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3267408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3277408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3287408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3297408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3307408Sgblack@eecs.umich.edu } 3317408Sgblack@eecs.umich.edu break; 3328302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 3338302SAli.Saidi@ARM.com { 3348302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 3358302SAli.Saidi@ARM.com newVal = miscRegs[MISCREG_CPSR] | newVal; 3368302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 3378302SAli.Saidi@ARM.com } 3388302SAli.Saidi@ARM.com break; 3397783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 3407783SGiacomo.Gabrielli@arm.com { 3417783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3427783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3437783SGiacomo.Gabrielli@arm.com } 3447783SGiacomo.Gabrielli@arm.com break; 3457783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 3467783SGiacomo.Gabrielli@arm.com { 3477783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3487783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3497783SGiacomo.Gabrielli@arm.com } 3507783SGiacomo.Gabrielli@arm.com break; 3517408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3527408Sgblack@eecs.umich.edu { 3538206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 3548206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 3557408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3567408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3577408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3587408Sgblack@eecs.umich.edu } 3597408Sgblack@eecs.umich.edu break; 3607408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3617408Sgblack@eecs.umich.edu { 3627408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3637408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3647408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3657408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3667408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3677749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3687749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3698527SAli.Saidi@ARM.com 3708527SAli.Saidi@ARM.com // Check if all CPUs are booted with caches enabled 3718527SAli.Saidi@ARM.com // so we can stop enforcing coherency of some kernel 3728527SAli.Saidi@ARM.com // structures manually. 3738527SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 3748527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 3758527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 3768527SAli.Saidi@ARM.com SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 3778527SAli.Saidi@ARM.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 3788527SAli.Saidi@ARM.com return; 3798527SAli.Saidi@ARM.com } 3808527SAli.Saidi@ARM.com 3818527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 3828527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 3838527SAli.Saidi@ARM.com oc->getDTBPtr()->allCpusCaching(); 3848527SAli.Saidi@ARM.com oc->getITBPtr()->allCpusCaching(); 3858527SAli.Saidi@ARM.com } 3867408Sgblack@eecs.umich.edu return; 3877408Sgblack@eecs.umich.edu } 3887408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3897408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3907408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3917408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3927408Sgblack@eecs.umich.edu case MISCREG_FPSID: 3937408Sgblack@eecs.umich.edu return; 3947408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3957408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3968284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 3978284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 3988284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 3998284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4008284SAli.Saidi@ARM.com oc->getITBPtr()->flushAll(); 4018284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAll(); 4028284SAli.Saidi@ARM.com } 4037408Sgblack@eecs.umich.edu return; 4047408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 4057408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 4067408Sgblack@eecs.umich.edu return; 4077408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 4087408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 4097408Sgblack@eecs.umich.edu return; 4107408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 4117408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 4128284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4138284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4148284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4158284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4168284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4178284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4188284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4198284SAli.Saidi@ARM.com bits(newVal, 7,0)); 4208284SAli.Saidi@ARM.com } 4217408Sgblack@eecs.umich.edu return; 4227408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 4237408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 4248284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4258284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4268284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4278284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4288284SAli.Saidi@ARM.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4298284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4308284SAli.Saidi@ARM.com } 4317408Sgblack@eecs.umich.edu return; 4327408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 4337408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 4348284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4358284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4368284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4378284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4388284SAli.Saidi@ARM.com oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 4398284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 4408284SAli.Saidi@ARM.com } 4417408Sgblack@eecs.umich.edu return; 4427408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 4437408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4447408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4457408Sgblack@eecs.umich.edu return; 4467408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 4477408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 4487408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 4497408Sgblack@eecs.umich.edu return; 4507408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 4517408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 4527408Sgblack@eecs.umich.edu return; 4537408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 4547408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 4557405SAli.Saidi@ARM.com return; 4567583SAli.Saidi@arm.com case MISCREG_ACTLR: 4577583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 4587583SAli.Saidi@arm.com break; 4597583SAli.Saidi@arm.com case MISCREG_PMCR: 4608059SAli.Saidi@ARM.com { 4618059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 4628059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 4638059SAli.Saidi@ARM.com // statistics. 4648059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 4658059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 4668059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 4678059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 4688059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 4698059SAli.Saidi@ARM.com break; 4708059SAli.Saidi@ARM.com } 4718059SAli.Saidi@ARM.com } 4727583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 4737583SAli.Saidi@arm.com case MISCREG_PMSELR: 4747583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 4757583SAli.Saidi@arm.com miscRegName[misc_reg]); 4767583SAli.Saidi@arm.com break; 4777436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4787436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4797436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4807436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4817436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 4827436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 4837436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 4847436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 4857436Sdam.sunwoo@arm.com { 4867436Sdam.sunwoo@arm.com RequestPtr req = new Request; 4877436Sdam.sunwoo@arm.com unsigned flags; 4887436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 4897436Sdam.sunwoo@arm.com Fault fault; 4907436Sdam.sunwoo@arm.com switch(misc_reg) { 4917436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4927436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4937436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4947436Sdam.sunwoo@arm.com break; 4957436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4967436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4977436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4987436Sdam.sunwoo@arm.com break; 4997436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5007436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5017436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 5027436Sdam.sunwoo@arm.com break; 5037436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5047436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 5057436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 5067436Sdam.sunwoo@arm.com break; 5077442Ssaidi@eecs.umich.edu default: 5087436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 5097436Sdam.sunwoo@arm.com } 5108208SAli.Saidi@ARM.com warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 5117720Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc()); 5127436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 5137436Sdam.sunwoo@arm.com if (fault == NoFault) { 5147436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5157436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 5167436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 5177436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 5187436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 5197436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 5207436Sdam.sunwoo@arm.com } 5217436Sdam.sunwoo@arm.com else { 5227436Sdam.sunwoo@arm.com // Set fault bit and FSR 5237436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 5247436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 5257436Sdam.sunwoo@arm.com (fsr.ext << 6) | 5267436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 5277436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 5287436Sdam.sunwoo@arm.com 0x1; // F bit 5297436Sdam.sunwoo@arm.com } 5307436Sdam.sunwoo@arm.com return; 5317436Sdam.sunwoo@arm.com } 5327749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 5337749SAli.Saidi@ARM.com case MISCREG_PRRR: 5347749SAli.Saidi@ARM.com case MISCREG_NMRR: 5357749SAli.Saidi@ARM.com case MISCREG_DACR: 5367749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 5377749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 5387749SAli.Saidi@ARM.com break; 5398208SAli.Saidi@ARM.com case MISCREG_CPSR_MODE: 5408208SAli.Saidi@ARM.com // This miscreg is used by copy*Regs to set the CPSR mode 5418208SAli.Saidi@ARM.com // without updating other CPSR variables. It's used to 5428208SAli.Saidi@ARM.com // make sure the register map is in such a state that we can 5438208SAli.Saidi@ARM.com // see all of the registers for the copy. 5448208SAli.Saidi@ARM.com updateRegMap(val); 5458208SAli.Saidi@ARM.com return; 5468549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 5478549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 5488549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 5497405SAli.Saidi@ARM.com } 5507405SAli.Saidi@ARM.com } 5517405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 5527405SAli.Saidi@ARM.com} 5537405SAli.Saidi@ARM.com 5547405SAli.Saidi@ARM.com} 555