isa.cc revision 8232
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 428232Snate@binkert.org#include "debug/Arm.hh" 438232Snate@binkert.org#include "debug/MiscRegs.hh" 447678Sgblack@eecs.umich.edu#include "sim/faults.hh" 458059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 467405SAli.Saidi@ARM.com 477405SAli.Saidi@ARM.comnamespace ArmISA 487405SAli.Saidi@ARM.com{ 497405SAli.Saidi@ARM.com 507427Sgblack@eecs.umich.eduvoid 517427Sgblack@eecs.umich.eduISA::clear() 527427Sgblack@eecs.umich.edu{ 537427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 547427Sgblack@eecs.umich.edu 557427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 567427Sgblack@eecs.umich.edu CPSR cpsr = 0; 577427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 587427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 597427Sgblack@eecs.umich.edu updateRegMap(cpsr); 607427Sgblack@eecs.umich.edu 617427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 627604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 637427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 647427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 657427Sgblack@eecs.umich.edu sctlr.u = 1; 667427Sgblack@eecs.umich.edu sctlr.xp = 1; 677427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 687427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 697427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 707427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 717427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 727427Sgblack@eecs.umich.edu 737427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 747427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 757427Sgblack@eecs.umich.edu 767427Sgblack@eecs.umich.edu /* 777427Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 787427Sgblack@eecs.umich.edu * Variant = 0, 797427Sgblack@eecs.umich.edu */ 807427Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 817645Sali.saidi@arm.com (0x35 << 24) | // Implementor is '5' from "M5" 827645Sali.saidi@arm.com (0 << 20) | // Variant 837645Sali.saidi@arm.com (0xf << 16) | // Architecture from CPUID scheme 847645Sali.saidi@arm.com (0xf00 << 4) | // Primary part number 857645Sali.saidi@arm.com (0 << 0) | // Revision 867427Sgblack@eecs.umich.edu 0; 877427Sgblack@eecs.umich.edu 887427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 897427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 907427Sgblack@eecs.umich.edu 917427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 927427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 937427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 947427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 957427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 967427Sgblack@eecs.umich.edu mvfr0.divide = 1; 977427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 987427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 997427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1007427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1017427Sgblack@eecs.umich.edu 1027427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1037427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1047427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1057427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1067427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1077427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1087427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1097427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1107427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1117427Sgblack@eecs.umich.edu 1127427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1137427Sgblack@eecs.umich.edu 1147436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1157436Sdam.sunwoo@arm.com 1167436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1177436Sdam.sunwoo@arm.com (1 << 19) | // 19 1187436Sdam.sunwoo@arm.com (0 << 18) | // 18 1197436Sdam.sunwoo@arm.com (0 << 17) | // 17 1207436Sdam.sunwoo@arm.com (1 << 16) | // 16 1217436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1227436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1237436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1247436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1257436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1267436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1277436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1287436Sdam.sunwoo@arm.com 0; // 1:0 1297436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1307436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1317436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1327436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1337436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1347436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1357436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1367436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1377436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1387436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1397436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1407436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1417436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1427436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1437436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1447436Sdam.sunwoo@arm.com 0; // 1:0 1457436Sdam.sunwoo@arm.com 1467644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1477644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1488147SAli.Saidi@ARM.com 1498147SAli.Saidi@ARM.com // See section B4.1.84 of ARM ARM 1508147SAli.Saidi@ARM.com // All values are latest for ARMv7-A profile 1518147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR0] = 0x01101111; 1528147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR1] = 0x02112111; 1538147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR2] = 0x21232141; 1548147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR3] = 0x01112131; 1558147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR4] = 0x10010142; 1568147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR5] = 0x00000000; 1578147SAli.Saidi@ARM.com 1587427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1597427Sgblack@eecs.umich.edu} 1607427Sgblack@eecs.umich.edu 1617405SAli.Saidi@ARM.comMiscReg 1627405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1637405SAli.Saidi@ARM.com{ 1647405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1657614Sminkyu.jeong@arm.com 1667614Sminkyu.jeong@arm.com int flat_idx; 1677614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1687614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1697614Sminkyu.jeong@arm.com else 1707614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1717614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1727614Sminkyu.jeong@arm.com 1737614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1747614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1757614Sminkyu.jeong@arm.com return val; 1767405SAli.Saidi@ARM.com} 1777405SAli.Saidi@ARM.com 1787405SAli.Saidi@ARM.com 1797405SAli.Saidi@ARM.comMiscReg 1807405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1817405SAli.Saidi@ARM.com{ 1827405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1837405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1847720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 1857720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 1867720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 1877405SAli.Saidi@ARM.com return cpsr; 1887405SAli.Saidi@ARM.com } 1897757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 1907405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1917405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1927757SAli.Saidi@ARM.com 1937405SAli.Saidi@ARM.com switch (misc_reg) { 1947405SAli.Saidi@ARM.com case MISCREG_CLIDR: 1957731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 1967405SAli.Saidi@ARM.com break; 1977405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 1987731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 1997405SAli.Saidi@ARM.com "always reads as 0.\n"); 2007405SAli.Saidi@ARM.com break; 2017405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 2027588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 2037588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 2047588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 2057583SAli.Saidi@arm.com case MISCREG_ID_MMFR0: 2067583SAli.Saidi@arm.com return 0x03; //VMSAz7 2077583SAli.Saidi@arm.com case MISCREG_CTR: 2087583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2097583SAli.Saidi@arm.com case MISCREG_ACTLR: 2107583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2117583SAli.Saidi@arm.com break; 2127583SAli.Saidi@arm.com case MISCREG_PMCR: 2137583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2147583SAli.Saidi@arm.com case MISCREG_PMSELR: 2157583SAli.Saidi@arm.com warn("Not doing anyhting for read to miscreg %s\n", 2167583SAli.Saidi@arm.com miscRegName[misc_reg]); 2177583SAli.Saidi@arm.com break; 2187783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2197783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2207783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2217783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2227405SAli.Saidi@ARM.com } 2237405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2247405SAli.Saidi@ARM.com} 2257405SAli.Saidi@ARM.com 2267405SAli.Saidi@ARM.comvoid 2277405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2287405SAli.Saidi@ARM.com{ 2297405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2307614Sminkyu.jeong@arm.com 2317614Sminkyu.jeong@arm.com int flat_idx; 2327614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2337614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2347614Sminkyu.jeong@arm.com else 2357614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2367614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2377614Sminkyu.jeong@arm.com 2387614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2397614Sminkyu.jeong@arm.com flat_idx, val); 2407405SAli.Saidi@ARM.com} 2417405SAli.Saidi@ARM.com 2427405SAli.Saidi@ARM.comvoid 2437405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2447405SAli.Saidi@ARM.com{ 2457749SAli.Saidi@ARM.com 2467405SAli.Saidi@ARM.com MiscReg newVal = val; 2477405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2487405SAli.Saidi@ARM.com updateRegMap(val); 2497749SAli.Saidi@ARM.com 2507749SAli.Saidi@ARM.com 2517749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 2527749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 2537405SAli.Saidi@ARM.com CPSR cpsr = val; 2547749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 2557749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 2567749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 2577749SAli.Saidi@ARM.com } 2587749SAli.Saidi@ARM.com 2597614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2607614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2617720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2627720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 2637720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 2647720Sgblack@eecs.umich.edu tc->pcState(pc); 2657408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2667405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2677405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 2687405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 2697408Sgblack@eecs.umich.edu } else { 2707408Sgblack@eecs.umich.edu switch (misc_reg) { 2717408Sgblack@eecs.umich.edu case MISCREG_CPACR: 2727408Sgblack@eecs.umich.edu { 2738206SWilliam.Wang@arm.com 2748206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 2758206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 2768206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 2778206SWilliam.Wang@arm.com // be writable 2788206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 2798206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 2808206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 2818206SWilliam.Wang@arm.com newVal &= cpacrMask; 2828206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 2838206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 2847408Sgblack@eecs.umich.edu } 2857408Sgblack@eecs.umich.edu break; 2867408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2877731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 2888206SWilliam.Wang@arm.com return; 2897408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 2907408Sgblack@eecs.umich.edu { 2917408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 2927408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 2937408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 2947408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 2957408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 2967408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 2977408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 2987408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 2997408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3007408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3017408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3027408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3037408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3047408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3057408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3067408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3077408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3087408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3097408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3107408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3117408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3127408Sgblack@eecs.umich.edu } 3137408Sgblack@eecs.umich.edu break; 3147783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 3157783SGiacomo.Gabrielli@arm.com { 3167783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 3177783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3187783SGiacomo.Gabrielli@arm.com } 3197783SGiacomo.Gabrielli@arm.com break; 3207783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 3217783SGiacomo.Gabrielli@arm.com { 3227783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 3237783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 3247783SGiacomo.Gabrielli@arm.com } 3257783SGiacomo.Gabrielli@arm.com break; 3267408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3277408Sgblack@eecs.umich.edu { 3288206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 3298206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 3307408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3317408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3327408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3337408Sgblack@eecs.umich.edu } 3347408Sgblack@eecs.umich.edu break; 3357408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3367408Sgblack@eecs.umich.edu { 3377408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3387408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3397408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3407408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3417408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3427749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3437749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3447408Sgblack@eecs.umich.edu return; 3457408Sgblack@eecs.umich.edu } 3467408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3477408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3487408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3497408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3507408Sgblack@eecs.umich.edu case MISCREG_FPSID: 3517408Sgblack@eecs.umich.edu return; 3527408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3537408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3547731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3557408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3567408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3577408Sgblack@eecs.umich.edu return; 3587408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3597408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3607408Sgblack@eecs.umich.edu return; 3617408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3627408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3637408Sgblack@eecs.umich.edu return; 3647408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 3657408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3667731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3677408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3687408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3697408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3707408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3717408Sgblack@eecs.umich.edu return; 3727408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 3737408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 3747731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3757408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3767408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3777408Sgblack@eecs.umich.edu return; 3787408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 3797408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 3807731SAli.Saidi@ARM.com warn_once("Need to flush all TLBs in MP\n"); 3817408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3827408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3837408Sgblack@eecs.umich.edu return; 3847408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 3857408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3867408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3877408Sgblack@eecs.umich.edu return; 3887408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 3897408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3907408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3917408Sgblack@eecs.umich.edu return; 3927408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 3937408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3947408Sgblack@eecs.umich.edu return; 3957408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 3967408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3977405SAli.Saidi@ARM.com return; 3987583SAli.Saidi@arm.com case MISCREG_ACTLR: 3997583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 4007583SAli.Saidi@arm.com break; 4017583SAli.Saidi@arm.com case MISCREG_PMCR: 4028059SAli.Saidi@ARM.com { 4038059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 4048059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 4058059SAli.Saidi@ARM.com // statistics. 4068059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 4078059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 4088059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 4098059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 4108059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 4118059SAli.Saidi@ARM.com break; 4128059SAli.Saidi@ARM.com } 4138059SAli.Saidi@ARM.com } 4147583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 4157583SAli.Saidi@arm.com case MISCREG_PMSELR: 4167583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 4177583SAli.Saidi@arm.com miscRegName[misc_reg]); 4187583SAli.Saidi@arm.com break; 4197436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4207436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4217436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4227436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4237436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 4247436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 4257436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 4267436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 4277436Sdam.sunwoo@arm.com { 4287436Sdam.sunwoo@arm.com RequestPtr req = new Request; 4297436Sdam.sunwoo@arm.com unsigned flags; 4307436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 4317436Sdam.sunwoo@arm.com Fault fault; 4327436Sdam.sunwoo@arm.com switch(misc_reg) { 4337436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 4347436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4357436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4367436Sdam.sunwoo@arm.com break; 4377436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4387436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4397436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4407436Sdam.sunwoo@arm.com break; 4417436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4427436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4437436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4447436Sdam.sunwoo@arm.com break; 4457436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4467436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4477436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4487436Sdam.sunwoo@arm.com break; 4497442Ssaidi@eecs.umich.edu default: 4507436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 4517436Sdam.sunwoo@arm.com } 4528208SAli.Saidi@ARM.com warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 4537720Sgblack@eecs.umich.edu req->setVirt(0, val, 1, flags, tc->pcState().pc()); 4547436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4557436Sdam.sunwoo@arm.com if (fault == NoFault) { 4567436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4577436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 4587436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 4597436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 4607436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4617436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 4627436Sdam.sunwoo@arm.com } 4637436Sdam.sunwoo@arm.com else { 4647436Sdam.sunwoo@arm.com // Set fault bit and FSR 4657436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 4667436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4677436Sdam.sunwoo@arm.com (fsr.ext << 6) | 4687436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 4697436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 4707436Sdam.sunwoo@arm.com 0x1; // F bit 4717436Sdam.sunwoo@arm.com } 4727436Sdam.sunwoo@arm.com return; 4737436Sdam.sunwoo@arm.com } 4747749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 4757749SAli.Saidi@ARM.com case MISCREG_PRRR: 4767749SAli.Saidi@ARM.com case MISCREG_NMRR: 4777749SAli.Saidi@ARM.com case MISCREG_DACR: 4787749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 4797749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 4807749SAli.Saidi@ARM.com break; 4818208SAli.Saidi@ARM.com case MISCREG_CPSR_MODE: 4828208SAli.Saidi@ARM.com // This miscreg is used by copy*Regs to set the CPSR mode 4838208SAli.Saidi@ARM.com // without updating other CPSR variables. It's used to 4848208SAli.Saidi@ARM.com // make sure the register map is in such a state that we can 4858208SAli.Saidi@ARM.com // see all of the registers for the copy. 4868208SAli.Saidi@ARM.com updateRegMap(val); 4878208SAli.Saidi@ARM.com return; 4887405SAli.Saidi@ARM.com } 4897405SAli.Saidi@ARM.com } 4907405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 4917405SAli.Saidi@ARM.com} 4927405SAli.Saidi@ARM.com 4937405SAli.Saidi@ARM.com} 494