isa.cc revision 7645
17405SAli.Saidi@ARM.com/* 27405SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 427405SAli.Saidi@ARM.com 437405SAli.Saidi@ARM.comnamespace ArmISA 447405SAli.Saidi@ARM.com{ 457405SAli.Saidi@ARM.com 467427Sgblack@eecs.umich.eduvoid 477427Sgblack@eecs.umich.eduISA::clear() 487427Sgblack@eecs.umich.edu{ 497427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 507427Sgblack@eecs.umich.edu 517427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 527427Sgblack@eecs.umich.edu CPSR cpsr = 0; 537427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 547427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 557427Sgblack@eecs.umich.edu updateRegMap(cpsr); 567427Sgblack@eecs.umich.edu 577427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 587604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 597427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 607427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 617427Sgblack@eecs.umich.edu sctlr.u = 1; 627427Sgblack@eecs.umich.edu sctlr.xp = 1; 637427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 647427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 657427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 667427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 677427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 687427Sgblack@eecs.umich.edu 697427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 707427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 717427Sgblack@eecs.umich.edu 727427Sgblack@eecs.umich.edu /* 737427Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 747427Sgblack@eecs.umich.edu * Variant = 0, 757427Sgblack@eecs.umich.edu */ 767427Sgblack@eecs.umich.edu miscRegs[MISCREG_MIDR] = 777645Sali.saidi@arm.com (0x35 << 24) | // Implementor is '5' from "M5" 787645Sali.saidi@arm.com (0 << 20) | // Variant 797645Sali.saidi@arm.com (0xf << 16) | // Architecture from CPUID scheme 807645Sali.saidi@arm.com (0xf00 << 4) | // Primary part number 817645Sali.saidi@arm.com (0 << 0) | // Revision 827427Sgblack@eecs.umich.edu 0; 837427Sgblack@eecs.umich.edu 847427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 857427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 867427Sgblack@eecs.umich.edu 877427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 887427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 897427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 907427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 917427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 927427Sgblack@eecs.umich.edu mvfr0.divide = 1; 937427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 947427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 957427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 967427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 977427Sgblack@eecs.umich.edu 987427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 997427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1007427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1017427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1027427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1037427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1047427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1057427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1067427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1077427Sgblack@eecs.umich.edu 1087427Sgblack@eecs.umich.edu miscRegs[MISCREG_MPIDR] = 0; 1097427Sgblack@eecs.umich.edu 1107436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1117436Sdam.sunwoo@arm.com 1127436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1137436Sdam.sunwoo@arm.com (1 << 19) | // 19 1147436Sdam.sunwoo@arm.com (0 << 18) | // 18 1157436Sdam.sunwoo@arm.com (0 << 17) | // 17 1167436Sdam.sunwoo@arm.com (1 << 16) | // 16 1177436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1187436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1197436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1207436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1217436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1227436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1237436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1247436Sdam.sunwoo@arm.com 0; // 1:0 1257436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1267436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1277436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1287436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1297436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1307436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1317436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1327436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1337436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1347436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1357436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1367436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1377436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1387436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1397436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1407436Sdam.sunwoo@arm.com 0; // 1:0 1417436Sdam.sunwoo@arm.com 1427644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1437644Sali.saidi@arm.com miscRegs[MISCREG_FPSID] = 0x410430A0; 1447427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1457427Sgblack@eecs.umich.edu} 1467427Sgblack@eecs.umich.edu 1477405SAli.Saidi@ARM.comMiscReg 1487405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) 1497405SAli.Saidi@ARM.com{ 1507405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1517614Sminkyu.jeong@arm.com 1527614Sminkyu.jeong@arm.com int flat_idx; 1537614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1547614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1557614Sminkyu.jeong@arm.com else 1567614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1577614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1587614Sminkyu.jeong@arm.com 1597614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1607614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1617614Sminkyu.jeong@arm.com return val; 1627405SAli.Saidi@ARM.com} 1637405SAli.Saidi@ARM.com 1647405SAli.Saidi@ARM.com 1657405SAli.Saidi@ARM.comMiscReg 1667405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1677405SAli.Saidi@ARM.com{ 1687405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 1697405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 1707405SAli.Saidi@ARM.com Addr pc = tc->readPC(); 1717405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcJBitShift)) 1727405SAli.Saidi@ARM.com cpsr.j = 1; 1737405SAli.Saidi@ARM.com else 1747405SAli.Saidi@ARM.com cpsr.j = 0; 1757405SAli.Saidi@ARM.com if (pc & (ULL(1) << PcTBitShift)) 1767405SAli.Saidi@ARM.com cpsr.t = 1; 1777405SAli.Saidi@ARM.com else 1787405SAli.Saidi@ARM.com cpsr.t = 0; 1797405SAli.Saidi@ARM.com return cpsr; 1807405SAli.Saidi@ARM.com } 1817405SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START && 1827405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 1837405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 1847405SAli.Saidi@ARM.com miscRegName[misc_reg]); 1857405SAli.Saidi@ARM.com } 1867405SAli.Saidi@ARM.com switch (misc_reg) { 1877405SAli.Saidi@ARM.com case MISCREG_CLIDR: 1887405SAli.Saidi@ARM.com warn("The clidr register always reports 0 caches.\n"); 1897405SAli.Saidi@ARM.com break; 1907405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 1917405SAli.Saidi@ARM.com warn("The ccsidr register isn't implemented and " 1927405SAli.Saidi@ARM.com "always reads as 0.\n"); 1937405SAli.Saidi@ARM.com break; 1947405SAli.Saidi@ARM.com case MISCREG_ID_PFR0: 1957588SAli.Saidi@arm.com warn("Returning thumbEE disabled for now since we don't support CP14" 1967588SAli.Saidi@arm.com "config registers and jumping to ThumbEE vectors\n"); 1977588SAli.Saidi@arm.com return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 1987583SAli.Saidi@arm.com case MISCREG_ID_MMFR0: 1997583SAli.Saidi@arm.com return 0x03; //VMSAz7 2007583SAli.Saidi@arm.com case MISCREG_CTR: 2017583SAli.Saidi@arm.com return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 2027583SAli.Saidi@arm.com case MISCREG_ACTLR: 2037583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2047583SAli.Saidi@arm.com break; 2057583SAli.Saidi@arm.com case MISCREG_PMCR: 2067583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2077583SAli.Saidi@arm.com case MISCREG_PMSELR: 2087583SAli.Saidi@arm.com warn("Not doing anyhting for read to miscreg %s\n", 2097583SAli.Saidi@arm.com miscRegName[misc_reg]); 2107583SAli.Saidi@arm.com break; 2117583SAli.Saidi@arm.com 2127405SAli.Saidi@ARM.com } 2137405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2147405SAli.Saidi@ARM.com} 2157405SAli.Saidi@ARM.com 2167405SAli.Saidi@ARM.comvoid 2177405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 2187405SAli.Saidi@ARM.com{ 2197405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 2207614Sminkyu.jeong@arm.com 2217614Sminkyu.jeong@arm.com int flat_idx; 2227614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 2237614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 2247614Sminkyu.jeong@arm.com else 2257614Sminkyu.jeong@arm.com flat_idx = misc_reg; 2267614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 2277614Sminkyu.jeong@arm.com 2287614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 2297614Sminkyu.jeong@arm.com flat_idx, val); 2307405SAli.Saidi@ARM.com} 2317405SAli.Saidi@ARM.com 2327405SAli.Saidi@ARM.comvoid 2337405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 2347405SAli.Saidi@ARM.com{ 2357405SAli.Saidi@ARM.com MiscReg newVal = val; 2367405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2377405SAli.Saidi@ARM.com updateRegMap(val); 2387405SAli.Saidi@ARM.com CPSR cpsr = val; 2397614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 2407614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 2417405SAli.Saidi@ARM.com Addr npc = tc->readNextPC() & ~PcModeMask; 2427405SAli.Saidi@ARM.com if (cpsr.j) 2437405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcJBitShift); 2447405SAli.Saidi@ARM.com if (cpsr.t) 2457405SAli.Saidi@ARM.com npc = npc | (ULL(1) << PcTBitShift); 2467405SAli.Saidi@ARM.com 2477405SAli.Saidi@ARM.com tc->setNextPC(npc); 2487408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 2497405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 2507405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 2517405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 2527408Sgblack@eecs.umich.edu } else { 2537408Sgblack@eecs.umich.edu switch (misc_reg) { 2547408Sgblack@eecs.umich.edu case MISCREG_ITSTATE: 2557408Sgblack@eecs.umich.edu { 2567408Sgblack@eecs.umich.edu ITSTATE itstate = newVal; 2577408Sgblack@eecs.umich.edu CPSR cpsr = miscRegs[MISCREG_CPSR]; 2587408Sgblack@eecs.umich.edu cpsr.it1 = itstate.bottom2; 2597408Sgblack@eecs.umich.edu cpsr.it2 = itstate.top6; 2607408Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 2617408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, 2627408Sgblack@eecs.umich.edu "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 2637408Sgblack@eecs.umich.edu (uint8_t)itstate, (uint32_t)cpsr); 2647405SAli.Saidi@ARM.com } 2657408Sgblack@eecs.umich.edu break; 2667408Sgblack@eecs.umich.edu case MISCREG_CPACR: 2677408Sgblack@eecs.umich.edu { 2687408Sgblack@eecs.umich.edu CPACR newCpacr = 0; 2697408Sgblack@eecs.umich.edu CPACR valCpacr = val; 2707408Sgblack@eecs.umich.edu newCpacr.cp10 = valCpacr.cp10; 2717408Sgblack@eecs.umich.edu newCpacr.cp11 = valCpacr.cp11; 2727640Sgblack@eecs.umich.edu //XXX d32dis isn't implemented. The manual says whether or not 2737640Sgblack@eecs.umich.edu //it works is implementation defined. 2747640Sgblack@eecs.umich.edu newCpacr.asedis = valCpacr.asedis; 2757408Sgblack@eecs.umich.edu newVal = newCpacr; 2767408Sgblack@eecs.umich.edu } 2777408Sgblack@eecs.umich.edu break; 2787408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 2797408Sgblack@eecs.umich.edu warn("The csselr register isn't implemented.\n"); 2807408Sgblack@eecs.umich.edu break; 2817408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 2827408Sgblack@eecs.umich.edu { 2837408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 2847408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 2857408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 2867408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 2877408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 2887408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 2897408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 2907408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 2917408Sgblack@eecs.umich.edu fpscrMask.len = ones; 2927408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 2937408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 2947408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 2957408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 2967408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 2977408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 2987408Sgblack@eecs.umich.edu fpscrMask.v = ones; 2997408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3007408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3017408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3027408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3037408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3047408Sgblack@eecs.umich.edu } 3057408Sgblack@eecs.umich.edu break; 3067408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 3077408Sgblack@eecs.umich.edu { 3087408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 3097408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 3107408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 3117408Sgblack@eecs.umich.edu } 3127408Sgblack@eecs.umich.edu break; 3137408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 3147408Sgblack@eecs.umich.edu { 3157408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 3167408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 3177408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 3187408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 3197408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 3207408Sgblack@eecs.umich.edu return; 3217408Sgblack@eecs.umich.edu } 3227408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 3237408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 3247408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 3257408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 3267408Sgblack@eecs.umich.edu case MISCREG_FPSID: 3277408Sgblack@eecs.umich.edu return; 3287408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 3297408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 3307408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3317408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3327408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3337408Sgblack@eecs.umich.edu return; 3347408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 3357408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 3367408Sgblack@eecs.umich.edu return; 3377408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 3387408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 3397408Sgblack@eecs.umich.edu return; 3407408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 3417408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 3427408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3437408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3447408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3457408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3467408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3477408Sgblack@eecs.umich.edu return; 3487408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 3497408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 3507408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3517408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3527408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3537408Sgblack@eecs.umich.edu return; 3547408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 3557408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 3567408Sgblack@eecs.umich.edu warn("Need to flush all TLBs in MP\n"); 3577408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 3587408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 3597408Sgblack@eecs.umich.edu return; 3607408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 3617408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3627408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3637408Sgblack@eecs.umich.edu return; 3647408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 3657408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 3667408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 3677408Sgblack@eecs.umich.edu return; 3687408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 3697408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 3707408Sgblack@eecs.umich.edu return; 3717408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 3727408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 3737405SAli.Saidi@ARM.com return; 3747583SAli.Saidi@arm.com case MISCREG_ACTLR: 3757583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 3767583SAli.Saidi@arm.com break; 3777583SAli.Saidi@arm.com case MISCREG_PMCR: 3787583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 3797583SAli.Saidi@arm.com case MISCREG_PMSELR: 3807583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 3817583SAli.Saidi@arm.com miscRegName[misc_reg]); 3827583SAli.Saidi@arm.com break; 3837436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 3847436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 3857436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 3867436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 3877436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 3887436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 3897436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 3907436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 3917436Sdam.sunwoo@arm.com { 3927436Sdam.sunwoo@arm.com RequestPtr req = new Request; 3937436Sdam.sunwoo@arm.com unsigned flags; 3947436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 3957436Sdam.sunwoo@arm.com Fault fault; 3967436Sdam.sunwoo@arm.com switch(misc_reg) { 3977436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 3987436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 3997436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4007436Sdam.sunwoo@arm.com break; 4017436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 4027436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 4037436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4047436Sdam.sunwoo@arm.com break; 4057436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 4067436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4077436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 4087436Sdam.sunwoo@arm.com break; 4097436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 4107436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 4117436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 4127436Sdam.sunwoo@arm.com break; 4137442Ssaidi@eecs.umich.edu default: 4147436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 4157436Sdam.sunwoo@arm.com } 4167436Sdam.sunwoo@arm.com req->setVirt(0, val, 1, flags, tc->readPC()); 4177436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 4187436Sdam.sunwoo@arm.com if (fault == NoFault) { 4197436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4207436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 4217436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 4227436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 4237436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 4247436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 4257436Sdam.sunwoo@arm.com } 4267436Sdam.sunwoo@arm.com else { 4277436Sdam.sunwoo@arm.com // Set fault bit and FSR 4287436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 4297436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 4307436Sdam.sunwoo@arm.com (fsr.ext << 6) | 4317436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 4327436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 4337436Sdam.sunwoo@arm.com 0x1; // F bit 4347436Sdam.sunwoo@arm.com } 4357436Sdam.sunwoo@arm.com return; 4367436Sdam.sunwoo@arm.com } 4377405SAli.Saidi@ARM.com } 4387405SAli.Saidi@ARM.com } 4397405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 4407405SAli.Saidi@ARM.com} 4417405SAli.Saidi@ARM.com 4427405SAli.Saidi@ARM.com} 443