isa.cc revision 7640
16242Sgblack@eecs.umich.edu/* 210324SCurtis.Dunham@arm.com * Copyright (c) 2010 ARM Limited 37093Sgblack@eecs.umich.edu * All rights reserved 47093Sgblack@eecs.umich.edu * 57093Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67093Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77093Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87093Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97093Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107093Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117093Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127093Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137093Sgblack@eecs.umich.edu * 146242Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 156242Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 166242Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 176242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 186242Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 196242Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 206242Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 216242Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 226242Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 236242Sgblack@eecs.umich.edu * this software without specific prior written permission. 246242Sgblack@eecs.umich.edu * 256242Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266242Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276242Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286242Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296242Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306242Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316242Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326242Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336242Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346242Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356242Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366242Sgblack@eecs.umich.edu * 376242Sgblack@eecs.umich.edu * Authors: Gabe Black 386242Sgblack@eecs.umich.edu * Ali Saidi 396242Sgblack@eecs.umich.edu */ 406242Sgblack@eecs.umich.edu 4110037SARM gem5 Developers#include "arch/arm/isa.hh" 426242Sgblack@eecs.umich.edu 436242Sgblack@eecs.umich.edunamespace ArmISA 446242Sgblack@eecs.umich.edu{ 456242Sgblack@eecs.umich.edu 4610037SARM gem5 Developersvoid 4710037SARM gem5 DevelopersISA::clear() 486242Sgblack@eecs.umich.edu{ 499256SAndreas.Sandberg@arm.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 506242Sgblack@eecs.umich.edu 5110037SARM gem5 Developers memset(miscRegs, 0, sizeof(miscRegs)); 5210037SARM gem5 Developers CPSR cpsr = 0; 5310037SARM gem5 Developers cpsr.mode = MODE_USER; 546242Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 556242Sgblack@eecs.umich.edu updateRegMap(cpsr); 566242Sgblack@eecs.umich.edu 576242Sgblack@eecs.umich.edu SCTLR sctlr = 0; 586242Sgblack@eecs.umich.edu sctlr.te = (bool)sctlr_rst.te; 596242Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 606242Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 616242Sgblack@eecs.umich.edu sctlr.u = 1; 626242Sgblack@eecs.umich.edu sctlr.xp = 1; 636242Sgblack@eecs.umich.edu sctlr.rao2 = 1; 646242Sgblack@eecs.umich.edu sctlr.rao3 = 1; 656242Sgblack@eecs.umich.edu sctlr.rao4 = 1; 666242Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 676242Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 686242Sgblack@eecs.umich.edu 696242Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 706242Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 716242Sgblack@eecs.umich.edu 727111Sgblack@eecs.umich.edu /* 736242Sgblack@eecs.umich.edu * Implemented = '5' from "M5", 746242Sgblack@eecs.umich.edu * Variant = 0, 756242Sgblack@eecs.umich.edu */ 7610037SARM gem5 Developers miscRegs[MISCREG_MIDR] = 7710037SARM gem5 Developers (0x35 << 24) | //Implementor is '5' from "M5" 7810037SARM gem5 Developers (0 << 20) | //Variant 7910037SARM gem5 Developers (0xf << 16) | //Architecture from CPUID scheme 8010037SARM gem5 Developers (0 << 4) | //Primary part number 8110037SARM gem5 Developers (0 << 0) | //Revision 8210037SARM gem5 Developers 0; 8310037SARM gem5 Developers 8410037SARM gem5 Developers // Separate Instruction and Data TLBs. 8510037SARM gem5 Developers miscRegs[MISCREG_TLBTR] = 1; 8610037SARM gem5 Developers 8710037SARM gem5 Developers MVFR0 mvfr0 = 0; 8810037SARM gem5 Developers mvfr0.advSimdRegisters = 2; 8910037SARM gem5 Developers mvfr0.singlePrecision = 2; 9010037SARM gem5 Developers mvfr0.doublePrecision = 2; 917259Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 9210037SARM gem5 Developers mvfr0.divide = 1; 9310037SARM gem5 Developers mvfr0.squareRoot = 1; 9410037SARM gem5 Developers mvfr0.shortVectors = 1; 9510037SARM gem5 Developers mvfr0.roundingModes = 1; 9610037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 9710037SARM gem5 Developers 9810037SARM gem5 Developers MVFR1 mvfr1 = 0; 9910037SARM gem5 Developers mvfr1.flushToZero = 1; 10010037SARM gem5 Developers mvfr1.defaultNaN = 1; 10110037SARM gem5 Developers mvfr1.advSimdLoadStore = 1; 10210037SARM gem5 Developers mvfr1.advSimdInteger = 1; 10310037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 10410037SARM gem5 Developers mvfr1.advSimdHalfPrecision = 1; 10510037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 10610037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 10710037SARM gem5 Developers 1088868SMatt.Horsnell@arm.com miscRegs[MISCREG_MPIDR] = 0; 10910037SARM gem5 Developers 11010037SARM gem5 Developers // Reset values of PRRR and NMRR are implementation dependent 11110037SARM gem5 Developers 11210037SARM gem5 Developers miscRegs[MISCREG_PRRR] = 11310037SARM gem5 Developers (1 << 19) | // 19 11410037SARM gem5 Developers (0 << 18) | // 18 11510037SARM gem5 Developers (0 << 17) | // 17 11610037SARM gem5 Developers (1 << 16) | // 16 11710037SARM gem5 Developers (2 << 14) | // 15:14 11810037SARM gem5 Developers (0 << 12) | // 13:12 11910037SARM gem5 Developers (2 << 10) | // 11:10 12010037SARM gem5 Developers (2 << 8) | // 9:8 12110037SARM gem5 Developers (2 << 6) | // 7:6 12210037SARM gem5 Developers (2 << 4) | // 5:4 12310037SARM gem5 Developers (1 << 2) | // 3:2 12410037SARM gem5 Developers 0; // 1:0 12510037SARM gem5 Developers miscRegs[MISCREG_NMRR] = 12610037SARM gem5 Developers (1 << 30) | // 31:30 12710037SARM gem5 Developers (0 << 26) | // 27:26 12810037SARM gem5 Developers (0 << 24) | // 25:24 12910037SARM gem5 Developers (3 << 22) | // 23:22 13010037SARM gem5 Developers (2 << 20) | // 21:20 13110037SARM gem5 Developers (0 << 18) | // 19:18 13210037SARM gem5 Developers (0 << 16) | // 17:16 13310037SARM gem5 Developers (1 << 14) | // 15:14 13410037SARM gem5 Developers (0 << 12) | // 13:12 13510037SARM gem5 Developers (2 << 10) | // 11:10 13610037SARM gem5 Developers (0 << 8) | // 9:8 13710037SARM gem5 Developers (3 << 6) | // 7:6 13810037SARM gem5 Developers (2 << 4) | // 5:4 13910037SARM gem5 Developers (0 << 2) | // 3:2 14010037SARM gem5 Developers 0; // 1:0 14110037SARM gem5 Developers 14210037SARM gem5 Developers //XXX We need to initialize the rest of the state. 14310037SARM gem5 Developers} 14410037SARM gem5 Developers 14510037SARM gem5 DevelopersMiscReg 14610037SARM gem5 DevelopersISA::readMiscRegNoEffect(int misc_reg) 14710037SARM gem5 Developers{ 14810037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 14910037SARM gem5 Developers 15010037SARM gem5 Developers int flat_idx; 15110037SARM gem5 Developers if (misc_reg == MISCREG_SPSR) 15210037SARM gem5 Developers flat_idx = flattenMiscIndex(misc_reg); 15310037SARM gem5 Developers else 15410037SARM gem5 Developers flat_idx = misc_reg; 15510037SARM gem5 Developers MiscReg val = miscRegs[flat_idx]; 15610037SARM gem5 Developers 15710037SARM gem5 Developers DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 15810037SARM gem5 Developers misc_reg, flat_idx, val); 15910037SARM gem5 Developers return val; 1607351Sgblack@eecs.umich.edu} 16110037SARM gem5 Developers 16210037SARM gem5 Developers 16310037SARM gem5 DevelopersMiscReg 16410037SARM gem5 DevelopersISA::readMiscReg(int misc_reg, ThreadContext *tc) 16510037SARM gem5 Developers{ 16610037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 16710037SARM gem5 Developers CPSR cpsr = miscRegs[misc_reg]; 16810037SARM gem5 Developers Addr pc = tc->readPC(); 16910037SARM gem5 Developers if (pc & (ULL(1) << PcJBitShift)) 17010037SARM gem5 Developers cpsr.j = 1; 17110037SARM gem5 Developers else 17210037SARM gem5 Developers cpsr.j = 0; 17310037SARM gem5 Developers if (pc & (ULL(1) << PcTBitShift)) 17410037SARM gem5 Developers cpsr.t = 1; 17510037SARM gem5 Developers else 17610037SARM gem5 Developers cpsr.t = 0; 17710037SARM gem5 Developers return cpsr; 17810037SARM gem5 Developers } 17910037SARM gem5 Developers if (misc_reg >= MISCREG_CP15_UNIMP_START && 18010037SARM gem5 Developers misc_reg < MISCREG_CP15_END) { 18110037SARM gem5 Developers panic("Unimplemented CP15 register %s read.\n", 18210037SARM gem5 Developers miscRegName[misc_reg]); 18310037SARM gem5 Developers } 18410037SARM gem5 Developers switch (misc_reg) { 18510037SARM gem5 Developers case MISCREG_CLIDR: 18610037SARM gem5 Developers warn("The clidr register always reports 0 caches.\n"); 18710037SARM gem5 Developers break; 18810037SARM gem5 Developers case MISCREG_CCSIDR: 18910037SARM gem5 Developers warn("The ccsidr register isn't implemented and " 19010037SARM gem5 Developers "always reads as 0.\n"); 19110037SARM gem5 Developers break; 19210037SARM gem5 Developers case MISCREG_ID_PFR0: 19310037SARM gem5 Developers warn("Returning thumbEE disabled for now since we don't support CP14" 19410037SARM gem5 Developers "config registers and jumping to ThumbEE vectors\n"); 19510037SARM gem5 Developers return 0x0031; // !ThumbEE | !Jazelle | Thumb | ARM 19610037SARM gem5 Developers case MISCREG_ID_MMFR0: 19710037SARM gem5 Developers return 0x03; //VMSAz7 19810037SARM gem5 Developers case MISCREG_CTR: 19910037SARM gem5 Developers return 0x86468006; // V7, 64 byte cache line, load/exclusive is exact 20010037SARM gem5 Developers case MISCREG_ACTLR: 20110037SARM gem5 Developers warn("Not doing anything for miscreg ACTLR\n"); 20210037SARM gem5 Developers break; 20310037SARM gem5 Developers case MISCREG_PMCR: 20410037SARM gem5 Developers case MISCREG_PMCCNTR: 20510037SARM gem5 Developers case MISCREG_PMSELR: 20610037SARM gem5 Developers warn("Not doing anyhting for read to miscreg %s\n", 20710037SARM gem5 Developers miscRegName[misc_reg]); 20810037SARM gem5 Developers break; 20910037SARM gem5 Developers 21010037SARM gem5 Developers } 21110037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 21210037SARM gem5 Developers} 21310037SARM gem5 Developers 21410037SARM gem5 Developersvoid 21510037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 21610037SARM gem5 Developers{ 21710037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 21810037SARM gem5 Developers 21910037SARM gem5 Developers int flat_idx; 22010037SARM gem5 Developers if (misc_reg == MISCREG_SPSR) 22110037SARM gem5 Developers flat_idx = flattenMiscIndex(misc_reg); 22210037SARM gem5 Developers else 22310037SARM gem5 Developers flat_idx = misc_reg; 22410037SARM gem5 Developers miscRegs[flat_idx] = val; 22510037SARM gem5 Developers 22610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 22710037SARM gem5 Developers flat_idx, val); 22810037SARM gem5 Developers} 22910037SARM gem5 Developers 23010037SARM gem5 Developersvoid 23110037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 23210037SARM gem5 Developers{ 23310037SARM gem5 Developers MiscReg newVal = val; 23410037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 23510037SARM gem5 Developers updateRegMap(val); 23610037SARM gem5 Developers CPSR cpsr = val; 23710037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 23810037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 23910037SARM gem5 Developers Addr npc = tc->readNextPC() & ~PcModeMask; 24010037SARM gem5 Developers if (cpsr.j) 24110037SARM gem5 Developers npc = npc | (ULL(1) << PcJBitShift); 24210037SARM gem5 Developers if (cpsr.t) 24310037SARM gem5 Developers npc = npc | (ULL(1) << PcTBitShift); 24410037SARM gem5 Developers 24510037SARM gem5 Developers tc->setNextPC(npc); 24610037SARM gem5 Developers } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 24710037SARM gem5 Developers misc_reg < MISCREG_CP15_END) { 24810037SARM gem5 Developers panic("Unimplemented CP15 register %s wrote with %#x.\n", 24910037SARM gem5 Developers miscRegName[misc_reg], val); 25010037SARM gem5 Developers } else { 25110037SARM gem5 Developers switch (misc_reg) { 25210037SARM gem5 Developers case MISCREG_ITSTATE: 25310037SARM gem5 Developers { 25410037SARM gem5 Developers ITSTATE itstate = newVal; 25510037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 25610037SARM gem5 Developers cpsr.it1 = itstate.bottom2; 25710037SARM gem5 Developers cpsr.it2 = itstate.top6; 25810037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 25910037SARM gem5 Developers DPRINTF(MiscRegs, 26010037SARM gem5 Developers "Updating ITSTATE -> %#x in CPSR -> %#x.\n", 26110037SARM gem5 Developers (uint8_t)itstate, (uint32_t)cpsr); 26210037SARM gem5 Developers } 26310037SARM gem5 Developers break; 26410037SARM gem5 Developers case MISCREG_CPACR: 26510037SARM gem5 Developers { 26610037SARM gem5 Developers CPACR newCpacr = 0; 26710037SARM gem5 Developers CPACR valCpacr = val; 26810037SARM gem5 Developers newCpacr.cp10 = valCpacr.cp10; 26910037SARM gem5 Developers newCpacr.cp11 = valCpacr.cp11; 27010037SARM gem5 Developers //XXX d32dis isn't implemented. The manual says whether or not 27110037SARM gem5 Developers //it works is implementation defined. 27210037SARM gem5 Developers newCpacr.asedis = valCpacr.asedis; 27310037SARM gem5 Developers newVal = newCpacr; 27410037SARM gem5 Developers } 27510037SARM gem5 Developers break; 27610037SARM gem5 Developers case MISCREG_CSSELR: 27710037SARM gem5 Developers warn("The csselr register isn't implemented.\n"); 27810037SARM gem5 Developers break; 27910037SARM gem5 Developers case MISCREG_FPSCR: 28010037SARM gem5 Developers { 28110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 28210037SARM gem5 Developers FPSCR fpscrMask = 0; 28310037SARM gem5 Developers fpscrMask.ioc = ones; 28410037SARM gem5 Developers fpscrMask.dzc = ones; 28510037SARM gem5 Developers fpscrMask.ofc = ones; 28610037SARM gem5 Developers fpscrMask.ufc = ones; 28710037SARM gem5 Developers fpscrMask.ixc = ones; 28810037SARM gem5 Developers fpscrMask.idc = ones; 28910037SARM gem5 Developers fpscrMask.len = ones; 29010037SARM gem5 Developers fpscrMask.stride = ones; 29110037SARM gem5 Developers fpscrMask.rMode = ones; 29210037SARM gem5 Developers fpscrMask.fz = ones; 29310037SARM gem5 Developers fpscrMask.dn = ones; 29410037SARM gem5 Developers fpscrMask.ahp = ones; 29510037SARM gem5 Developers fpscrMask.qc = ones; 29610037SARM gem5 Developers fpscrMask.v = ones; 29710037SARM gem5 Developers fpscrMask.c = ones; 29810037SARM gem5 Developers fpscrMask.z = ones; 29910037SARM gem5 Developers fpscrMask.n = ones; 30010037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 30110037SARM gem5 Developers (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 30210037SARM gem5 Developers } 30310037SARM gem5 Developers break; 30410037SARM gem5 Developers case MISCREG_FPEXC: 30510037SARM gem5 Developers { 30610037SARM gem5 Developers const uint32_t fpexcMask = 0x60000000; 30710037SARM gem5 Developers newVal = (newVal & fpexcMask) | 30810037SARM gem5 Developers (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 30910037SARM gem5 Developers } 31010037SARM gem5 Developers break; 31110037SARM gem5 Developers case MISCREG_SCTLR: 31210037SARM gem5 Developers { 31310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 31410037SARM gem5 Developers SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 31510037SARM gem5 Developers SCTLR new_sctlr = newVal; 31610037SARM gem5 Developers new_sctlr.nmfi = (bool)sctlr.nmfi; 31710037SARM gem5 Developers miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 31810037SARM gem5 Developers return; 31910037SARM gem5 Developers } 32010037SARM gem5 Developers case MISCREG_TLBTR: 32110037SARM gem5 Developers case MISCREG_MVFR0: 32210037SARM gem5 Developers case MISCREG_MVFR1: 32310037SARM gem5 Developers case MISCREG_MPIDR: 32410037SARM gem5 Developers case MISCREG_FPSID: 32510037SARM gem5 Developers return; 32610037SARM gem5 Developers case MISCREG_TLBIALLIS: 32710037SARM gem5 Developers case MISCREG_TLBIALL: 32810037SARM gem5 Developers warn("Need to flush all TLBs in MP\n"); 32910037SARM gem5 Developers tc->getITBPtr()->flushAll(); 33010037SARM gem5 Developers tc->getDTBPtr()->flushAll(); 33110037SARM gem5 Developers return; 33210037SARM gem5 Developers case MISCREG_ITLBIALL: 33310037SARM gem5 Developers tc->getITBPtr()->flushAll(); 33410037SARM gem5 Developers return; 33510037SARM gem5 Developers case MISCREG_DTLBIALL: 33610037SARM gem5 Developers tc->getDTBPtr()->flushAll(); 33710037SARM gem5 Developers return; 33810037SARM gem5 Developers case MISCREG_TLBIMVAIS: 33910037SARM gem5 Developers case MISCREG_TLBIMVA: 34010037SARM gem5 Developers warn("Need to flush all TLBs in MP\n"); 34110037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 34210037SARM gem5 Developers bits(newVal, 7,0)); 34310037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 34410037SARM gem5 Developers bits(newVal, 7,0)); 34510037SARM gem5 Developers return; 34610037SARM gem5 Developers case MISCREG_TLBIASIDIS: 34710037SARM gem5 Developers case MISCREG_TLBIASID: 34810037SARM gem5 Developers warn("Need to flush all TLBs in MP\n"); 34910037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 35010037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 35110037SARM gem5 Developers return; 35210037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 35310037SARM gem5 Developers case MISCREG_TLBIMVAA: 35410037SARM gem5 Developers warn("Need to flush all TLBs in MP\n"); 35510037SARM gem5 Developers tc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 35610037SARM gem5 Developers tc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 35710037SARM gem5 Developers return; 35810037SARM gem5 Developers case MISCREG_ITLBIMVA: 35910037SARM gem5 Developers tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 36010037SARM gem5 Developers bits(newVal, 7,0)); 36110037SARM gem5 Developers return; 36210037SARM gem5 Developers case MISCREG_DTLBIMVA: 36310037SARM gem5 Developers tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 36410037SARM gem5 Developers bits(newVal, 7,0)); 36510037SARM gem5 Developers return; 36610037SARM gem5 Developers case MISCREG_ITLBIASID: 36710037SARM gem5 Developers tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 36810037SARM gem5 Developers return; 36910037SARM gem5 Developers case MISCREG_DTLBIASID: 37010037SARM gem5 Developers tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 37110037SARM gem5 Developers return; 37210037SARM gem5 Developers case MISCREG_ACTLR: 37310037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 37410037SARM gem5 Developers break; 37510037SARM gem5 Developers case MISCREG_PMCR: 37610037SARM gem5 Developers case MISCREG_PMCCNTR: 37710037SARM gem5 Developers case MISCREG_PMSELR: 37810037SARM gem5 Developers warn("Not doing anything for write to miscreg %s\n", 37910037SARM gem5 Developers miscRegName[misc_reg]); 38010037SARM gem5 Developers break; 38110037SARM gem5 Developers case MISCREG_V2PCWPR: 38210037SARM gem5 Developers case MISCREG_V2PCWPW: 38310037SARM gem5 Developers case MISCREG_V2PCWUR: 38410037SARM gem5 Developers case MISCREG_V2PCWUW: 38510037SARM gem5 Developers case MISCREG_V2POWPR: 38610037SARM gem5 Developers case MISCREG_V2POWPW: 38710037SARM gem5 Developers case MISCREG_V2POWUR: 38810037SARM gem5 Developers case MISCREG_V2POWUW: 38910037SARM gem5 Developers { 39010037SARM gem5 Developers RequestPtr req = new Request; 39110037SARM gem5 Developers unsigned flags; 39210037SARM gem5 Developers BaseTLB::Mode mode; 39310037SARM gem5 Developers Fault fault; 39410037SARM gem5 Developers switch(misc_reg) { 39510037SARM gem5 Developers case MISCREG_V2PCWPR: 39610037SARM gem5 Developers flags = TLB::MustBeOne; 39710037SARM gem5 Developers mode = BaseTLB::Read; 39810037SARM gem5 Developers break; 39910037SARM gem5 Developers case MISCREG_V2PCWPW: 40010037SARM gem5 Developers flags = TLB::MustBeOne; 40110037SARM gem5 Developers mode = BaseTLB::Write; 4027259Sgblack@eecs.umich.edu break; 40310037SARM gem5 Developers case MISCREG_V2PCWUR: 40410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 40510037SARM gem5 Developers mode = BaseTLB::Read; 40610037SARM gem5 Developers break; 40710037SARM gem5 Developers case MISCREG_V2PCWUW: 40810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 40910037SARM gem5 Developers mode = BaseTLB::Write; 41010037SARM gem5 Developers break; 41110037SARM gem5 Developers default: 41210037SARM gem5 Developers panic("Security Extensions not implemented!"); 41310037SARM gem5 Developers } 41410037SARM gem5 Developers req->setVirt(0, val, 1, flags, tc->readPC()); 41510037SARM gem5 Developers fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 41610037SARM gem5 Developers if (fault == NoFault) { 41710037SARM gem5 Developers miscRegs[MISCREG_PAR] = 41810037SARM gem5 Developers (req->getPaddr() & 0xfffff000) | 41910037SARM gem5 Developers (tc->getDTBPtr()->getAttr() ); 42010037SARM gem5 Developers DPRINTF(MiscRegs, 42110037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 42210037SARM gem5 Developers val, miscRegs[MISCREG_PAR]); 42310037SARM gem5 Developers } 42410037SARM gem5 Developers else { 42510037SARM gem5 Developers // Set fault bit and FSR 42610037SARM gem5 Developers FSR fsr = miscRegs[MISCREG_DFSR]; 42710037SARM gem5 Developers miscRegs[MISCREG_PAR] = 42810037SARM gem5 Developers (fsr.ext << 6) | 42910037SARM gem5 Developers (fsr.fsHigh << 5) | 43010037SARM gem5 Developers (fsr.fsLow << 1) | 43110037SARM gem5 Developers 0x1; // F bit 43210037SARM gem5 Developers } 43310037SARM gem5 Developers return; 43410037SARM gem5 Developers } 43510037SARM gem5 Developers } 43610037SARM gem5 Developers } 43710037SARM gem5 Developers setMiscRegNoEffect(misc_reg, newVal); 43810037SARM gem5 Developers} 43910037SARM gem5 Developers 44010037SARM gem5 Developers} 44110037SARM gem5 Developers