isa.cc revision 13881
17405SAli.Saidi@ARM.com/* 210844Sandreas.sandberg@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 448887Sgeoffrey.blake@arm.com#include "arch/arm/tlb.hh" 4510461SAndreas.Sandberg@ARM.com#include "arch/arm/tlbi_op.hh" 468232Snate@binkert.org#include "cpu/base.hh" 478232Snate@binkert.org#include "cpu/checker/cpu.hh" 4810844Sandreas.sandberg@arm.com#include "debug/Arm.hh" 499384SAndreas.Sandberg@arm.com#include "debug/MiscRegs.hh" 507678Sgblack@eecs.umich.edu#include "dev/arm/generic_timer.hh" 518059SAli.Saidi@ARM.com#include "dev/arm/gic_v3.hh" 528284SAli.Saidi@ARM.com#include "dev/arm/gic_v3_cpu_interface.hh" 537405SAli.Saidi@ARM.com#include "params/ArmISA.hh" 547405SAli.Saidi@ARM.com#include "sim/faults.hh" 557405SAli.Saidi@ARM.com#include "sim/stat_control.hh" 567405SAli.Saidi@ARM.com#include "sim/system.hh" 5710037SARM gem5 Developers 5810037SARM gem5 Developersnamespace ArmISA 5910037SARM gem5 Developers{ 6010037SARM gem5 Developers 6110037SARM gem5 DevelopersISA::ISA(Params *p) 6210037SARM gem5 Developers : SimObject(p), 6310037SARM gem5 Developers system(NULL), 6410037SARM gem5 Developers _decoderFlavour(p->decoderFlavour), 6510037SARM gem5 Developers _vecRegRenameMode(Enums::Full), 6610037SARM gem5 Developers pmu(p->pmu), 6710037SARM gem5 Developers haveGICv3CPUInterface(false), 6810037SARM gem5 Developers impdefAsNop(p->impdef_nop) 6910037SARM gem5 Developers{ 7010037SARM gem5 Developers miscRegs[MISCREG_SCTLR_RST] = 0; 7110037SARM gem5 Developers 7210037SARM gem5 Developers // Hook up a dummy device if we haven't been configured with a 7310037SARM gem5 Developers // real PMU. By using a dummy device, we don't need to check that 7410037SARM gem5 Developers // the PMU exist every time we try to access a PMU register. 7510037SARM gem5 Developers if (!pmu) 7610037SARM gem5 Developers pmu = &dummyDevice; 7710037SARM gem5 Developers 7810037SARM gem5 Developers // Give all ISA devices a pointer to this ISA 7910037SARM gem5 Developers pmu->setISA(this); 8010037SARM gem5 Developers 8110037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 8210037SARM gem5 Developers 8310037SARM gem5 Developers // Cache system-level properties 8410037SARM gem5 Developers if (FullSystem && system) { 8510037SARM gem5 Developers highestELIs64 = system->highestELIs64(); 8610037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8710037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8810037SARM gem5 Developers haveCrypto = system->haveCrypto(); 8910037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 9010037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 9110037SARM gem5 Developers physAddrRange = system->physAddrRange(); 9210037SARM gem5 Developers haveSVE = system->haveSVE(); 9310037SARM gem5 Developers sveVL = system->sveVL(); 9410037SARM gem5 Developers } else { 9510037SARM gem5 Developers highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9610037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9710037SARM gem5 Developers haveCrypto = true; 9810037SARM gem5 Developers haveLargeAsid64 = false; 9910037SARM gem5 Developers physAddrRange = 32; // dummy value 10010037SARM gem5 Developers haveSVE = true; 10110037SARM gem5 Developers sveVL = p->sve_vl_se; 10210037SARM gem5 Developers } 10310037SARM gem5 Developers 10410037SARM gem5 Developers // Initial rename mode depends on highestEL 10510037SARM gem5 Developers const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 10610037SARM gem5 Developers highestELIs64 ? Enums::Full : Enums::Elem; 10710037SARM gem5 Developers 10810037SARM gem5 Developers initializeMiscRegMetadata(); 10910037SARM gem5 Developers preUnflattenMiscReg(); 11010037SARM gem5 Developers 11110037SARM gem5 Developers clear(); 11210037SARM gem5 Developers} 11310037SARM gem5 Developers 11410037SARM gem5 Developersstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 11510037SARM gem5 Developers 11610037SARM gem5 Developersconst ArmISAParams * 11710037SARM gem5 DevelopersISA::params() const 11810037SARM gem5 Developers{ 11910037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 12010037SARM gem5 Developers} 12110037SARM gem5 Developers 12210037SARM gem5 Developersvoid 12310037SARM gem5 DevelopersISA::clear() 12410037SARM gem5 Developers{ 12510037SARM gem5 Developers const Params *p(params()); 12610037SARM gem5 Developers 1279384SAndreas.Sandberg@arm.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 12810461SAndreas.Sandberg@ARM.com memset(miscRegs, 0, sizeof(miscRegs)); 12910461SAndreas.Sandberg@ARM.com 13011165SRekai.GonzalezAlberquilla@arm.com initID32(p); 13110461SAndreas.Sandberg@ARM.com 13210461SAndreas.Sandberg@ARM.com // We always initialize AArch64 ID registers even 1339384SAndreas.Sandberg@arm.com // if we are in AArch32. This is done since if we 1349384SAndreas.Sandberg@arm.com // are in SE mode we don't know if our ArmProcess is 1359384SAndreas.Sandberg@arm.com // AArch32 or AArch64 1369384SAndreas.Sandberg@arm.com initID64(p); 13710037SARM gem5 Developers 13810461SAndreas.Sandberg@ARM.com // Start with an event in the mailbox 13910461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 14010461SAndreas.Sandberg@ARM.com 14110461SAndreas.Sandberg@ARM.com // Separate Instruction and Data TLBs 14210461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_TLBTR] = 1; 14310461SAndreas.Sandberg@ARM.com 14410609Sandreas.sandberg@arm.com MVFR0 mvfr0 = 0; 14510609Sandreas.sandberg@arm.com mvfr0.advSimdRegisters = 2; 14610609Sandreas.sandberg@arm.com mvfr0.singlePrecision = 2; 14710037SARM gem5 Developers mvfr0.doublePrecision = 2; 14810037SARM gem5 Developers mvfr0.vfpExceptionTrapping = 0; 14910037SARM gem5 Developers mvfr0.divide = 1; 15010037SARM gem5 Developers mvfr0.squareRoot = 1; 15110037SARM gem5 Developers mvfr0.shortVectors = 1; 15210037SARM gem5 Developers mvfr0.roundingModes = 1; 15310037SARM gem5 Developers miscRegs[MISCREG_MVFR0] = mvfr0; 15410037SARM gem5 Developers 15510037SARM gem5 Developers MVFR1 mvfr1 = 0; 15610037SARM gem5 Developers mvfr1.flushToZero = 1; 15710037SARM gem5 Developers mvfr1.defaultNaN = 1; 15810037SARM gem5 Developers mvfr1.advSimdLoadStore = 1; 15910037SARM gem5 Developers mvfr1.advSimdInteger = 1; 16010037SARM gem5 Developers mvfr1.advSimdSinglePrecision = 1; 16110037SARM gem5 Developers mvfr1.advSimdHalfPrecision = 1; 16210037SARM gem5 Developers mvfr1.vfpHalfPrecision = 1; 16310037SARM gem5 Developers miscRegs[MISCREG_MVFR1] = mvfr1; 16410037SARM gem5 Developers 16510037SARM gem5 Developers // Reset values of PRRR and NMRR are implementation dependent 16610037SARM gem5 Developers 16710037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 16810037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 16910037SARM gem5 Developers (1 << 19) | // 19 17010037SARM gem5 Developers (0 << 18) | // 18 17110037SARM gem5 Developers (0 << 17) | // 17 17210037SARM gem5 Developers (1 << 16) | // 16 17310037SARM gem5 Developers (2 << 14) | // 15:14 1749384SAndreas.Sandberg@arm.com (0 << 12) | // 13:12 1759384SAndreas.Sandberg@arm.com (2 << 10) | // 11:10 1769384SAndreas.Sandberg@arm.com (2 << 8) | // 9:8 1779384SAndreas.Sandberg@arm.com (2 << 6) | // 7:6 1789384SAndreas.Sandberg@arm.com (2 << 4) | // 5:4 1799384SAndreas.Sandberg@arm.com (1 << 2) | // 3:2 1809384SAndreas.Sandberg@arm.com 0; // 1:0 1819384SAndreas.Sandberg@arm.com 1829384SAndreas.Sandberg@arm.com miscRegs[MISCREG_NMRR_NS] = 1837427Sgblack@eecs.umich.edu (1 << 30) | // 31:30 1847427Sgblack@eecs.umich.edu (0 << 26) | // 27:26 1857427Sgblack@eecs.umich.edu (0 << 24) | // 25:24 1869385SAndreas.Sandberg@arm.com (3 << 22) | // 23:22 1879385SAndreas.Sandberg@arm.com (2 << 20) | // 21:20 1887427Sgblack@eecs.umich.edu (0 << 18) | // 19:18 1897427Sgblack@eecs.umich.edu (0 << 16) | // 17:16 19010037SARM gem5 Developers (1 << 14) | // 15:14 19110037SARM gem5 Developers (0 << 12) | // 13:12 19210037SARM gem5 Developers (2 << 10) | // 11:10 19310037SARM gem5 Developers (0 << 8) | // 9:8 19410037SARM gem5 Developers (3 << 6) | // 7:6 19510037SARM gem5 Developers (2 << 4) | // 5:4 19610037SARM gem5 Developers (0 << 2) | // 3:2 19710037SARM gem5 Developers 0; // 1:0 19810037SARM gem5 Developers 19910037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 20010037SARM gem5 Developers // Initialize AArch64 state 20110037SARM gem5 Developers clear64(p); 20210037SARM gem5 Developers return; 20310037SARM gem5 Developers } 2047427Sgblack@eecs.umich.edu 2057427Sgblack@eecs.umich.edu // Initialize AArch32 state... 2067427Sgblack@eecs.umich.edu clear32(p, sctlr_rst); 2077427Sgblack@eecs.umich.edu} 2087427Sgblack@eecs.umich.edu 2097427Sgblack@eecs.umich.eduvoid 21010037SARM gem5 DevelopersISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 21110037SARM gem5 Developers{ 21210037SARM gem5 Developers CPSR cpsr = 0; 21310037SARM gem5 Developers cpsr.mode = MODE_USER; 2147427Sgblack@eecs.umich.edu 2157427Sgblack@eecs.umich.edu if (FullSystem) { 2167427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVBAR] = system->resetAddr(); 21710037SARM gem5 Developers } 21810204SAli.Saidi@ARM.com 21910204SAli.Saidi@ARM.com miscRegs[MISCREG_CPSR] = cpsr; 22010037SARM gem5 Developers updateRegMap(cpsr); 2217427Sgblack@eecs.umich.edu 22210037SARM gem5 Developers SCTLR sctlr = 0; 2237427Sgblack@eecs.umich.edu sctlr.te = (bool) sctlr_rst.te; 22410037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 2257427Sgblack@eecs.umich.edu sctlr.v = (bool) sctlr_rst.v; 2267427Sgblack@eecs.umich.edu sctlr.u = 1; 22710037SARM gem5 Developers sctlr.xp = 1; 2287427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 2297427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 2307427Sgblack@eecs.umich.edu sctlr.rao4 = 0xf; // SCTLR[6:3] 2317427Sgblack@eecs.umich.edu sctlr.uci = 1; 2327427Sgblack@eecs.umich.edu sctlr.dze = 1; 2337427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_NS] = sctlr; 2347427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 2357427Sgblack@eecs.umich.edu miscRegs[MISCREG_HCPTR] = 0; 2367427Sgblack@eecs.umich.edu 2377427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPACR] = 0; 2387427Sgblack@eecs.umich.edu 2397427Sgblack@eecs.umich.edu miscRegs[MISCREG_FPSID] = p->fpsid; 2407427Sgblack@eecs.umich.edu 2417427Sgblack@eecs.umich.edu if (haveLPAE) { 2427427Sgblack@eecs.umich.edu TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 2437427Sgblack@eecs.umich.edu ttbcr.eae = 0; 2447427Sgblack@eecs.umich.edu miscRegs[MISCREG_TTBCR_NS] = ttbcr; 2457427Sgblack@eecs.umich.edu // Enforce consistency with system-level settings 2467427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2477427Sgblack@eecs.umich.edu } 2487427Sgblack@eecs.umich.edu 2497427Sgblack@eecs.umich.edu if (haveSecurity) { 2507427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_S] = sctlr; 2517436Sdam.sunwoo@arm.com miscRegs[MISCREG_SCR] = 0; 2527436Sdam.sunwoo@arm.com miscRegs[MISCREG_VBAR_S] = 0; 25310037SARM gem5 Developers } else { 25410037SARM gem5 Developers // we're always non-secure 2557436Sdam.sunwoo@arm.com miscRegs[MISCREG_SCR] = 1; 2567436Sdam.sunwoo@arm.com } 2577436Sdam.sunwoo@arm.com 2587436Sdam.sunwoo@arm.com //XXX We need to initialize the rest of the state. 2597436Sdam.sunwoo@arm.com} 2607436Sdam.sunwoo@arm.com 2617436Sdam.sunwoo@arm.comvoid 2627436Sdam.sunwoo@arm.comISA::clear64(const ArmISAParams *p) 2637436Sdam.sunwoo@arm.com{ 2647436Sdam.sunwoo@arm.com CPSR cpsr = 0; 2657436Sdam.sunwoo@arm.com Addr rvbar = system->resetAddr(); 2667436Sdam.sunwoo@arm.com switch (system->highestEL()) { 26710037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 2687436Sdam.sunwoo@arm.com // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 2697436Sdam.sunwoo@arm.com // value 2707436Sdam.sunwoo@arm.com case EL3: 2717436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL3H; 2727436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL3] = rvbar; 2737436Sdam.sunwoo@arm.com break; 2747436Sdam.sunwoo@arm.com case EL2: 2757436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL2H; 2767436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL2] = rvbar; 2777436Sdam.sunwoo@arm.com break; 2787436Sdam.sunwoo@arm.com case EL1: 2797436Sdam.sunwoo@arm.com cpsr.mode = MODE_EL1H; 2807436Sdam.sunwoo@arm.com miscRegs[MISCREG_RVBAR_EL1] = rvbar; 2817436Sdam.sunwoo@arm.com break; 2827436Sdam.sunwoo@arm.com default: 2837436Sdam.sunwoo@arm.com panic("Invalid highest implemented exception level"); 2847644Sali.saidi@arm.com break; 2858147SAli.Saidi@ARM.com } 2869385SAndreas.Sandberg@arm.com 2879385SAndreas.Sandberg@arm.com // Initialize rest of CPSR 2889385SAndreas.Sandberg@arm.com cpsr.daif = 0xf; // Mask all interrupts 2899385SAndreas.Sandberg@arm.com cpsr.ss = 0; 2909385SAndreas.Sandberg@arm.com cpsr.il = 0; 2919385SAndreas.Sandberg@arm.com miscRegs[MISCREG_CPSR] = cpsr; 2929385SAndreas.Sandberg@arm.com updateRegMap(cpsr); 2939385SAndreas.Sandberg@arm.com 2949385SAndreas.Sandberg@arm.com // Initialize other control registers 2959385SAndreas.Sandberg@arm.com miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 2969385SAndreas.Sandberg@arm.com if (haveSecurity) { 2979385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 2989385SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 2999385SAndreas.Sandberg@arm.com } else if (haveVirtualization) { 3009385SAndreas.Sandberg@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 3019385SAndreas.Sandberg@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 3029385SAndreas.Sandberg@arm.com } else { 3039385SAndreas.Sandberg@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 30410037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 30510037SARM gem5 Developers // Always non-secure 30610037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 30710037SARM gem5 Developers } 30810037SARM gem5 Developers} 30910037SARM gem5 Developers 31010037SARM gem5 Developersvoid 31110037SARM gem5 DevelopersISA::initID32(const ArmISAParams *p) 31210037SARM gem5 Developers{ 31310037SARM gem5 Developers // Initialize configurable default values 31410037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 31510037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 31610037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 31710037SARM gem5 Developers 31810037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 31910037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 3208147SAli.Saidi@ARM.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 3217427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 3227427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 3237427Sgblack@eecs.umich.edu miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 32410037SARM gem5 Developers 32510037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 32610037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 32710037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 32810037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 32910037SARM gem5 Developers 33010037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5] = insertBits( 33110037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR5], 19, 4, 33210037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 33310037SARM gem5 Developers} 33410037SARM gem5 Developers 33510037SARM gem5 Developersvoid 33610037SARM gem5 DevelopersISA::initID64(const ArmISAParams *p) 33710037SARM gem5 Developers{ 33810037SARM gem5 Developers // Initialize configurable id registers 33910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 34010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 34110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR0_EL1] = 34210037SARM gem5 Developers (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 34310037SARM gem5 Developers (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 34410037SARM gem5 Developers 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 34710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 34810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 34910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 35010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 35110037SARM gem5 Developers 35210037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0_EL1] = 35310037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 35410037SARM gem5 Developers 35510037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 35610037SARM gem5 Developers 35710037SARM gem5 Developers // SVE 35810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 35910037SARM gem5 Developers if (haveSecurity) { 36010037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 36110037SARM gem5 Developers } else if (haveVirtualization) { 36210037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 36310037SARM gem5 Developers } else { 36410037SARM gem5 Developers miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 36510037SARM gem5 Developers } 36610037SARM gem5 Developers 36710037SARM gem5 Developers // Enforce consistency with system-level settings... 36810037SARM gem5 Developers 36910037SARM gem5 Developers // EL3 37010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 37210037SARM gem5 Developers haveSecurity ? 0x2 : 0x0); 37310037SARM gem5 Developers // EL2 37410461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 37610461SAndreas.Sandberg@ARM.com haveVirtualization ? 0x2 : 0x0); 37710461SAndreas.Sandberg@ARM.com // SVE 37810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 38010037SARM gem5 Developers haveSVE ? 0x1 : 0x0); 38110037SARM gem5 Developers // Large ASID support 38210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 38410037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 38510037SARM gem5 Developers // Physical address size 38610461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38710461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 38810461SAndreas.Sandberg@ARM.com encodePhysAddrRange64(physAddrRange)); 38910461SAndreas.Sandberg@ARM.com // Crypto 39010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 39110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 39210037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 39310037SARM gem5 Developers} 39410037SARM gem5 Developers 39510037SARM gem5 Developersvoid 39610037SARM gem5 DevelopersISA::startup(ThreadContext *tc) 39710037SARM gem5 Developers{ 39810037SARM gem5 Developers pmu->setThreadContext(tc); 39910037SARM gem5 Developers 40010037SARM gem5 Developers if (system) { 40110037SARM gem5 Developers Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 40210037SARM gem5 Developers if (gicv3) { 40310037SARM gem5 Developers haveGICv3CPUInterface = true; 40410037SARM gem5 Developers gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 40510037SARM gem5 Developers gicv3CpuInterface->setISA(this); 40610037SARM gem5 Developers gicv3CpuInterface->setThreadContext(tc); 40710037SARM gem5 Developers } 40810037SARM gem5 Developers } 40910037SARM gem5 Developers} 41010037SARM gem5 Developers 41110037SARM gem5 Developers 41210037SARM gem5 DevelopersRegVal 4137405SAli.Saidi@ARM.comISA::readMiscRegNoEffect(int misc_reg) const 41410035Sandreas.hansson@arm.com{ 4157405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4167405SAli.Saidi@ARM.com 4177614Sminkyu.jeong@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 41810037SARM gem5 Developers const auto &map = getMiscIndices(misc_reg); 41910037SARM gem5 Developers int lower = map.first, upper = map.second; 42010037SARM gem5 Developers // NB!: apply architectural masks according to desired register, 4217614Sminkyu.jeong@arm.com // despite possibly getting value from different (mapped) register. 42210037SARM gem5 Developers auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 42310037SARM gem5 Developers |(miscRegs[upper] << 32)); 42410037SARM gem5 Developers if (val & reg.res0()) { 42510037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 42610037SARM gem5 Developers miscRegName[misc_reg], val & reg.res0()); 42710037SARM gem5 Developers } 42810037SARM gem5 Developers if ((val & reg.res1()) != reg.res1()) { 42910037SARM gem5 Developers DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 43010037SARM gem5 Developers miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 43110037SARM gem5 Developers } 43210037SARM gem5 Developers return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 43310037SARM gem5 Developers} 43410037SARM gem5 Developers 43510037SARM gem5 Developers 4367614Sminkyu.jeong@arm.comRegVal 4377405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 4387405SAli.Saidi@ARM.com{ 4397405SAli.Saidi@ARM.com CPSR cpsr = 0; 4407405SAli.Saidi@ARM.com PCState pc = 0; 4417405SAli.Saidi@ARM.com SCR scr = 0; 4427405SAli.Saidi@ARM.com 44310037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 44410037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 44510037SARM gem5 Developers pc = tc->pcState(); 4469050Schander.sudanthi@arm.com cpsr.j = pc.jazelle() ? 1 : 0; 4477405SAli.Saidi@ARM.com cpsr.t = pc.thumb() ? 1 : 0; 44810037SARM gem5 Developers return cpsr; 44910037SARM gem5 Developers } 4507720Sgblack@eecs.umich.edu 4517720Sgblack@eecs.umich.edu#ifndef NDEBUG 4527405SAli.Saidi@ARM.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 4537405SAli.Saidi@ARM.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 4547757SAli.Saidi@ARM.com warn("Unimplemented system register %s read.\n", 45510037SARM gem5 Developers miscRegName[misc_reg]); 45610037SARM gem5 Developers else 45710037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 45810037SARM gem5 Developers miscRegName[misc_reg]); 45910037SARM gem5 Developers } 46010037SARM gem5 Developers#endif 46110037SARM gem5 Developers 46210037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 46310037SARM gem5 Developers case MISCREG_HCR: 46410037SARM gem5 Developers { 46510037SARM gem5 Developers if (!haveVirtualization) 46610037SARM gem5 Developers return 0; 46710037SARM gem5 Developers else 46810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 46910037SARM gem5 Developers } 47010037SARM gem5 Developers case MISCREG_CPACR: 47110037SARM gem5 Developers { 47210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 47310037SARM gem5 Developers CPACR cpacrMask = 0; 47410037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 47510037SARM gem5 Developers // be readable? (straight copy from the write code) 47610037SARM gem5 Developers cpacrMask.cp10 = ones; 47710037SARM gem5 Developers cpacrMask.cp11 = ones; 47810037SARM gem5 Developers cpacrMask.asedis = ones; 47910037SARM gem5 Developers 48010037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 48110037SARM gem5 Developers if (haveSecurity) { 48210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 48310037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 48410037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 48510037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 48610037SARM gem5 Developers // NB: Skipping the full loop, here 48710037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 48810037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 48910037SARM gem5 Developers } 49010037SARM gem5 Developers } 49110037SARM gem5 Developers RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 49210037SARM gem5 Developers val &= cpacrMask; 49310037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49410037SARM gem5 Developers miscRegName[misc_reg], val); 49510037SARM gem5 Developers return val; 49610037SARM gem5 Developers } 49710037SARM gem5 Developers case MISCREG_MPIDR: 49810037SARM gem5 Developers case MISCREG_MPIDR_EL1: 49910037SARM gem5 Developers return readMPIDR(system, tc); 50010037SARM gem5 Developers case MISCREG_VMPIDR: 5018284SAli.Saidi@ARM.com case MISCREG_VMPIDR_EL2: 50210037SARM gem5 Developers // top bit defined as RES1 50310037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 50410037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 50510037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 5069050Schander.sudanthi@arm.com case MISCREG_MIDR: 50710037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50810037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 50910037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 51010037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 51110037SARM gem5 Developers } else { 51210037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 51310037SARM gem5 Developers } 51410037SARM gem5 Developers break; 51510037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 51610037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 51710037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 51810037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 51910037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 52010037SARM gem5 Developers return 0; 52110037SARM gem5 Developers 52210037SARM gem5 Developers case MISCREG_CLIDR: 52310037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 52410037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 5259050Schander.sudanthi@arm.com "ARM implementations.\n"); 5268284SAli.Saidi@ARM.com return 0x00200000; 52710037SARM gem5 Developers case MISCREG_CCSIDR: 52810037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 52910037SARM gem5 Developers "always reads as 0.\n"); 53010037SARM gem5 Developers break; 53110037SARM gem5 Developers case MISCREG_CTR: // AArch32, ARMv7, top bit set 53210037SARM gem5 Developers case MISCREG_CTR_EL0: // AArch64 53310037SARM gem5 Developers { 5347405SAli.Saidi@ARM.com //all caches have the same line size in gem5 5357731SAli.Saidi@ARM.com //4 byte words in ARM 5368468Swade.walker@arm.com unsigned lineSizeWords = 5378468Swade.walker@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5388468Swade.walker@arm.com unsigned log2LineSizeWords = 0; 5397405SAli.Saidi@ARM.com 5407731SAli.Saidi@ARM.com while (lineSizeWords >>= 1) { 5417405SAli.Saidi@ARM.com ++log2LineSizeWords; 5427405SAli.Saidi@ARM.com } 5437583SAli.Saidi@arm.com 5449130Satgutier@umich.edu CTR ctr = 0; 5459130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5469130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5479130Satgutier@umich.edu //b11 - gem5 uses pipt 5489814Sandreas.hansson@arm.com ctr.l1IndexPolicy = 0x3; 5499130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5509130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5519130Satgutier@umich.edu //log2 of max reservation size (words) 5529130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5539130Satgutier@umich.edu //log2 of max writeback size (words) 5549130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5559130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5569130Satgutier@umich.edu ctr.format = 0x4; 5579130Satgutier@umich.edu 5589130Satgutier@umich.edu return ctr; 5599130Satgutier@umich.edu } 5609130Satgutier@umich.edu case MISCREG_ACTLR: 5619130Satgutier@umich.edu warn("Not doing anything for miscreg ACTLR\n"); 5629130Satgutier@umich.edu break; 5639130Satgutier@umich.edu 5649130Satgutier@umich.edu case MISCREG_PMXEVTYPER_PMCCFILTR: 5659130Satgutier@umich.edu case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 5669130Satgutier@umich.edu case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 5679130Satgutier@umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 5689130Satgutier@umich.edu return pmu->readMiscReg(misc_reg); 5699130Satgutier@umich.edu 5709130Satgutier@umich.edu case MISCREG_CPSR_Q: 5717583SAli.Saidi@arm.com panic("shouldn't be reading this register seperately\n"); 5727583SAli.Saidi@arm.com case MISCREG_FPSCR_QC: 5737583SAli.Saidi@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 57410461SAndreas.Sandberg@ARM.com case MISCREG_FPSCR_EXC: 57510461SAndreas.Sandberg@ARM.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 57610461SAndreas.Sandberg@ARM.com case MISCREG_FPSR: 57710461SAndreas.Sandberg@ARM.com { 57810461SAndreas.Sandberg@ARM.com const uint32_t ones = (uint32_t)(-1); 57910461SAndreas.Sandberg@ARM.com FPSCR fpscrMask = 0; 58010461SAndreas.Sandberg@ARM.com fpscrMask.ioc = ones; 5818302SAli.Saidi@ARM.com fpscrMask.dzc = ones; 5828302SAli.Saidi@ARM.com fpscrMask.ofc = ones; 5837783SGiacomo.Gabrielli@arm.com fpscrMask.ufc = ones; 5847783SGiacomo.Gabrielli@arm.com fpscrMask.ixc = ones; 5857783SGiacomo.Gabrielli@arm.com fpscrMask.idc = ones; 5867783SGiacomo.Gabrielli@arm.com fpscrMask.qc = ones; 58710037SARM gem5 Developers fpscrMask.v = ones; 58810037SARM gem5 Developers fpscrMask.c = ones; 58910037SARM gem5 Developers fpscrMask.z = ones; 59010037SARM gem5 Developers fpscrMask.n = ones; 59110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 59210037SARM gem5 Developers } 59310037SARM gem5 Developers case MISCREG_FPCR: 59410037SARM gem5 Developers { 59510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 59610037SARM gem5 Developers FPSCR fpscrMask = 0; 59710037SARM gem5 Developers fpscrMask.len = ones; 59810037SARM gem5 Developers fpscrMask.fz16 = ones; 59910037SARM gem5 Developers fpscrMask.stride = ones; 60010037SARM gem5 Developers fpscrMask.rMode = ones; 60110037SARM gem5 Developers fpscrMask.fz = ones; 60210037SARM gem5 Developers fpscrMask.dn = ones; 60310037SARM gem5 Developers fpscrMask.ahp = ones; 60410037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60510037SARM gem5 Developers } 60610037SARM gem5 Developers case MISCREG_NZCV: 60710037SARM gem5 Developers { 60810037SARM gem5 Developers CPSR cpsr = 0; 60910037SARM gem5 Developers cpsr.nz = tc->readCCReg(CCREG_NZ); 61010037SARM gem5 Developers cpsr.c = tc->readCCReg(CCREG_C); 61110037SARM gem5 Developers cpsr.v = tc->readCCReg(CCREG_V); 61210037SARM gem5 Developers return cpsr; 61310037SARM gem5 Developers } 61410037SARM gem5 Developers case MISCREG_DAIF: 61510037SARM gem5 Developers { 61610037SARM gem5 Developers CPSR cpsr = 0; 61710037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 61810037SARM gem5 Developers return cpsr; 61910037SARM gem5 Developers } 62010037SARM gem5 Developers case MISCREG_SP_EL0: 62110037SARM gem5 Developers { 62210037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 62310037SARM gem5 Developers } 62410037SARM gem5 Developers case MISCREG_SP_EL1: 62510338SCurtis.Dunham@arm.com { 62610338SCurtis.Dunham@arm.com return tc->readIntReg(INTREG_SP1); 62710338SCurtis.Dunham@arm.com } 62810037SARM gem5 Developers case MISCREG_SP_EL2: 62910037SARM gem5 Developers { 63010037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 63110037SARM gem5 Developers } 63210037SARM gem5 Developers case MISCREG_SPSEL: 63310037SARM gem5 Developers { 63410037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 63510037SARM gem5 Developers } 63610037SARM gem5 Developers case MISCREG_CURRENTEL: 63710037SARM gem5 Developers { 63810037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 63910037SARM gem5 Developers } 64010037SARM gem5 Developers case MISCREG_L2CTLR: 64110037SARM gem5 Developers { 64210037SARM gem5 Developers // mostly unimplemented, just set NumCPUs field from sim and return 64310037SARM gem5 Developers L2CTLR l2ctlr = 0; 64410037SARM gem5 Developers // b00:1CPU to b11:4CPUs 64510037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 64610037SARM gem5 Developers return l2ctlr; 64710037SARM gem5 Developers } 64810037SARM gem5 Developers case MISCREG_DBGDIDR: 64910037SARM gem5 Developers /* For now just implement the version number. 65010037SARM gem5 Developers * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 65110037SARM gem5 Developers */ 65210037SARM gem5 Developers return 0x5 << 16; 65310037SARM gem5 Developers case MISCREG_DBGDSCRint: 65410037SARM gem5 Developers return 0; 65510037SARM gem5 Developers case MISCREG_ISR: 6568549Sdaniel.johnson@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 6578868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_HCR), 6588868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_CPSR), 6598868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_SCR)); 6608868SMatt.Horsnell@arm.com case MISCREG_ISR_EL1: 6618868SMatt.Horsnell@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 6628868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_HCR_EL2), 6638868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_CPSR), 6648868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_SCR_EL3)); 6658868SMatt.Horsnell@arm.com case MISCREG_DCZID_EL0: 66610461SAndreas.Sandberg@ARM.com return 0x04; // DC ZVA clear 64-byte chunks 6678868SMatt.Horsnell@arm.com case MISCREG_HCPTR: 66810461SAndreas.Sandberg@ARM.com { 66910037SARM gem5 Developers RegVal val = readMiscRegNoEffect(misc_reg); 6708868SMatt.Horsnell@arm.com // The trap bit associated with CP14 is defined as RAZ 67110037SARM gem5 Developers val &= ~(1 << 14); 67211150Smitch.hayenga@arm.com // If a CP bit in NSACR is 0 then the corresponding bit in 67310037SARM gem5 Developers // HCPTR is RAO/WI 67410037SARM gem5 Developers bool secure_lookup = haveSecurity && 67510037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 67610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 67711150Smitch.hayenga@arm.com if (!secure_lookup) { 67810037SARM gem5 Developers RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 67910037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 68010037SARM gem5 Developers } 68110037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 68210037SARM gem5 Developers val |= 0x33FF; 68310037SARM gem5 Developers return (val); 68410037SARM gem5 Developers } 68510037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 68610037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 68710037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 68810037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 68910037SARM gem5 Developers 69010037SARM gem5 Developers case MISCREG_ID_PFR0: 69110037SARM gem5 Developers // !ThumbEE | !Jazelle | Thumb | ARM 69210037SARM gem5 Developers return 0x00000031; 69310037SARM gem5 Developers case MISCREG_ID_PFR1: 69410037SARM gem5 Developers { // Timer | Virti | !M Profile | TrustZone | ARMv4 69510037SARM gem5 Developers bool haveTimer = (system->getGenericTimer() != NULL); 69610037SARM gem5 Developers return 0x00000001 69710037SARM gem5 Developers | (haveSecurity ? 0x00000010 : 0x0) 69810037SARM gem5 Developers | (haveVirtualization ? 0x00001000 : 0x0) 69910037SARM gem5 Developers | (haveTimer ? 0x00010000 : 0x0); 70010037SARM gem5 Developers } 70110037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 70210037SARM gem5 Developers return 0x0000000000000002 | // AArch{64,32} supported at EL0 70310037SARM gem5 Developers 0x0000000000000020 | // EL1 70410037SARM gem5 Developers (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 70510037SARM gem5 Developers (haveSecurity ? 0x0000000000002000 : 0) | // EL3 70610037SARM gem5 Developers (haveSVE ? 0x0000000100000000 : 0) | // SVE 70710037SARM gem5 Developers (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 70810037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 70910037SARM gem5 Developers return 0; // bits [63:0] RES0 (reserved for future use) 71010037SARM gem5 Developers 71110037SARM gem5 Developers // Generic Timer registers 71210037SARM gem5 Developers case MISCREG_CNTHV_CTL_EL2: 71310037SARM gem5 Developers case MISCREG_CNTHV_CVAL_EL2: 71410037SARM gem5 Developers case MISCREG_CNTHV_TVAL_EL2: 71510037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 71610037SARM gem5 Developers case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 71710037SARM gem5 Developers case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 71810037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 71910037SARM gem5 Developers return getGenericTimer(tc).readMiscReg(misc_reg); 72010037SARM gem5 Developers 72110037SARM gem5 Developers case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 72210037SARM gem5 Developers case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 72310037SARM gem5 Developers return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 72410037SARM gem5 Developers 72510037SARM gem5 Developers default: 72610037SARM gem5 Developers break; 72710037SARM gem5 Developers 72810037SARM gem5 Developers } 72910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 73010037SARM gem5 Developers} 73110037SARM gem5 Developers 73210037SARM gem5 Developersvoid 73310037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, RegVal val) 73410844Sandreas.sandberg@arm.com{ 73510037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 73610844Sandreas.sandberg@arm.com 73710844Sandreas.sandberg@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 73810844Sandreas.sandberg@arm.com const auto &map = getMiscIndices(misc_reg); 73910844Sandreas.sandberg@arm.com int lower = map.first, upper = map.second; 74010844Sandreas.sandberg@arm.com 74110844Sandreas.sandberg@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 74210188Sgeoffrey.blake@arm.com if (upper > 0) { 74310037SARM gem5 Developers miscRegs[lower] = bits(v, 31, 0); 74410037SARM gem5 Developers miscRegs[upper] = bits(v, 63, 32); 7457405SAli.Saidi@ARM.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 7467405SAli.Saidi@ARM.com misc_reg, lower, upper, v); 7477405SAli.Saidi@ARM.com } else { 7487405SAli.Saidi@ARM.com miscRegs[lower] = v; 7497405SAli.Saidi@ARM.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 7507405SAli.Saidi@ARM.com misc_reg, lower, v); 7517405SAli.Saidi@ARM.com } 7527405SAli.Saidi@ARM.com} 7537614Sminkyu.jeong@arm.com 75410037SARM gem5 Developersvoid 75510037SARM gem5 DevelopersISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 7567614Sminkyu.jeong@arm.com{ 75710037SARM gem5 Developers 75810037SARM gem5 Developers RegVal newVal = val; 75910037SARM gem5 Developers bool secure_lookup; 76010037SARM gem5 Developers SCR scr; 76110037SARM gem5 Developers 76210037SARM gem5 Developers if (misc_reg == MISCREG_CPSR) { 76310037SARM gem5 Developers updateRegMap(val); 76410037SARM gem5 Developers 76510037SARM gem5 Developers 76610037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 76710037SARM gem5 Developers int old_mode = old_cpsr.mode; 76810037SARM gem5 Developers CPSR cpsr = val; 76910037SARM gem5 Developers if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 77010037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 77110037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 77210037SARM gem5 Developers } 77310037SARM gem5 Developers 77410037SARM gem5 Developers DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 77510037SARM gem5 Developers miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7767405SAli.Saidi@ARM.com PCState pc = tc->pcState(); 7777405SAli.Saidi@ARM.com pc.nextThumb(cpsr.t); 7787405SAli.Saidi@ARM.com pc.nextJazelle(cpsr.j); 7797405SAli.Saidi@ARM.com pc.illegalExec(cpsr.il == 1); 7807405SAli.Saidi@ARM.com 7817749SAli.Saidi@ARM.com tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 7827405SAli.Saidi@ARM.com 7838284SAli.Saidi@ARM.com // Follow slightly different semantics if a CheckerCPU object 78410037SARM gem5 Developers // is connected 78510037SARM gem5 Developers CheckerCPU *checker = tc->getCheckerCpuPtr(); 7868284SAli.Saidi@ARM.com if (checker) { 7878284SAli.Saidi@ARM.com tc->pcStateNoRecord(pc); 78810037SARM gem5 Developers } else { 78910037SARM gem5 Developers tc->pcState(pc); 79010037SARM gem5 Developers } 7918284SAli.Saidi@ARM.com } else { 7927405SAli.Saidi@ARM.com#ifndef NDEBUG 7937405SAli.Saidi@ARM.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 7947749SAli.Saidi@ARM.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 7957749SAli.Saidi@ARM.com warn("Unimplemented system register %s write with %#x.\n", 7967749SAli.Saidi@ARM.com miscRegName[misc_reg], val); 7977749SAli.Saidi@ARM.com else 7987405SAli.Saidi@ARM.com panic("Unimplemented system register %s write with %#x.\n", 7997749SAli.Saidi@ARM.com miscRegName[misc_reg], val); 8007749SAli.Saidi@ARM.com } 8017749SAli.Saidi@ARM.com#endif 8027749SAli.Saidi@ARM.com switch (unflattenMiscReg(misc_reg)) { 8037749SAli.Saidi@ARM.com case MISCREG_CPACR: 8047614Sminkyu.jeong@arm.com { 8057614Sminkyu.jeong@arm.com 8067720Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8077720Sgblack@eecs.umich.edu CPACR cpacrMask = 0; 8087720Sgblack@eecs.umich.edu // Only cp10, cp11, and ase are implemented, nothing else should 8098887Sgeoffrey.blake@arm.com // be writable 8108887Sgeoffrey.blake@arm.com cpacrMask.cp10 = ones; 8118887Sgeoffrey.blake@arm.com cpacrMask.cp11 = ones; 8128887Sgeoffrey.blake@arm.com cpacrMask.asedis = ones; 8138887Sgeoffrey.blake@arm.com 8148887Sgeoffrey.blake@arm.com // Security Extensions may limit the writability of CPACR 8158887Sgeoffrey.blake@arm.com if (haveSecurity) { 8168887Sgeoffrey.blake@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 8178887Sgeoffrey.blake@arm.com CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 8187408Sgblack@eecs.umich.edu if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 81910037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 82010037SARM gem5 Developers // NB: Skipping the full loop, here 82110037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 82210037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 82310037SARM gem5 Developers } 82410037SARM gem5 Developers } 82510037SARM gem5 Developers 82610037SARM gem5 Developers RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 82710037SARM gem5 Developers newVal &= cpacrMask; 82810037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 82910037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8307408Sgblack@eecs.umich.edu miscRegName[misc_reg], newVal); 8317408Sgblack@eecs.umich.edu } 8328206SWilliam.Wang@arm.com break; 8338206SWilliam.Wang@arm.com case MISCREG_CPACR_EL1: 8348206SWilliam.Wang@arm.com { 8358206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8368206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 8378206SWilliam.Wang@arm.com cpacrMask.tta = ones; 8388206SWilliam.Wang@arm.com cpacrMask.fpen = ones; 8398206SWilliam.Wang@arm.com if (haveSVE) { 84010037SARM gem5 Developers cpacrMask.zen = ones; 84110037SARM gem5 Developers } 84210037SARM gem5 Developers newVal &= cpacrMask; 84310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 84410037SARM gem5 Developers miscRegName[misc_reg], newVal); 84510037SARM gem5 Developers } 84610037SARM gem5 Developers break; 84710037SARM gem5 Developers case MISCREG_CPTR_EL2: 84810037SARM gem5 Developers { 84910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 85010037SARM gem5 Developers CPTR cptrMask = 0; 85110037SARM gem5 Developers cptrMask.tcpac = ones; 85210037SARM gem5 Developers cptrMask.tta = ones; 85310037SARM gem5 Developers cptrMask.tfp = ones; 8548206SWilliam.Wang@arm.com if (haveSVE) { 85510037SARM gem5 Developers cptrMask.tz = ones; 85610037SARM gem5 Developers } 85710037SARM gem5 Developers newVal &= cptrMask; 85810037SARM gem5 Developers cptrMask = 0; 85910037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 86010037SARM gem5 Developers cptrMask.res1_7_0_el2 = ones; 86110037SARM gem5 Developers if (!haveSVE) { 86210037SARM gem5 Developers cptrMask.res1_8_el2 = ones; 86310037SARM gem5 Developers } 86410037SARM gem5 Developers cptrMask.res1_9_el2 = ones; 86510037SARM gem5 Developers newVal |= cptrMask; 86610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 86710037SARM gem5 Developers miscRegName[misc_reg], newVal); 86810037SARM gem5 Developers } 86910037SARM gem5 Developers break; 87010037SARM gem5 Developers case MISCREG_CPTR_EL3: 87110037SARM gem5 Developers { 87210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87310037SARM gem5 Developers CPTR cptrMask = 0; 87410037SARM gem5 Developers cptrMask.tcpac = ones; 87510037SARM gem5 Developers cptrMask.tta = ones; 87610037SARM gem5 Developers cptrMask.tfp = ones; 87710037SARM gem5 Developers if (haveSVE) { 87810037SARM gem5 Developers cptrMask.ez = ones; 87910037SARM gem5 Developers } 88010037SARM gem5 Developers newVal &= cptrMask; 88110037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 88210037SARM gem5 Developers miscRegName[misc_reg], newVal); 88310037SARM gem5 Developers } 88410037SARM gem5 Developers break; 88510037SARM gem5 Developers case MISCREG_CSSELR: 88610037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 88710037SARM gem5 Developers return; 88810037SARM gem5 Developers 88910037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 89010037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 89110037SARM gem5 Developers return; 89210037SARM gem5 Developers 89310037SARM gem5 Developers case MISCREG_FPSCR: 89410037SARM gem5 Developers { 8958206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8968206SWilliam.Wang@arm.com FPSCR fpscrMask = 0; 8977408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8987408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8997408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9007731SAli.Saidi@ARM.com fpscrMask.ufc = ones; 9018206SWilliam.Wang@arm.com fpscrMask.ixc = ones; 90210037SARM gem5 Developers fpscrMask.idc = ones; 90310037SARM gem5 Developers fpscrMask.ioe = ones; 90410037SARM gem5 Developers fpscrMask.dze = ones; 90510037SARM gem5 Developers fpscrMask.ofe = ones; 90610037SARM gem5 Developers fpscrMask.ufe = ones; 9077408Sgblack@eecs.umich.edu fpscrMask.ixe = ones; 9087408Sgblack@eecs.umich.edu fpscrMask.ide = ones; 9097408Sgblack@eecs.umich.edu fpscrMask.len = ones; 9107408Sgblack@eecs.umich.edu fpscrMask.fz16 = ones; 9117408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9127408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9137408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9147408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9157408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9167408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 91710037SARM gem5 Developers fpscrMask.v = ones; 91810037SARM gem5 Developers fpscrMask.c = ones; 91910037SARM gem5 Developers fpscrMask.z = ones; 92010037SARM gem5 Developers fpscrMask.n = ones; 92110037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 92210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 9237408Sgblack@eecs.umich.edu ~(uint32_t)fpscrMask); 9247408Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 9257408Sgblack@eecs.umich.edu } 9267408Sgblack@eecs.umich.edu break; 9277408Sgblack@eecs.umich.edu case MISCREG_FPSR: 9287408Sgblack@eecs.umich.edu { 9297408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 9307408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 9317408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 9327408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 9337408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 9347408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 93510037SARM gem5 Developers fpscrMask.ixc = ones; 93610037SARM gem5 Developers fpscrMask.idc = ones; 9379377Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9387408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9397408Sgblack@eecs.umich.edu fpscrMask.c = ones; 94010037SARM gem5 Developers fpscrMask.z = ones; 94110037SARM gem5 Developers fpscrMask.n = ones; 94210037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 94310037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 94410037SARM gem5 Developers ~(uint32_t)fpscrMask); 94510037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 94610037SARM gem5 Developers } 94710037SARM gem5 Developers break; 94810037SARM gem5 Developers case MISCREG_FPCR: 94910037SARM gem5 Developers { 95010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 95110037SARM gem5 Developers FPSCR fpscrMask = 0; 95210037SARM gem5 Developers fpscrMask.len = ones; 95310037SARM gem5 Developers fpscrMask.fz16 = ones; 95410037SARM gem5 Developers fpscrMask.stride = ones; 95510037SARM gem5 Developers fpscrMask.rMode = ones; 95610037SARM gem5 Developers fpscrMask.fz = ones; 95710037SARM gem5 Developers fpscrMask.dn = ones; 95810037SARM gem5 Developers fpscrMask.ahp = ones; 95910037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 96010037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 96110037SARM gem5 Developers ~(uint32_t)fpscrMask); 96210037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 96310037SARM gem5 Developers } 96410037SARM gem5 Developers break; 96510037SARM gem5 Developers case MISCREG_CPSR_Q: 96610037SARM gem5 Developers { 96710037SARM gem5 Developers assert(!(newVal & ~CpsrMaskQ)); 96810037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 96910037SARM gem5 Developers misc_reg = MISCREG_CPSR; 97010037SARM gem5 Developers } 97110037SARM gem5 Developers break; 97210037SARM gem5 Developers case MISCREG_FPSCR_QC: 97310037SARM gem5 Developers { 97410037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 97510037SARM gem5 Developers (newVal & FpscrQcMask); 97610037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 97710037SARM gem5 Developers } 97810037SARM gem5 Developers break; 97910037SARM gem5 Developers case MISCREG_FPSCR_EXC: 98010037SARM gem5 Developers { 98110037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 98210037SARM gem5 Developers (newVal & FpscrExcMask); 9838302SAli.Saidi@ARM.com misc_reg = MISCREG_FPSCR; 9848302SAli.Saidi@ARM.com } 9858302SAli.Saidi@ARM.com break; 98610037SARM gem5 Developers case MISCREG_FPEXC: 9878302SAli.Saidi@ARM.com { 9888302SAli.Saidi@ARM.com // vfpv3 architecture, section B.6.1 of DDI04068 9898302SAli.Saidi@ARM.com // bit 29 - valid only if fpexc[31] is 0 9907783SGiacomo.Gabrielli@arm.com const uint32_t fpexcMask = 0x60000000; 9917783SGiacomo.Gabrielli@arm.com newVal = (newVal & fpexcMask) | 99210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 99310037SARM gem5 Developers } 9947783SGiacomo.Gabrielli@arm.com break; 9957783SGiacomo.Gabrielli@arm.com case MISCREG_HCR: 9967783SGiacomo.Gabrielli@arm.com { 9977783SGiacomo.Gabrielli@arm.com if (!haveVirtualization) 9987783SGiacomo.Gabrielli@arm.com return; 99910037SARM gem5 Developers } 100010037SARM gem5 Developers break; 10017783SGiacomo.Gabrielli@arm.com case MISCREG_IFSR: 10027783SGiacomo.Gabrielli@arm.com { 10037783SGiacomo.Gabrielli@arm.com // ARM ARM (ARM DDI 0406C.b) B4.1.96 10047408Sgblack@eecs.umich.edu const uint32_t ifsrMask = 10057408Sgblack@eecs.umich.edu mask(31, 13) | mask(11, 11) | mask(8, 6); 10068206SWilliam.Wang@arm.com newVal = newVal & ~ifsrMask; 10078206SWilliam.Wang@arm.com } 10087408Sgblack@eecs.umich.edu break; 10097408Sgblack@eecs.umich.edu case MISCREG_DFSR: 101010037SARM gem5 Developers { 10117408Sgblack@eecs.umich.edu // ARM ARM (ARM DDI 0406C.b) B4.1.52 10127408Sgblack@eecs.umich.edu const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 101310037SARM gem5 Developers newVal = newVal & ~dfsrMask; 101410037SARM gem5 Developers } 101510037SARM gem5 Developers break; 101610037SARM gem5 Developers case MISCREG_AMAIR0: 101710037SARM gem5 Developers case MISCREG_AMAIR1: 101810037SARM gem5 Developers { 101910037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 102010037SARM gem5 Developers // Valid only with LPAE 102110037SARM gem5 Developers if (!haveLPAE) 102210037SARM gem5 Developers return; 102310037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 102410037SARM gem5 Developers } 102510037SARM gem5 Developers break; 102610037SARM gem5 Developers case MISCREG_SCR: 102710037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 102810037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 102910037SARM gem5 Developers break; 103010037SARM gem5 Developers case MISCREG_SCTLR: 103110037SARM gem5 Developers { 103210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 103310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 103410037SARM gem5 Developers 103510037SARM gem5 Developers MiscRegIndex sctlr_idx; 103610037SARM gem5 Developers if (haveSecurity && !highestELIs64 && !scr.ns) { 103710037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_S; 103810037SARM gem5 Developers } else { 103910037SARM gem5 Developers sctlr_idx = MISCREG_SCTLR_NS; 104010037SARM gem5 Developers } 104110037SARM gem5 Developers 104210037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 104310037SARM gem5 Developers SCTLR new_sctlr = newVal; 104410037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 104510037SARM gem5 Developers miscRegs[sctlr_idx] = (RegVal)new_sctlr; 104610037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 104710037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 10487408Sgblack@eecs.umich.edu } 10497408Sgblack@eecs.umich.edu case MISCREG_MIDR: 10507408Sgblack@eecs.umich.edu case MISCREG_ID_PFR0: 105110037SARM gem5 Developers case MISCREG_ID_PFR1: 105210037SARM gem5 Developers case MISCREG_ID_DFR0: 105310037SARM gem5 Developers case MISCREG_ID_MMFR0: 105410037SARM gem5 Developers case MISCREG_ID_MMFR1: 105510037SARM gem5 Developers case MISCREG_ID_MMFR2: 105610037SARM gem5 Developers case MISCREG_ID_MMFR3: 105710037SARM gem5 Developers case MISCREG_ID_ISAR0: 105810037SARM gem5 Developers case MISCREG_ID_ISAR1: 105910037SARM gem5 Developers case MISCREG_ID_ISAR2: 106010037SARM gem5 Developers case MISCREG_ID_ISAR3: 106110037SARM gem5 Developers case MISCREG_ID_ISAR4: 106210037SARM gem5 Developers case MISCREG_ID_ISAR5: 106310037SARM gem5 Developers 10647408Sgblack@eecs.umich.edu case MISCREG_MPIDR: 106510037SARM gem5 Developers case MISCREG_FPSID: 106610037SARM gem5 Developers case MISCREG_TLBTR: 10677749SAli.Saidi@ARM.com case MISCREG_MVFR0: 10687749SAli.Saidi@ARM.com case MISCREG_MVFR1: 10697408Sgblack@eecs.umich.edu 10709385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64AFR0_EL1: 10719385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64AFR1_EL1: 10729385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64DFR0_EL1: 107310461SAndreas.Sandberg@ARM.com case MISCREG_ID_AA64DFR1_EL1: 10749385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64ISAR0_EL1: 10759385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64ISAR1_EL1: 10769385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64MMFR0_EL1: 10779385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64MMFR1_EL1: 10789385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64MMFR2_EL1: 10799385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64PFR0_EL1: 10809385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64PFR1_EL1: 10819385SAndreas.Sandberg@arm.com // ID registers are constants. 10829385SAndreas.Sandberg@arm.com return; 10839385SAndreas.Sandberg@arm.com 10849385SAndreas.Sandberg@arm.com // TLB Invalidate All 10859385SAndreas.Sandberg@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 10869385SAndreas.Sandberg@arm.com { 10877408Sgblack@eecs.umich.edu assert32(tc); 10887408Sgblack@eecs.umich.edu scr = readMiscReg(MISCREG_SCR, tc); 10897408Sgblack@eecs.umich.edu 109010037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 109110037SARM gem5 Developers tlbiOp(tc); 109210037SARM gem5 Developers return; 109310037SARM gem5 Developers } 109410037SARM gem5 Developers // TLB Invalidate All, Inner Shareable 109510037SARM gem5 Developers case MISCREG_TLBIALLIS: 109610037SARM gem5 Developers { 109710037SARM gem5 Developers assert32(tc); 109810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 109910037SARM gem5 Developers 110010037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 11019385SAndreas.Sandberg@arm.com tlbiOp.broadcast(tc); 11027408Sgblack@eecs.umich.edu return; 11039385SAndreas.Sandberg@arm.com } 110410037SARM gem5 Developers // Instruction TLB Invalidate All 11057408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 110610037SARM gem5 Developers { 110710037SARM gem5 Developers assert32(tc); 110810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 110910037SARM gem5 Developers 111010037SARM gem5 Developers ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 11118284SAli.Saidi@ARM.com tlbiOp(tc); 11128284SAli.Saidi@ARM.com return; 11138284SAli.Saidi@ARM.com } 11148284SAli.Saidi@ARM.com // Data TLB Invalidate All 111510037SARM gem5 Developers case MISCREG_DTLBIALL: 111610037SARM gem5 Developers { 11178887Sgeoffrey.blake@arm.com assert32(tc); 11188887Sgeoffrey.blake@arm.com scr = readMiscReg(MISCREG_SCR, tc); 11198887Sgeoffrey.blake@arm.com 11208733Sgeoffrey.blake@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 112110037SARM gem5 Developers tlbiOp(tc); 112210037SARM gem5 Developers return; 112310037SARM gem5 Developers } 112410037SARM gem5 Developers // TLB Invalidate by VA 11258733Sgeoffrey.blake@arm.com // mcr tlbimval(is) is invalidating all matching entries 11268284SAli.Saidi@ARM.com // regardless of the level of lookup, since in gem5 we cache 11277408Sgblack@eecs.umich.edu // in the tlb the last level of lookup only. 112810037SARM gem5 Developers case MISCREG_TLBIMVA: 11297408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAL: 113010037SARM gem5 Developers { 113110037SARM gem5 Developers assert32(tc); 113210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 113310037SARM gem5 Developers 113410037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 11357408Sgblack@eecs.umich.edu haveSecurity && !scr.ns, 113610037SARM gem5 Developers mbits(newVal, 31, 12), 11377408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 113810037SARM gem5 Developers 113910037SARM gem5 Developers tlbiOp(tc); 114010037SARM gem5 Developers return; 114110037SARM gem5 Developers } 114210037SARM gem5 Developers // TLB Invalidate by VA, Inner Shareable 11437408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 114410037SARM gem5 Developers case MISCREG_TLBIMVALIS: 11457408Sgblack@eecs.umich.edu { 11467408Sgblack@eecs.umich.edu assert32(tc); 114710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 114810037SARM gem5 Developers 114910037SARM gem5 Developers TLBIMVA tlbiOp(EL1, 115010037SARM gem5 Developers haveSecurity && !scr.ns, 11518284SAli.Saidi@ARM.com mbits(newVal, 31, 12), 11528284SAli.Saidi@ARM.com bits(newVal, 7,0)); 11538284SAli.Saidi@ARM.com 11548284SAli.Saidi@ARM.com tlbiOp.broadcast(tc); 11558284SAli.Saidi@ARM.com return; 115610037SARM gem5 Developers } 115710037SARM gem5 Developers // TLB Invalidate by ASID match 11588284SAli.Saidi@ARM.com case MISCREG_TLBIASID: 115910037SARM gem5 Developers { 116010037SARM gem5 Developers assert32(tc); 11618887Sgeoffrey.blake@arm.com scr = readMiscReg(MISCREG_SCR, tc); 11628887Sgeoffrey.blake@arm.com 11638733Sgeoffrey.blake@arm.com TLBIASID tlbiOp(EL1, 11648733Sgeoffrey.blake@arm.com haveSecurity && !scr.ns, 116510037SARM gem5 Developers bits(newVal, 7,0)); 11668733Sgeoffrey.blake@arm.com 116710037SARM gem5 Developers tlbiOp(tc); 11688733Sgeoffrey.blake@arm.com return; 11698284SAli.Saidi@ARM.com } 11707408Sgblack@eecs.umich.edu // TLB Invalidate by ASID match, Inner Shareable 117110037SARM gem5 Developers case MISCREG_TLBIASIDIS: 11727408Sgblack@eecs.umich.edu { 11737408Sgblack@eecs.umich.edu assert32(tc); 117410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 117510037SARM gem5 Developers 117610037SARM gem5 Developers TLBIASID tlbiOp(EL1, 117710037SARM gem5 Developers haveSecurity && !scr.ns, 11788284SAli.Saidi@ARM.com bits(newVal, 7,0)); 11798284SAli.Saidi@ARM.com 11808284SAli.Saidi@ARM.com tlbiOp.broadcast(tc); 11818284SAli.Saidi@ARM.com return; 118210037SARM gem5 Developers } 118310037SARM gem5 Developers // mcr tlbimvaal(is) is invalidating all matching entries 118410037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 118510037SARM gem5 Developers // in the tlb the last level of lookup only. 11868887Sgeoffrey.blake@arm.com // TLB Invalidate by VA, All ASID 11878733Sgeoffrey.blake@arm.com case MISCREG_TLBIMVAA: 118810037SARM gem5 Developers case MISCREG_TLBIMVAAL: 118910037SARM gem5 Developers { 119010037SARM gem5 Developers assert32(tc); 119110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 11928733Sgeoffrey.blake@arm.com 11938284SAli.Saidi@ARM.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 11947408Sgblack@eecs.umich.edu mbits(newVal, 31,12), false); 119510037SARM gem5 Developers 11967408Sgblack@eecs.umich.edu tlbiOp(tc); 11977408Sgblack@eecs.umich.edu return; 119810037SARM gem5 Developers } 119910037SARM gem5 Developers // TLB Invalidate by VA, All ASID, Inner Shareable 120010037SARM gem5 Developers case MISCREG_TLBIMVAAIS: 120110037SARM gem5 Developers case MISCREG_TLBIMVAALIS: 120210037SARM gem5 Developers { 120310037SARM gem5 Developers assert32(tc); 120410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 120510037SARM gem5 Developers 120610037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 120710037SARM gem5 Developers mbits(newVal, 31,12), false); 120810037SARM gem5 Developers 120910037SARM gem5 Developers tlbiOp.broadcast(tc); 121010037SARM gem5 Developers return; 121110037SARM gem5 Developers } 121210037SARM gem5 Developers // mcr tlbimvalh(is) is invalidating all matching entries 121310037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 121410037SARM gem5 Developers // in the tlb the last level of lookup only. 121510037SARM gem5 Developers // TLB Invalidate by VA, Hyp mode 121610037SARM gem5 Developers case MISCREG_TLBIMVAH: 121710037SARM gem5 Developers case MISCREG_TLBIMVALH: 121810037SARM gem5 Developers { 121910037SARM gem5 Developers assert32(tc); 122010037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 122110037SARM gem5 Developers 122210037SARM gem5 Developers TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 122310037SARM gem5 Developers mbits(newVal, 31,12), true); 122410037SARM gem5 Developers 122510037SARM gem5 Developers tlbiOp(tc); 122610037SARM gem5 Developers return; 122710037SARM gem5 Developers } 122810037SARM gem5 Developers // TLB Invalidate by VA, Hyp mode, Inner Shareable 122910037SARM gem5 Developers case MISCREG_TLBIMVAHIS: 123010037SARM gem5 Developers case MISCREG_TLBIMVALHIS: 123110037SARM gem5 Developers { 123210037SARM gem5 Developers assert32(tc); 123310037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 123410037SARM gem5 Developers 123510037SARM gem5 Developers TLBIMVAA tlbiOp(EL2, haveSecurity && !scr.ns, 123610037SARM gem5 Developers mbits(newVal, 31,12), true); 123710037SARM gem5 Developers 123810037SARM gem5 Developers tlbiOp.broadcast(tc); 123910037SARM gem5 Developers return; 124010037SARM gem5 Developers } 124110037SARM gem5 Developers // mcr tlbiipas2l(is) is invalidating all matching entries 124210037SARM gem5 Developers // regardless of the level of lookup, since in gem5 we cache 124310037SARM gem5 Developers // in the tlb the last level of lookup only. 124410037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2 124510037SARM gem5 Developers case MISCREG_TLBIIPAS2: 124610037SARM gem5 Developers case MISCREG_TLBIIPAS2L: 124710037SARM gem5 Developers { 124810037SARM gem5 Developers assert32(tc); 124910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 125010037SARM gem5 Developers 125110037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 125210037SARM gem5 Developers haveSecurity && !scr.ns, 125310037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 125410037SARM gem5 Developers 125510037SARM gem5 Developers tlbiOp(tc); 125610037SARM gem5 Developers return; 125710037SARM gem5 Developers } 125810037SARM gem5 Developers // TLB Invalidate by Intermediate Physical Address, Stage 2, 125910037SARM gem5 Developers // Inner Shareable 126010037SARM gem5 Developers case MISCREG_TLBIIPAS2IS: 126110037SARM gem5 Developers case MISCREG_TLBIIPAS2LIS: 126210037SARM gem5 Developers { 126310037SARM gem5 Developers assert32(tc); 126410037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 126510037SARM gem5 Developers 126610037SARM gem5 Developers TLBIIPA tlbiOp(EL1, 126710037SARM gem5 Developers haveSecurity && !scr.ns, 126810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 126910037SARM gem5 Developers 127010037SARM gem5 Developers tlbiOp.broadcast(tc); 127110037SARM gem5 Developers return; 127210037SARM gem5 Developers } 127310037SARM gem5 Developers // Instruction TLB Invalidate by VA 127410037SARM gem5 Developers case MISCREG_ITLBIMVA: 127510037SARM gem5 Developers { 127610037SARM gem5 Developers assert32(tc); 127710037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 127810037SARM gem5 Developers 127910037SARM gem5 Developers ITLBIMVA tlbiOp(EL1, 128010037SARM gem5 Developers haveSecurity && !scr.ns, 128110037SARM gem5 Developers mbits(newVal, 31, 12), 128210037SARM gem5 Developers bits(newVal, 7,0)); 128310037SARM gem5 Developers 128410037SARM gem5 Developers tlbiOp(tc); 128510037SARM gem5 Developers return; 128610037SARM gem5 Developers } 128710037SARM gem5 Developers // Data TLB Invalidate by VA 128810037SARM gem5 Developers case MISCREG_DTLBIMVA: 128910037SARM gem5 Developers { 129010037SARM gem5 Developers assert32(tc); 129110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 129210037SARM gem5 Developers 129310037SARM gem5 Developers DTLBIMVA tlbiOp(EL1, 129410037SARM gem5 Developers haveSecurity && !scr.ns, 129510037SARM gem5 Developers mbits(newVal, 31, 12), 129610037SARM gem5 Developers bits(newVal, 7,0)); 129710037SARM gem5 Developers 129810037SARM gem5 Developers tlbiOp(tc); 129910037SARM gem5 Developers return; 130010037SARM gem5 Developers } 130110037SARM gem5 Developers // Instruction TLB Invalidate by ASID match 130210037SARM gem5 Developers case MISCREG_ITLBIASID: 130310037SARM gem5 Developers { 130410037SARM gem5 Developers assert32(tc); 130510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 130610037SARM gem5 Developers 130710037SARM gem5 Developers ITLBIASID tlbiOp(EL1, 130810037SARM gem5 Developers haveSecurity && !scr.ns, 130910037SARM gem5 Developers bits(newVal, 7,0)); 131010037SARM gem5 Developers 131110037SARM gem5 Developers tlbiOp(tc); 131210037SARM gem5 Developers return; 131310037SARM gem5 Developers } 131410037SARM gem5 Developers // Data TLB Invalidate by ASID match 131510037SARM gem5 Developers case MISCREG_DTLBIASID: 131610037SARM gem5 Developers { 131710037SARM gem5 Developers assert32(tc); 131810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 131910037SARM gem5 Developers 132010037SARM gem5 Developers DTLBIASID tlbiOp(EL1, 132110037SARM gem5 Developers haveSecurity && !scr.ns, 132210037SARM gem5 Developers bits(newVal, 7,0)); 132310037SARM gem5 Developers 132410037SARM gem5 Developers tlbiOp(tc); 132510037SARM gem5 Developers return; 132610037SARM gem5 Developers } 132710037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp 132810037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 132910037SARM gem5 Developers { 133010037SARM gem5 Developers assert32(tc); 133110037SARM gem5 Developers 133210037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 133310037SARM gem5 Developers tlbiOp(tc); 133410037SARM gem5 Developers return; 133510037SARM gem5 Developers } 133610037SARM gem5 Developers // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 133710037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 133810037SARM gem5 Developers { 133910037SARM gem5 Developers assert32(tc); 134010037SARM gem5 Developers 134110037SARM gem5 Developers TLBIALLN tlbiOp(EL1, false); 134210037SARM gem5 Developers tlbiOp.broadcast(tc); 13438284SAli.Saidi@ARM.com return; 13448284SAli.Saidi@ARM.com } 13458284SAli.Saidi@ARM.com // TLB Invalidate All, Hyp mode 13468284SAli.Saidi@ARM.com case MISCREG_TLBIALLH: 134710037SARM gem5 Developers { 134810709SAndreas.Sandberg@ARM.com assert32(tc); 134910037SARM gem5 Developers 135010037SARM gem5 Developers TLBIALLN tlbiOp(EL2, true); 135110037SARM gem5 Developers tlbiOp(tc); 135210037SARM gem5 Developers return; 135310037SARM gem5 Developers } 135410037SARM gem5 Developers // TLB Invalidate All, Hyp mode, Inner Shareable 135510037SARM gem5 Developers case MISCREG_TLBIALLHIS: 135610037SARM gem5 Developers { 135710037SARM gem5 Developers assert32(tc); 135810037SARM gem5 Developers 135910037SARM gem5 Developers TLBIALLN tlbiOp(EL2, true); 136010037SARM gem5 Developers tlbiOp.broadcast(tc); 136110037SARM gem5 Developers return; 136210037SARM gem5 Developers } 136310037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3 136410037SARM gem5 Developers case MISCREG_TLBI_ALLE3: 136510037SARM gem5 Developers { 136610037SARM gem5 Developers assert64(tc); 136710037SARM gem5 Developers 136810037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 136910037SARM gem5 Developers tlbiOp(tc); 137010037SARM gem5 Developers return; 137110037SARM gem5 Developers } 137210037SARM gem5 Developers // AArch64 TLB Invalidate All, EL3, Inner Shareable 137310037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 137410037SARM gem5 Developers { 137510037SARM gem5 Developers assert64(tc); 137610037SARM gem5 Developers 137710037SARM gem5 Developers TLBIALL tlbiOp(EL3, true); 137810037SARM gem5 Developers tlbiOp.broadcast(tc); 137910037SARM gem5 Developers return; 138010037SARM gem5 Developers } 138110037SARM gem5 Developers // AArch64 TLB Invalidate All, EL2, Inner Shareable 138210037SARM gem5 Developers case MISCREG_TLBI_ALLE2: 13838887Sgeoffrey.blake@arm.com case MISCREG_TLBI_ALLE2IS: 13848887Sgeoffrey.blake@arm.com { 13858733Sgeoffrey.blake@arm.com assert64(tc); 138610037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 138710037SARM gem5 Developers 138810037SARM gem5 Developers TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 138910037SARM gem5 Developers tlbiOp(tc); 13908733Sgeoffrey.blake@arm.com return; 13918284SAli.Saidi@ARM.com } 13927408Sgblack@eecs.umich.edu // AArch64 TLB Invalidate All, EL1 139310037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 139410037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 139510037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 139610037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 139710037SARM gem5 Developers { 139810037SARM gem5 Developers assert64(tc); 139910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 140010037SARM gem5 Developers 14017405SAli.Saidi@ARM.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 14027583SAli.Saidi@arm.com tlbiOp(tc); 14037583SAli.Saidi@arm.com return; 14047583SAli.Saidi@arm.com } 140510461SAndreas.Sandberg@ARM.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 140610461SAndreas.Sandberg@ARM.com case MISCREG_TLBI_ALLE1IS: 140710461SAndreas.Sandberg@ARM.com case MISCREG_TLBI_VMALLE1IS: 140810461SAndreas.Sandberg@ARM.com case MISCREG_TLBI_VMALLS12E1IS: 140910461SAndreas.Sandberg@ARM.com // @todo: handle VMID and stage 2 to enable Virtualization 141010461SAndreas.Sandberg@ARM.com { 14117583SAli.Saidi@arm.com assert64(tc); 141210461SAndreas.Sandberg@ARM.com scr = readMiscReg(MISCREG_SCR, tc); 141310461SAndreas.Sandberg@ARM.com 141410037SARM gem5 Developers TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 141510037SARM gem5 Developers tlbiOp.broadcast(tc); 141610037SARM gem5 Developers return; 141710037SARM gem5 Developers } 141810037SARM gem5 Developers // VAEx(IS) and VALEx(IS) are the same because TLBs 141910037SARM gem5 Developers // only store entries 142010037SARM gem5 Developers // from the last level of translation table walks 142110037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 142210037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3 142310037SARM gem5 Developers case MISCREG_TLBI_VAE3_Xt: 142410037SARM gem5 Developers case MISCREG_TLBI_VALE3_Xt: 142510037SARM gem5 Developers { 142610037SARM gem5 Developers assert64(tc); 142710037SARM gem5 Developers 142810037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 142910037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 143010037SARM gem5 Developers 0xbeef); 143110037SARM gem5 Developers tlbiOp(tc); 143210037SARM gem5 Developers return; 143310037SARM gem5 Developers } 143410037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 143510037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 143610037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 143710037SARM gem5 Developers { 143810037SARM gem5 Developers assert64(tc); 143910037SARM gem5 Developers 144010037SARM gem5 Developers TLBIMVA tlbiOp(EL3, true, 144110037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 144210037SARM gem5 Developers 0xbeef); 144310037SARM gem5 Developers 144410037SARM gem5 Developers tlbiOp.broadcast(tc); 144510037SARM gem5 Developers return; 144610037SARM gem5 Developers } 144710037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2 144810037SARM gem5 Developers case MISCREG_TLBI_VAE2_Xt: 144910037SARM gem5 Developers case MISCREG_TLBI_VALE2_Xt: 145010037SARM gem5 Developers { 14517436Sdam.sunwoo@arm.com assert64(tc); 145210037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 145310037SARM gem5 Developers 145410037SARM gem5 Developers TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 14557436Sdam.sunwoo@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 14567436Sdam.sunwoo@arm.com 0xbeef); 145710037SARM gem5 Developers tlbiOp(tc); 145810037SARM gem5 Developers return; 145910037SARM gem5 Developers } 146010037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 146110037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 146210037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 146310037SARM gem5 Developers { 146410037SARM gem5 Developers assert64(tc); 146510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 146610037SARM gem5 Developers 146710037SARM gem5 Developers TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 146810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 146910037SARM gem5 Developers 0xbeef); 147010037SARM gem5 Developers 147110037SARM gem5 Developers tlbiOp.broadcast(tc); 147210037SARM gem5 Developers return; 147310037SARM gem5 Developers } 147410037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1 147510037SARM gem5 Developers case MISCREG_TLBI_VAE1_Xt: 147610037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 147710037SARM gem5 Developers { 147810037SARM gem5 Developers assert64(tc); 147910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 148010037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 148110037SARM gem5 Developers bits(newVal, 55, 48); 148210037SARM gem5 Developers 148310037SARM gem5 Developers TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 148410037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 148510037SARM gem5 Developers asid); 148610037SARM gem5 Developers 148710037SARM gem5 Developers tlbiOp(tc); 148810037SARM gem5 Developers return; 148910037SARM gem5 Developers } 149010037SARM gem5 Developers // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 149110037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 149210037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 149310037SARM gem5 Developers { 149410037SARM gem5 Developers assert64(tc); 149510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 149610037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 149710037SARM gem5 Developers bits(newVal, 55, 48); 149810037SARM gem5 Developers 149910037SARM gem5 Developers TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 150010037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, 150110037SARM gem5 Developers asid); 150210037SARM gem5 Developers 150310037SARM gem5 Developers tlbiOp.broadcast(tc); 150410037SARM gem5 Developers return; 150510037SARM gem5 Developers } 150610037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1 150710037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 150810037SARM gem5 Developers case MISCREG_TLBI_ASIDE1_Xt: 150910037SARM gem5 Developers { 151010037SARM gem5 Developers assert64(tc); 151110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 151210037SARM gem5 Developers auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 151310037SARM gem5 Developers bits(newVal, 55, 48); 151410037SARM gem5 Developers 15157436Sdam.sunwoo@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 151610037SARM gem5 Developers tlbiOp(tc); 151710037SARM gem5 Developers return; 151810037SARM gem5 Developers } 151910037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 152010037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 152110037SARM gem5 Developers { 152210037SARM gem5 Developers assert64(tc); 152310653Sandreas.hansson@arm.com scr = readMiscReg(MISCREG_SCR, tc); 152411435Smitch.hayenga@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 152510653Sandreas.hansson@arm.com bits(newVal, 55, 48); 152610037SARM gem5 Developers 152710037SARM gem5 Developers TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 152810037SARM gem5 Developers tlbiOp.broadcast(tc); 152910037SARM gem5 Developers return; 15307436Sdam.sunwoo@arm.com } 153110653Sandreas.hansson@arm.com // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 153210037SARM gem5 Developers // entries from the last level of translation table walks 153310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1 153410037SARM gem5 Developers case MISCREG_TLBI_VAAE1_Xt: 153510037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 153610037SARM gem5 Developers { 153710037SARM gem5 Developers assert64(tc); 153810037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 153910037SARM gem5 Developers 15407436Sdam.sunwoo@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 15417436Sdam.sunwoo@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 154210037SARM gem5 Developers 154310037SARM gem5 Developers tlbiOp(tc); 154410037SARM gem5 Developers return; 154510037SARM gem5 Developers } 154610037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 154710037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 154810037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 154910037SARM gem5 Developers { 155010037SARM gem5 Developers assert64(tc); 155110037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 155210037SARM gem5 Developers 155310037SARM gem5 Developers TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 155410037SARM gem5 Developers static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 155510037SARM gem5 Developers 155610037SARM gem5 Developers tlbiOp.broadcast(tc); 155710037SARM gem5 Developers return; 155810037SARM gem5 Developers } 155910037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 156010037SARM gem5 Developers // Stage 2, EL1 156110037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1_Xt: 156210037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 156310037SARM gem5 Developers { 15647436Sdam.sunwoo@arm.com assert64(tc); 156510037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 15667436Sdam.sunwoo@arm.com 15677436Sdam.sunwoo@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 156810037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 156910037SARM gem5 Developers 157010037SARM gem5 Developers tlbiOp(tc); 157110037SARM gem5 Developers return; 157210037SARM gem5 Developers } 157310037SARM gem5 Developers // AArch64 TLB Invalidate by Intermediate Physical Address, 157410037SARM gem5 Developers // Stage 2, EL1, Inner Shareable 157510037SARM gem5 Developers case MISCREG_TLBI_IPAS2E1IS_Xt: 157610037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 157710037SARM gem5 Developers { 157810037SARM gem5 Developers assert64(tc); 157910037SARM gem5 Developers scr = readMiscReg(MISCREG_SCR, tc); 158010037SARM gem5 Developers 158110037SARM gem5 Developers TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 158210037SARM gem5 Developers static_cast<Addr>(bits(newVal, 35, 0)) << 12); 158310037SARM gem5 Developers 158410037SARM gem5 Developers tlbiOp.broadcast(tc); 158510037SARM gem5 Developers return; 158610037SARM gem5 Developers } 158710037SARM gem5 Developers case MISCREG_ACTLR: 158810037SARM gem5 Developers warn("Not doing anything for write of miscreg ACTLR\n"); 158910037SARM gem5 Developers break; 159010037SARM gem5 Developers 159110037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 159210037SARM gem5 Developers case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 159310037SARM gem5 Developers case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 159410037SARM gem5 Developers case MISCREG_PMCR ... MISCREG_PMOVSSET: 159510037SARM gem5 Developers pmu->setMiscReg(misc_reg, newVal); 159610037SARM gem5 Developers break; 159710037SARM gem5 Developers 159810037SARM gem5 Developers 159910037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 160010037SARM gem5 Developers { 160110037SARM gem5 Developers HSTR hstrMask = 0; 160210037SARM gem5 Developers hstrMask.tjdbx = 1; 160310037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 160410037SARM gem5 Developers break; 160510037SARM gem5 Developers } 160610037SARM gem5 Developers case MISCREG_HCPTR: 160710037SARM gem5 Developers { 160810037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 160910037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 161010037SARM gem5 Developers secure_lookup = haveSecurity && 161110037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 161210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 161310508SAli.Saidi@ARM.com if (!secure_lookup) { 161410508SAli.Saidi@ARM.com RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 161510508SAli.Saidi@ARM.com RegVal mask = 161610508SAli.Saidi@ARM.com (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 161710508SAli.Saidi@ARM.com newVal = (newVal & ~mask) | (oldValue & mask); 161810508SAli.Saidi@ARM.com } 16197749SAli.Saidi@ARM.com break; 16207749SAli.Saidi@ARM.com } 16217749SAli.Saidi@ARM.com case MISCREG_HDFAR: // alias for secure DFAR 162210037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 162310037SARM gem5 Developers break; 16247749SAli.Saidi@ARM.com case MISCREG_HIFAR: // alias for secure IFAR 162510037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 162610037SARM gem5 Developers break; 162710037SARM gem5 Developers case MISCREG_ATS1CPR: 162810037SARM gem5 Developers case MISCREG_ATS1CPW: 162910037SARM gem5 Developers case MISCREG_ATS1CUR: 163010508SAli.Saidi@ARM.com case MISCREG_ATS1CUW: 163110508SAli.Saidi@ARM.com case MISCREG_ATS12NSOPR: 163210037SARM gem5 Developers case MISCREG_ATS12NSOPW: 163310037SARM gem5 Developers case MISCREG_ATS12NSOUR: 163410037SARM gem5 Developers case MISCREG_ATS12NSOUW: 163510037SARM gem5 Developers case MISCREG_ATS1HR: 16367749SAli.Saidi@ARM.com case MISCREG_ATS1HW: 16377749SAli.Saidi@ARM.com { 16387749SAli.Saidi@ARM.com Request::Flags flags = 0; 163910037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 164010037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 164110037SARM gem5 Developers Fault fault; 164210037SARM gem5 Developers switch(misc_reg) { 164310338SCurtis.Dunham@arm.com case MISCREG_ATS1CPR: 164410338SCurtis.Dunham@arm.com flags = TLB::MustBeOne; 164510338SCurtis.Dunham@arm.com tranType = TLB::S1CTran; 164610037SARM gem5 Developers mode = BaseTLB::Read; 164710037SARM gem5 Developers break; 164810037SARM gem5 Developers case MISCREG_ATS1CPW: 164910037SARM gem5 Developers flags = TLB::MustBeOne; 165010037SARM gem5 Developers tranType = TLB::S1CTran; 165110037SARM gem5 Developers mode = BaseTLB::Write; 165210037SARM gem5 Developers break; 165310037SARM gem5 Developers case MISCREG_ATS1CUR: 165410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 165510037SARM gem5 Developers tranType = TLB::S1CTran; 165610037SARM gem5 Developers mode = BaseTLB::Read; 165710037SARM gem5 Developers break; 165810037SARM gem5 Developers case MISCREG_ATS1CUW: 165910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 166010037SARM gem5 Developers tranType = TLB::S1CTran; 166110037SARM gem5 Developers mode = BaseTLB::Write; 166210037SARM gem5 Developers break; 166310037SARM gem5 Developers case MISCREG_ATS12NSOPR: 166410037SARM gem5 Developers if (!haveSecurity) 166510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 166610037SARM gem5 Developers flags = TLB::MustBeOne; 166710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 166810037SARM gem5 Developers mode = BaseTLB::Read; 166910037SARM gem5 Developers break; 167010037SARM gem5 Developers case MISCREG_ATS12NSOPW: 167110037SARM gem5 Developers if (!haveSecurity) 167210037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 167310037SARM gem5 Developers flags = TLB::MustBeOne; 167410037SARM gem5 Developers tranType = TLB::S1S2NsTran; 167510037SARM gem5 Developers mode = BaseTLB::Write; 167610037SARM gem5 Developers break; 167710037SARM gem5 Developers case MISCREG_ATS12NSOUR: 167810037SARM gem5 Developers if (!haveSecurity) 167910037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 168010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168110037SARM gem5 Developers tranType = TLB::S1S2NsTran; 168210037SARM gem5 Developers mode = BaseTLB::Read; 168310037SARM gem5 Developers break; 168410037SARM gem5 Developers case MISCREG_ATS12NSOUW: 168510037SARM gem5 Developers if (!haveSecurity) 168610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 168710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 168910037SARM gem5 Developers mode = BaseTLB::Write; 169010037SARM gem5 Developers break; 169110037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 169210037SARM gem5 Developers flags = TLB::MustBeOne; 169310037SARM gem5 Developers tranType = TLB::HypMode; 169410037SARM gem5 Developers mode = BaseTLB::Read; 169510037SARM gem5 Developers break; 169610037SARM gem5 Developers case MISCREG_ATS1HW: 169710037SARM gem5 Developers flags = TLB::MustBeOne; 169810037SARM gem5 Developers tranType = TLB::HypMode; 169910037SARM gem5 Developers mode = BaseTLB::Write; 170010037SARM gem5 Developers break; 170110037SARM gem5 Developers } 170210037SARM gem5 Developers // If we're in timing mode then doing the translation in 170310037SARM gem5 Developers // functional mode then we're slightly distorting performance 170410037SARM gem5 Developers // results obtained from simulations. The translation should be 170510037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 170610037SARM gem5 Developers // can't be an atomic translation because that causes problems 170710037SARM gem5 Developers // with unexpected atomic snoop requests. 170810037SARM gem5 Developers warn("Translating via %s in functional mode! Fix Me!\n", 170910037SARM gem5 Developers miscRegName[misc_reg]); 171010037SARM gem5 Developers 171110037SARM gem5 Developers auto req = std::make_shared<Request>( 171210037SARM gem5 Developers 0, val, 0, flags, Request::funcMasterId, 171310037SARM gem5 Developers tc->pcState().pc(), tc->contextId()); 171410037SARM gem5 Developers 171510037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional( 171610037SARM gem5 Developers req, tc, mode, tranType); 171710037SARM gem5 Developers 171810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 171910037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 172010037SARM gem5 Developers 172110037SARM gem5 Developers RegVal newVal; 172210037SARM gem5 Developers if (fault == NoFault) { 172310037SARM gem5 Developers Addr paddr = req->getPaddr(); 172410037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 172510037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 172610037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 172710037SARM gem5 Developers (getDTBPtr(tc)->getAttr()); 172810037SARM gem5 Developers } else { 172910037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 173010037SARM gem5 Developers (getDTBPtr(tc)->getAttr()); 173110037SARM gem5 Developers } 173210037SARM gem5 Developers DPRINTF(MiscRegs, 173310037SARM gem5 Developers "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 173410037SARM gem5 Developers val, newVal); 173510037SARM gem5 Developers } else { 173610037SARM gem5 Developers ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 173710037SARM gem5 Developers armFault->update(tc); 173810037SARM gem5 Developers // Set fault bit and FSR 173910037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 174010037SARM gem5 Developers 174110037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 174210037SARM gem5 Developers if (newVal) { 174310037SARM gem5 Developers // LPAE - rearange fault status 174410037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 174510037SARM gem5 Developers } else { 174610037SARM gem5 Developers // VMSA - rearange fault status 174710037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 174810037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 174910037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 175010037SARM gem5 Developers } 175110037SARM gem5 Developers newVal |= 0x1; // F bit 175210037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 175310037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 175410037SARM gem5 Developers DPRINTF(MiscRegs, 175510037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 175610037SARM gem5 Developers val, fsr, newVal); 175710037SARM gem5 Developers } 175810037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 175910037SARM gem5 Developers return; 176010037SARM gem5 Developers } 176110037SARM gem5 Developers case MISCREG_TTBCR: 176210037SARM gem5 Developers { 176310037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 176410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 176510037SARM gem5 Developers TTBCR ttbcrMask = 0; 176610037SARM gem5 Developers TTBCR ttbcrNew = newVal; 176710037SARM gem5 Developers 176810037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 176910037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 177011435Smitch.hayenga@arm.com if (haveSecurity) { 177110037SARM gem5 Developers ttbcrMask.pd0 = ones; 177210037SARM gem5 Developers ttbcrMask.pd1 = ones; 177310037SARM gem5 Developers } 177410037SARM gem5 Developers ttbcrMask.epd0 = ones; 177510037SARM gem5 Developers ttbcrMask.irgn0 = ones; 177610037SARM gem5 Developers ttbcrMask.orgn0 = ones; 177710037SARM gem5 Developers ttbcrMask.sh0 = ones; 177810037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 177910037SARM gem5 Developers ttbcrMask.a1 = ones; 178010037SARM gem5 Developers ttbcrMask.epd1 = ones; 178110037SARM gem5 Developers ttbcrMask.irgn1 = ones; 178210037SARM gem5 Developers ttbcrMask.orgn1 = ones; 178310037SARM gem5 Developers ttbcrMask.sh1 = ones; 178410037SARM gem5 Developers if (haveLPAE) 178510037SARM gem5 Developers ttbcrMask.eae = ones; 178610037SARM gem5 Developers 178710037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 178810037SARM gem5 Developers newVal = newVal & ttbcrMask; 178910037SARM gem5 Developers } else { 179010037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 179110037SARM gem5 Developers } 179210037SARM gem5 Developers // Invalidate TLB MiscReg 179310037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 179410037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 179510037SARM gem5 Developers break; 179610037SARM gem5 Developers } 179710037SARM gem5 Developers case MISCREG_TTBR0: 179810037SARM gem5 Developers case MISCREG_TTBR1: 179910037SARM gem5 Developers { 180010037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 180110037SARM gem5 Developers if (haveLPAE) { 180210037SARM gem5 Developers if (ttbcr.eae) { 180310037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 180410037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 180510037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 180610037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 180710037SARM gem5 Developers } 180810037SARM gem5 Developers } 180910037SARM gem5 Developers // Invalidate TLB MiscReg 181010037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 181110037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 18128549Sdaniel.johnson@arm.com break; 18138549Sdaniel.johnson@arm.com } 18148549Sdaniel.johnson@arm.com case MISCREG_SCTLR_EL1: 181510037SARM gem5 Developers case MISCREG_CONTEXTIDR: 181610037SARM gem5 Developers case MISCREG_PRRR: 181710037SARM gem5 Developers case MISCREG_NMRR: 181810844Sandreas.sandberg@arm.com case MISCREG_MAIR0: 181910844Sandreas.sandberg@arm.com case MISCREG_MAIR1: 182010844Sandreas.sandberg@arm.com case MISCREG_DACR: 182110844Sandreas.sandberg@arm.com case MISCREG_VTTBR: 182210844Sandreas.sandberg@arm.com case MISCREG_SCR_EL3: 182310037SARM gem5 Developers case MISCREG_HCR_EL2: 18247405SAli.Saidi@ARM.com case MISCREG_TCR_EL1: 18257405SAli.Saidi@ARM.com case MISCREG_TCR_EL2: 18267405SAli.Saidi@ARM.com case MISCREG_TCR_EL3: 18277405SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 18287405SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 182910037SARM gem5 Developers case MISCREG_HSCTLR: 183010709SAndreas.Sandberg@ARM.com case MISCREG_TTBR0_EL1: 183110709SAndreas.Sandberg@ARM.com case MISCREG_TTBR1_EL1: 183210037SARM gem5 Developers case MISCREG_TTBR0_EL2: 183310709SAndreas.Sandberg@ARM.com case MISCREG_TTBR1_EL2: 183410037SARM gem5 Developers case MISCREG_TTBR0_EL3: 183510037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 183610037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 183710037SARM gem5 Developers break; 183810037SARM gem5 Developers case MISCREG_NZCV: 183910037SARM gem5 Developers { 184010037SARM gem5 Developers CPSR cpsr = val; 184110037SARM gem5 Developers 184210037SARM gem5 Developers tc->setCCReg(CCREG_NZ, cpsr.nz); 184310037SARM gem5 Developers tc->setCCReg(CCREG_C, cpsr.c); 184410037SARM gem5 Developers tc->setCCReg(CCREG_V, cpsr.v); 184510037SARM gem5 Developers } 184610037SARM gem5 Developers break; 184710037SARM gem5 Developers case MISCREG_DAIF: 184810037SARM gem5 Developers { 184910037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 185010037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 185110037SARM gem5 Developers newVal = cpsr; 185210037SARM gem5 Developers misc_reg = MISCREG_CPSR; 185310037SARM gem5 Developers } 185410037SARM gem5 Developers break; 185510037SARM gem5 Developers case MISCREG_SP_EL0: 185610037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 185710037SARM gem5 Developers break; 185810037SARM gem5 Developers case MISCREG_SP_EL1: 185910037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 186010037SARM gem5 Developers break; 186110037SARM gem5 Developers case MISCREG_SP_EL2: 186210037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 186310037SARM gem5 Developers break; 186410037SARM gem5 Developers case MISCREG_SPSEL: 186510037SARM gem5 Developers { 186610037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 186710037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 186810037SARM gem5 Developers newVal = cpsr; 186910037SARM gem5 Developers misc_reg = MISCREG_CPSR; 187010037SARM gem5 Developers } 187110037SARM gem5 Developers break; 187210037SARM gem5 Developers case MISCREG_CURRENTEL: 187310037SARM gem5 Developers { 187410037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 187510037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 187610037SARM gem5 Developers newVal = cpsr; 187710037SARM gem5 Developers misc_reg = MISCREG_CPSR; 187810037SARM gem5 Developers } 187910037SARM gem5 Developers break; 188010037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 188110037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 188210037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 188310037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 188410037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 188510037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 188610037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 188710037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 188810037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 188910037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 189010037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 189110037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 189210037SARM gem5 Developers { 189310037SARM gem5 Developers RequestPtr req = std::make_shared<Request>(); 189410037SARM gem5 Developers Request::Flags flags = 0; 189510037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 189610037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 189710037SARM gem5 Developers Fault fault; 189810037SARM gem5 Developers switch(misc_reg) { 189910037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 190010037SARM gem5 Developers flags = TLB::MustBeOne; 190110037SARM gem5 Developers tranType = TLB::S1E1Tran; 190210037SARM gem5 Developers mode = BaseTLB::Read; 190310037SARM gem5 Developers break; 190410037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 190510037SARM gem5 Developers flags = TLB::MustBeOne; 190610037SARM gem5 Developers tranType = TLB::S1E1Tran; 190710037SARM gem5 Developers mode = BaseTLB::Write; 190810037SARM gem5 Developers break; 190910037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 191010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 191110037SARM gem5 Developers tranType = TLB::S1E0Tran; 191210037SARM gem5 Developers mode = BaseTLB::Read; 191310037SARM gem5 Developers break; 191410037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 191510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 191610037SARM gem5 Developers tranType = TLB::S1E0Tran; 191710844Sandreas.sandberg@arm.com mode = BaseTLB::Write; 191810844Sandreas.sandberg@arm.com break; 191910037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 192010844Sandreas.sandberg@arm.com flags = TLB::MustBeOne; 192110844Sandreas.sandberg@arm.com tranType = TLB::S1E2Tran; 192210844Sandreas.sandberg@arm.com mode = BaseTLB::Read; 192310844Sandreas.sandberg@arm.com break; 192410844Sandreas.sandberg@arm.com case MISCREG_AT_S1E2W_Xt: 192510844Sandreas.sandberg@arm.com flags = TLB::MustBeOne; 192610844Sandreas.sandberg@arm.com tranType = TLB::S1E2Tran; 192710844Sandreas.sandberg@arm.com mode = BaseTLB::Write; 192810844Sandreas.sandberg@arm.com break; 192910844Sandreas.sandberg@arm.com case MISCREG_AT_S12E0R_Xt: 193010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 193110037SARM gem5 Developers tranType = TLB::S12E0Tran; 193211150Smitch.hayenga@arm.com mode = BaseTLB::Read; 193310844Sandreas.sandberg@arm.com break; 193410037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 193510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 19367405SAli.Saidi@ARM.com tranType = TLB::S12E0Tran; 19379384SAndreas.Sandberg@arm.com mode = BaseTLB::Write; 19389384SAndreas.Sandberg@arm.com break; 19399384SAndreas.Sandberg@arm.com case MISCREG_AT_S12E1R_Xt: 19409384SAndreas.Sandberg@arm.com flags = TLB::MustBeOne; 19419384SAndreas.Sandberg@arm.com tranType = TLB::S12E1Tran; 19429384SAndreas.Sandberg@arm.com mode = BaseTLB::Read; 1943 break; 1944 case MISCREG_AT_S12E1W_Xt: 1945 flags = TLB::MustBeOne; 1946 tranType = TLB::S12E1Tran; 1947 mode = BaseTLB::Write; 1948 break; 1949 case MISCREG_AT_S1E3R_Xt: 1950 flags = TLB::MustBeOne; 1951 tranType = TLB::S1E3Tran; 1952 mode = BaseTLB::Read; 1953 break; 1954 case MISCREG_AT_S1E3W_Xt: 1955 flags = TLB::MustBeOne; 1956 tranType = TLB::S1E3Tran; 1957 mode = BaseTLB::Write; 1958 break; 1959 } 1960 // If we're in timing mode then doing the translation in 1961 // functional mode then we're slightly distorting performance 1962 // results obtained from simulations. The translation should be 1963 // done in the same mode the core is running in. NOTE: This 1964 // can't be an atomic translation because that causes problems 1965 // with unexpected atomic snoop requests. 1966 warn("Translating via %s in functional mode! Fix Me!\n", 1967 miscRegName[misc_reg]); 1968 1969 req->setVirt(0, val, 0, flags, Request::funcMasterId, 1970 tc->pcState().pc()); 1971 req->setContext(tc->contextId()); 1972 fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 1973 tranType); 1974 1975 RegVal newVal; 1976 if (fault == NoFault) { 1977 Addr paddr = req->getPaddr(); 1978 uint64_t attr = getDTBPtr(tc)->getAttr(); 1979 uint64_t attr1 = attr >> 56; 1980 if (!attr1 || attr1 ==0x44) { 1981 attr |= 0x100; 1982 attr &= ~ uint64_t(0x80); 1983 } 1984 newVal = (paddr & mask(47, 12)) | attr; 1985 DPRINTF(MiscRegs, 1986 "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 1987 val, newVal); 1988 } else { 1989 ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 1990 armFault->update(tc); 1991 // Set fault bit and FSR 1992 FSR fsr = armFault->getFsr(tc); 1993 1994 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1995 if (cpsr.width) { // AArch32 1996 newVal = ((fsr >> 9) & 1) << 11; 1997 // rearrange fault status 1998 newVal |= ((fsr >> 0) & 0x3f) << 1; 1999 newVal |= 0x1; // F bit 2000 newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 2001 newVal |= armFault->isStage2() ? 0x200 : 0; 2002 } else { // AArch64 2003 newVal = 1; // F bit 2004 newVal |= fsr << 1; // FST 2005 // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 2006 newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 2007 newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 2008 newVal |= 1 << 11; // RES1 2009 } 2010 DPRINTF(MiscRegs, 2011 "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 2012 val, fsr, newVal); 2013 } 2014 setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 2015 return; 2016 } 2017 case MISCREG_SPSR_EL3: 2018 case MISCREG_SPSR_EL2: 2019 case MISCREG_SPSR_EL1: 2020 // Force bits 23:21 to 0 2021 newVal = val & ~(0x7 << 21); 2022 break; 2023 case MISCREG_L2CTLR: 2024 warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 2025 miscRegName[misc_reg], uint32_t(val)); 2026 break; 2027 2028 // Generic Timer registers 2029 case MISCREG_CNTHV_CTL_EL2: 2030 case MISCREG_CNTHV_CVAL_EL2: 2031 case MISCREG_CNTHV_TVAL_EL2: 2032 case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 2033 case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 2034 case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 2035 case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 2036 getGenericTimer(tc).setMiscReg(misc_reg, newVal); 2037 break; 2038 case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 2039 case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 2040 getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 2041 return; 2042 case MISCREG_ZCR_EL3: 2043 case MISCREG_ZCR_EL2: 2044 case MISCREG_ZCR_EL1: 2045 tc->getDecoderPtr()->setSveLen( 2046 (getCurSveVecLenInBits(tc) >> 7) - 1); 2047 break; 2048 } 2049 } 2050 setMiscRegNoEffect(misc_reg, newVal); 2051} 2052 2053BaseISADevice & 2054ISA::getGenericTimer(ThreadContext *tc) 2055{ 2056 // We only need to create an ISA interface the first time we try 2057 // to access the timer. 2058 if (timer) 2059 return *timer.get(); 2060 2061 assert(system); 2062 GenericTimer *generic_timer(system->getGenericTimer()); 2063 if (!generic_timer) { 2064 panic("Trying to get a generic timer from a system that hasn't " 2065 "been configured to use a generic timer.\n"); 2066 } 2067 2068 timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 2069 timer->setThreadContext(tc); 2070 2071 return *timer.get(); 2072} 2073 2074BaseISADevice & 2075ISA::getGICv3CPUInterface(ThreadContext *tc) 2076{ 2077 panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 2078 return *gicv3CpuInterface.get(); 2079} 2080 2081unsigned 2082ISA::getCurSveVecLenInBits(ThreadContext *tc) const 2083{ 2084 if (!FullSystem) { 2085 return sveVL * 128; 2086 } 2087 2088 panic_if(!tc, 2089 "A ThreadContext is needed to determine the SVE vector length " 2090 "in full-system mode"); 2091 2092 CPSR cpsr = miscRegs[MISCREG_CPSR]; 2093 ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 2094 2095 unsigned len = 0; 2096 2097 if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 2098 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 2099 } 2100 2101 if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 2102 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 2103 } else if (haveVirtualization && !inSecureState(tc) && 2104 (el == EL0 || el == EL1)) { 2105 len = std::min( 2106 len, 2107 static_cast<unsigned>( 2108 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 2109 } 2110 2111 if (el == EL3) { 2112 len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 2113 } else if (haveSecurity) { 2114 len = std::min( 2115 len, 2116 static_cast<unsigned>( 2117 static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 2118 } 2119 2120 len = std::min(len, sveVL - 1); 2121 2122 return (len + 1) * 128; 2123} 2124 2125void 2126ISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 2127{ 2128 auto vv = vc.as<uint64_t>(); 2129 for (int i = 2; i < eCount; ++i) { 2130 vv[i] = 0; 2131 } 2132} 2133 2134} // namespace ArmISA 2135 2136ArmISA::ISA * 2137ArmISAParams::create() 2138{ 2139 return new ArmISA::ISA(this); 2140} 2141