isa.cc revision 13759
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4611793Sbrandon.potter@amd.com#include "cpu/base.hh" 478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 488232Snate@binkert.org#include "debug/Arm.hh" 498232Snate@binkert.org#include "debug/MiscRegs.hh" 5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 5113531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh" 5213531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh" 539384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 547678Sgblack@eecs.umich.edu#include "sim/faults.hh" 558059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 568284SAli.Saidi@ARM.com#include "sim/system.hh" 577405SAli.Saidi@ARM.com 587405SAli.Saidi@ARM.comnamespace ArmISA 597405SAli.Saidi@ARM.com{ 607405SAli.Saidi@ARM.com 619384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 6210461SAndreas.Sandberg@ARM.com : SimObject(p), 6310461SAndreas.Sandberg@ARM.com system(NULL), 6411165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 6513599Sgiacomo.travaglini@arm.com _vecRegRenameMode(Enums::Full), 6612714Sgiacomo.travaglini@arm.com pmu(p->pmu), 6713691Sgiacomo.travaglini@arm.com haveGICv3CPUInterface(false), 6812714Sgiacomo.travaglini@arm.com impdefAsNop(p->impdef_nop) 699384SAndreas.Sandberg@arm.com{ 7011770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 7110037SARM gem5 Developers 7210461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 7310461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 7410461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7510461SAndreas.Sandberg@ARM.com if (!pmu) 7610461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7710461SAndreas.Sandberg@ARM.com 7810609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 7910609Sandreas.sandberg@arm.com pmu->setISA(this); 8010609Sandreas.sandberg@arm.com 8110037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 8210037SARM gem5 Developers 8310037SARM gem5 Developers // Cache system-level properties 8410037SARM gem5 Developers if (FullSystem && system) { 8511771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 8610037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8710037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8813173Sgiacomo.travaglini@arm.com haveCrypto = system->haveCrypto(); 8910037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 9010037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 9113114Sgiacomo.travaglini@arm.com physAddrRange = system->physAddrRange(); 9213759Sgiacomo.gabrielli@arm.com haveSVE = system->haveSVE(); 9313759Sgiacomo.gabrielli@arm.com sveVL = system->sveVL(); 9410037SARM gem5 Developers } else { 9511771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9610037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9713499Sgiacomo.travaglini@arm.com haveCrypto = true; 9810037SARM gem5 Developers haveLargeAsid64 = false; 9913114Sgiacomo.travaglini@arm.com physAddrRange = 32; // dummy value 10013759Sgiacomo.gabrielli@arm.com haveSVE = true; 10113759Sgiacomo.gabrielli@arm.com sveVL = p->sve_vl_se; 10210037SARM gem5 Developers } 10310037SARM gem5 Developers 10413599Sgiacomo.travaglini@arm.com // Initial rename mode depends on highestEL 10513599Sgiacomo.travaglini@arm.com const_cast<Enums::VecRegRenameMode&>(_vecRegRenameMode) = 10613599Sgiacomo.travaglini@arm.com highestELIs64 ? Enums::Full : Enums::Elem; 10713599Sgiacomo.travaglini@arm.com 10812477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 10910037SARM gem5 Developers preUnflattenMiscReg(); 11010037SARM gem5 Developers 1119384SAndreas.Sandberg@arm.com clear(); 1129384SAndreas.Sandberg@arm.com} 1139384SAndreas.Sandberg@arm.com 11412479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 11512479SCurtis.Dunham@arm.com 1169384SAndreas.Sandberg@arm.comconst ArmISAParams * 1179384SAndreas.Sandberg@arm.comISA::params() const 1189384SAndreas.Sandberg@arm.com{ 1199384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1209384SAndreas.Sandberg@arm.com} 1219384SAndreas.Sandberg@arm.com 1227427Sgblack@eecs.umich.eduvoid 1237427Sgblack@eecs.umich.eduISA::clear() 1247427Sgblack@eecs.umich.edu{ 1259385SAndreas.Sandberg@arm.com const Params *p(params()); 1269385SAndreas.Sandberg@arm.com 1277427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1287427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 12910037SARM gem5 Developers 13013114Sgiacomo.travaglini@arm.com initID32(p); 13110037SARM gem5 Developers 13213114Sgiacomo.travaglini@arm.com // We always initialize AArch64 ID registers even 13313114Sgiacomo.travaglini@arm.com // if we are in AArch32. This is done since if we 13413114Sgiacomo.travaglini@arm.com // are in SE mode we don't know if our ArmProcess is 13513114Sgiacomo.travaglini@arm.com // AArch32 or AArch64 13613114Sgiacomo.travaglini@arm.com initID64(p); 13712690Sgiacomo.travaglini@arm.com 13810037SARM gem5 Developers // Start with an event in the mailbox 1397427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 1407427Sgblack@eecs.umich.edu 14110037SARM gem5 Developers // Separate Instruction and Data TLBs 1427427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1437427Sgblack@eecs.umich.edu 1447427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1457427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1467427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1477427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1487427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1497427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1507427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1517427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1527427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1537427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1547427Sgblack@eecs.umich.edu 1557427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1567427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1577427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1587427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1597427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1607427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1617427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1627427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1637427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1647427Sgblack@eecs.umich.edu 1657436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1667436Sdam.sunwoo@arm.com 16710037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 16810037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 1697436Sdam.sunwoo@arm.com (1 << 19) | // 19 1707436Sdam.sunwoo@arm.com (0 << 18) | // 18 1717436Sdam.sunwoo@arm.com (0 << 17) | // 17 1727436Sdam.sunwoo@arm.com (1 << 16) | // 16 1737436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1747436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1757436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1767436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1777436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1787436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1797436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1807436Sdam.sunwoo@arm.com 0; // 1:0 18113393Sgiacomo.travaglini@arm.com 18210037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 1837436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1847436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1857436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1867436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1877436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1887436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1897436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1907436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1917436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1927436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1937436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1947436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1957436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1967436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1977436Sdam.sunwoo@arm.com 0; // 1:0 1987436Sdam.sunwoo@arm.com 19913393Sgiacomo.travaglini@arm.com if (FullSystem && system->highestELIs64()) { 20013393Sgiacomo.travaglini@arm.com // Initialize AArch64 state 20113393Sgiacomo.travaglini@arm.com clear64(p); 20213393Sgiacomo.travaglini@arm.com return; 20313393Sgiacomo.travaglini@arm.com } 20413393Sgiacomo.travaglini@arm.com 20513393Sgiacomo.travaglini@arm.com // Initialize AArch32 state... 20613393Sgiacomo.travaglini@arm.com clear32(p, sctlr_rst); 20713393Sgiacomo.travaglini@arm.com} 20813393Sgiacomo.travaglini@arm.com 20913393Sgiacomo.travaglini@arm.comvoid 21013393Sgiacomo.travaglini@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 21113393Sgiacomo.travaglini@arm.com{ 21213393Sgiacomo.travaglini@arm.com CPSR cpsr = 0; 21313393Sgiacomo.travaglini@arm.com cpsr.mode = MODE_USER; 21413393Sgiacomo.travaglini@arm.com 21513396Sgiacomo.travaglini@arm.com if (FullSystem) { 21613396Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MVBAR] = system->resetAddr(); 21713396Sgiacomo.travaglini@arm.com } 21813396Sgiacomo.travaglini@arm.com 21913393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPSR] = cpsr; 22013393Sgiacomo.travaglini@arm.com updateRegMap(cpsr); 22113393Sgiacomo.travaglini@arm.com 22213393Sgiacomo.travaglini@arm.com SCTLR sctlr = 0; 22313393Sgiacomo.travaglini@arm.com sctlr.te = (bool) sctlr_rst.te; 22413393Sgiacomo.travaglini@arm.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 22513393Sgiacomo.travaglini@arm.com sctlr.v = (bool) sctlr_rst.v; 22613393Sgiacomo.travaglini@arm.com sctlr.u = 1; 22713393Sgiacomo.travaglini@arm.com sctlr.xp = 1; 22813393Sgiacomo.travaglini@arm.com sctlr.rao2 = 1; 22913393Sgiacomo.travaglini@arm.com sctlr.rao3 = 1; 23013393Sgiacomo.travaglini@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 23113393Sgiacomo.travaglini@arm.com sctlr.uci = 1; 23213393Sgiacomo.travaglini@arm.com sctlr.dze = 1; 23313393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 23413393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 23513393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_HCPTR] = 0; 23613393Sgiacomo.travaglini@arm.com 2377644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2388147SAli.Saidi@ARM.com 2399385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 2409385SAndreas.Sandberg@arm.com 24110037SARM gem5 Developers if (haveLPAE) { 24210037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 24310037SARM gem5 Developers ttbcr.eae = 0; 24410037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 24510037SARM gem5 Developers // Enforce consistency with system-level settings 24610037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 24710037SARM gem5 Developers } 24810037SARM gem5 Developers 24910037SARM gem5 Developers if (haveSecurity) { 25010037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 25110037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 25210037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 25310037SARM gem5 Developers } else { 25410037SARM gem5 Developers // we're always non-secure 25510037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 25610037SARM gem5 Developers } 2578147SAli.Saidi@ARM.com 2587427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2597427Sgblack@eecs.umich.edu} 2607427Sgblack@eecs.umich.edu 26110037SARM gem5 Developersvoid 26210037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 26310037SARM gem5 Developers{ 26410037SARM gem5 Developers CPSR cpsr = 0; 26513396Sgiacomo.travaglini@arm.com Addr rvbar = system->resetAddr(); 26610037SARM gem5 Developers switch (system->highestEL()) { 26710037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 26810037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 26910037SARM gem5 Developers // value 27010037SARM gem5 Developers case EL3: 27110037SARM gem5 Developers cpsr.mode = MODE_EL3H; 27210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 27310037SARM gem5 Developers break; 27410037SARM gem5 Developers case EL2: 27510037SARM gem5 Developers cpsr.mode = MODE_EL2H; 27610037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 27710037SARM gem5 Developers break; 27810037SARM gem5 Developers case EL1: 27910037SARM gem5 Developers cpsr.mode = MODE_EL1H; 28010037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 28110037SARM gem5 Developers break; 28210037SARM gem5 Developers default: 28310037SARM gem5 Developers panic("Invalid highest implemented exception level"); 28410037SARM gem5 Developers break; 28510037SARM gem5 Developers } 28610037SARM gem5 Developers 28710037SARM gem5 Developers // Initialize rest of CPSR 28810037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 28910037SARM gem5 Developers cpsr.ss = 0; 29010037SARM gem5 Developers cpsr.il = 0; 29110037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 29210037SARM gem5 Developers updateRegMap(cpsr); 29310037SARM gem5 Developers 29410037SARM gem5 Developers // Initialize other control registers 29510037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 29610037SARM gem5 Developers if (haveSecurity) { 29711770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 29810037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 29911574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 30011770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 30111770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 30210037SARM gem5 Developers } else { 30311770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 30411770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 30510037SARM gem5 Developers // Always non-secure 30610037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 30710037SARM gem5 Developers } 30813114Sgiacomo.travaglini@arm.com} 30910037SARM gem5 Developers 31013114Sgiacomo.travaglini@arm.comvoid 31113114Sgiacomo.travaglini@arm.comISA::initID32(const ArmISAParams *p) 31213114Sgiacomo.travaglini@arm.com{ 31313114Sgiacomo.travaglini@arm.com // Initialize configurable default values 31413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR] = p->midr; 31513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 31613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_VPIDR] = p->midr; 31713114Sgiacomo.travaglini@arm.com 31813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 31913114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 32013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 32113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 32213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 32313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 32413114Sgiacomo.travaglini@arm.com 32513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 32613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 32713114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 32813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 32913499Sgiacomo.travaglini@arm.com 33013499Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = insertBits( 33113499Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5], 19, 4, 33213499Sgiacomo.travaglini@arm.com haveCrypto ? 0x1112 : 0x0); 33313114Sgiacomo.travaglini@arm.com} 33413114Sgiacomo.travaglini@arm.com 33513114Sgiacomo.travaglini@arm.comvoid 33613114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p) 33713114Sgiacomo.travaglini@arm.com{ 33810037SARM gem5 Developers // Initialize configurable id registers 33910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 34010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 34110461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 34210461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 34310461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 34410461SAndreas.Sandberg@ARM.com 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 34710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 34810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 34910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 35013116Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 35110037SARM gem5 Developers 35210461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 35310461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 35410461SAndreas.Sandberg@ARM.com 35510461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 35610461SAndreas.Sandberg@ARM.com 35713759Sgiacomo.gabrielli@arm.com // SVE 35813759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64ZFR0_EL1] = 0; // SVEver 0 35913759Sgiacomo.gabrielli@arm.com if (haveSecurity) { 36013759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL3] = sveVL - 1; 36113759Sgiacomo.gabrielli@arm.com } else if (haveVirtualization) { 36213759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL2] = sveVL - 1; 36313759Sgiacomo.gabrielli@arm.com } else { 36413759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ZCR_EL1] = sveVL - 1; 36513759Sgiacomo.gabrielli@arm.com } 36613759Sgiacomo.gabrielli@arm.com 36710037SARM gem5 Developers // Enforce consistency with system-level settings... 36810037SARM gem5 Developers 36910037SARM gem5 Developers // EL3 37010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 37211574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 37310037SARM gem5 Developers // EL2 37410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 37611574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 37713759Sgiacomo.gabrielli@arm.com // SVE 37813759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 37913759Sgiacomo.gabrielli@arm.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 35, 32, 38013759Sgiacomo.gabrielli@arm.com haveSVE ? 0x1 : 0x0); 38110037SARM gem5 Developers // Large ASID support 38210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 38410037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 38510037SARM gem5 Developers // Physical address size 38610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 38710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 38813114Sgiacomo.travaglini@arm.com encodePhysAddrRange64(physAddrRange)); 38913173Sgiacomo.travaglini@arm.com // Crypto 39013173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 39113173Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 39213173Sgiacomo.travaglini@arm.com haveCrypto ? 0x1112 : 0x0); 39310037SARM gem5 Developers} 39410037SARM gem5 Developers 39512972Sandreas.sandberg@arm.comvoid 39612972Sandreas.sandberg@arm.comISA::startup(ThreadContext *tc) 39712972Sandreas.sandberg@arm.com{ 39812972Sandreas.sandberg@arm.com pmu->setThreadContext(tc); 39912972Sandreas.sandberg@arm.com 40013531Sjairo.balart@metempsy.com if (system) { 40113531Sjairo.balart@metempsy.com Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC()); 40213531Sjairo.balart@metempsy.com if (gicv3) { 40313691Sgiacomo.travaglini@arm.com haveGICv3CPUInterface = true; 40413531Sjairo.balart@metempsy.com gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId())); 40513531Sjairo.balart@metempsy.com gicv3CpuInterface->setISA(this); 40613531Sjairo.balart@metempsy.com } 40713531Sjairo.balart@metempsy.com } 40812972Sandreas.sandberg@arm.com} 40912972Sandreas.sandberg@arm.com 41012972Sandreas.sandberg@arm.com 41113581Sgabeblack@google.comRegVal 41210035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 4137405SAli.Saidi@ARM.com{ 4147405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 4157614Sminkyu.jeong@arm.com 41612478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 41712478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 41812478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 41912478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 42012478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 42112478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 42212478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 42312478SCurtis.Dunham@arm.com if (val & reg.res0()) { 42412478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 42512478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 42612478SCurtis.Dunham@arm.com } 42712478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 42812478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 42912478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 43012478SCurtis.Dunham@arm.com } 43112478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 4327405SAli.Saidi@ARM.com} 4337405SAli.Saidi@ARM.com 4347405SAli.Saidi@ARM.com 43513581Sgabeblack@google.comRegVal 4367405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 4377405SAli.Saidi@ARM.com{ 43810037SARM gem5 Developers CPSR cpsr = 0; 43910037SARM gem5 Developers PCState pc = 0; 44010037SARM gem5 Developers SCR scr = 0; 4419050Schander.sudanthi@arm.com 4427405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 44310037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 44410037SARM gem5 Developers pc = tc->pcState(); 4457720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 4467720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 4477405SAli.Saidi@ARM.com return cpsr; 4487405SAli.Saidi@ARM.com } 4497757SAli.Saidi@ARM.com 45010037SARM gem5 Developers#ifndef NDEBUG 45110037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 45210037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 45310037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 45410037SARM gem5 Developers miscRegName[misc_reg]); 45510037SARM gem5 Developers else 45610037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 45710037SARM gem5 Developers miscRegName[misc_reg]); 45810037SARM gem5 Developers } 45910037SARM gem5 Developers#endif 46010037SARM gem5 Developers 46110037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 46210037SARM gem5 Developers case MISCREG_HCR: 46310037SARM gem5 Developers { 46410037SARM gem5 Developers if (!haveVirtualization) 46510037SARM gem5 Developers return 0; 46610037SARM gem5 Developers else 46710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 46810037SARM gem5 Developers } 46910037SARM gem5 Developers case MISCREG_CPACR: 47010037SARM gem5 Developers { 47110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 47210037SARM gem5 Developers CPACR cpacrMask = 0; 47310037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 47410037SARM gem5 Developers // be readable? (straight copy from the write code) 47510037SARM gem5 Developers cpacrMask.cp10 = ones; 47610037SARM gem5 Developers cpacrMask.cp11 = ones; 47710037SARM gem5 Developers cpacrMask.asedis = ones; 47810037SARM gem5 Developers 47910037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 48010037SARM gem5 Developers if (haveSecurity) { 48110037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 48210037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 48312667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 48410037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 48510037SARM gem5 Developers // NB: Skipping the full loop, here 48610037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 48710037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 48810037SARM gem5 Developers } 48910037SARM gem5 Developers } 49013581Sgabeblack@google.com RegVal val = readMiscRegNoEffect(MISCREG_CPACR); 49110037SARM gem5 Developers val &= cpacrMask; 49210037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 49310037SARM gem5 Developers miscRegName[misc_reg], val); 49410037SARM gem5 Developers return val; 49510037SARM gem5 Developers } 4968284SAli.Saidi@ARM.com case MISCREG_MPIDR: 49710037SARM gem5 Developers case MISCREG_MPIDR_EL1: 49813550Sgiacomo.travaglini@arm.com return readMPIDR(system, tc); 49910037SARM gem5 Developers case MISCREG_VMPIDR: 50013550Sgiacomo.travaglini@arm.com case MISCREG_VMPIDR_EL2: 50110037SARM gem5 Developers // top bit defined as RES1 50210037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 50310037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 50410037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 50510037SARM gem5 Developers case MISCREG_MIDR: 50610037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 50710037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 50810037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 50910037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 51010037SARM gem5 Developers } else { 51110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 5129050Schander.sudanthi@arm.com } 5138284SAli.Saidi@ARM.com break; 51410037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 51510037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 51610037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 51710037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 51810037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 51910037SARM gem5 Developers return 0; 52010037SARM gem5 Developers 5217405SAli.Saidi@ARM.com case MISCREG_CLIDR: 5227731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 5238468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 5248468Swade.walker@arm.com "ARM implementations.\n"); 5258468Swade.walker@arm.com return 0x00200000; 5267405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 5277731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 5287405SAli.Saidi@ARM.com "always reads as 0.\n"); 5297405SAli.Saidi@ARM.com break; 53011809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 53111809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 5329130Satgutier@umich.edu { 5339130Satgutier@umich.edu //all caches have the same line size in gem5 5349130Satgutier@umich.edu //4 byte words in ARM 5359130Satgutier@umich.edu unsigned lineSizeWords = 5369814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5379130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 5389130Satgutier@umich.edu 5399130Satgutier@umich.edu while (lineSizeWords >>= 1) { 5409130Satgutier@umich.edu ++log2LineSizeWords; 5419130Satgutier@umich.edu } 5429130Satgutier@umich.edu 5439130Satgutier@umich.edu CTR ctr = 0; 5449130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5459130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5469130Satgutier@umich.edu //b11 - gem5 uses pipt 5479130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5489130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5499130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5509130Satgutier@umich.edu //log2 of max reservation size (words) 5519130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5529130Satgutier@umich.edu //log2 of max writeback size (words) 5539130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5549130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5559130Satgutier@umich.edu ctr.format = 0x4; 5569130Satgutier@umich.edu 5579130Satgutier@umich.edu return ctr; 5589130Satgutier@umich.edu } 5597583SAli.Saidi@arm.com case MISCREG_ACTLR: 5607583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 5617583SAli.Saidi@arm.com break; 56210461SAndreas.Sandberg@ARM.com 56310461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 56410461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 56510461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 56610461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 56710461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 56810461SAndreas.Sandberg@ARM.com 5698302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 5708302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 5717783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 5727783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5737783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5747783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 57510037SARM gem5 Developers case MISCREG_FPSR: 57610037SARM gem5 Developers { 57710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 57810037SARM gem5 Developers FPSCR fpscrMask = 0; 57910037SARM gem5 Developers fpscrMask.ioc = ones; 58010037SARM gem5 Developers fpscrMask.dzc = ones; 58110037SARM gem5 Developers fpscrMask.ofc = ones; 58210037SARM gem5 Developers fpscrMask.ufc = ones; 58310037SARM gem5 Developers fpscrMask.ixc = ones; 58410037SARM gem5 Developers fpscrMask.idc = ones; 58510037SARM gem5 Developers fpscrMask.qc = ones; 58610037SARM gem5 Developers fpscrMask.v = ones; 58710037SARM gem5 Developers fpscrMask.c = ones; 58810037SARM gem5 Developers fpscrMask.z = ones; 58910037SARM gem5 Developers fpscrMask.n = ones; 59010037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 59110037SARM gem5 Developers } 59210037SARM gem5 Developers case MISCREG_FPCR: 59310037SARM gem5 Developers { 59410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 59510037SARM gem5 Developers FPSCR fpscrMask = 0; 59610037SARM gem5 Developers fpscrMask.len = ones; 59713759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 59810037SARM gem5 Developers fpscrMask.stride = ones; 59910037SARM gem5 Developers fpscrMask.rMode = ones; 60010037SARM gem5 Developers fpscrMask.fz = ones; 60110037SARM gem5 Developers fpscrMask.dn = ones; 60210037SARM gem5 Developers fpscrMask.ahp = ones; 60310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 60410037SARM gem5 Developers } 60510037SARM gem5 Developers case MISCREG_NZCV: 60610037SARM gem5 Developers { 60710037SARM gem5 Developers CPSR cpsr = 0; 60810338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 60910338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 61010338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 61110037SARM gem5 Developers return cpsr; 61210037SARM gem5 Developers } 61310037SARM gem5 Developers case MISCREG_DAIF: 61410037SARM gem5 Developers { 61510037SARM gem5 Developers CPSR cpsr = 0; 61610037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 61710037SARM gem5 Developers return cpsr; 61810037SARM gem5 Developers } 61910037SARM gem5 Developers case MISCREG_SP_EL0: 62010037SARM gem5 Developers { 62110037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 62210037SARM gem5 Developers } 62310037SARM gem5 Developers case MISCREG_SP_EL1: 62410037SARM gem5 Developers { 62510037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 62610037SARM gem5 Developers } 62710037SARM gem5 Developers case MISCREG_SP_EL2: 62810037SARM gem5 Developers { 62910037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 63010037SARM gem5 Developers } 63110037SARM gem5 Developers case MISCREG_SPSEL: 63210037SARM gem5 Developers { 63310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 63410037SARM gem5 Developers } 63510037SARM gem5 Developers case MISCREG_CURRENTEL: 63610037SARM gem5 Developers { 63710037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 63810037SARM gem5 Developers } 6398549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6408868SMatt.Horsnell@arm.com { 6418868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 6428868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 6438868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 6448868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 6458868SMatt.Horsnell@arm.com return l2ctlr; 6468868SMatt.Horsnell@arm.com } 6478868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 6488868SMatt.Horsnell@arm.com /* For now just implement the version number. 64910461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 6508868SMatt.Horsnell@arm.com */ 65110461SAndreas.Sandberg@ARM.com return 0x5 << 16; 65210037SARM gem5 Developers case MISCREG_DBGDSCRint: 6538868SMatt.Horsnell@arm.com return 0; 65410037SARM gem5 Developers case MISCREG_ISR: 65511150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 65610037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 65710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 65810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 65910037SARM gem5 Developers case MISCREG_ISR_EL1: 66011150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 66110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 66210037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 66310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 66410037SARM gem5 Developers case MISCREG_DCZID_EL0: 66510037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 66610037SARM gem5 Developers case MISCREG_HCPTR: 66710037SARM gem5 Developers { 66813581Sgabeblack@google.com RegVal val = readMiscRegNoEffect(misc_reg); 66910037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 67010037SARM gem5 Developers val &= ~(1 << 14); 67110037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 67210037SARM gem5 Developers // HCPTR is RAO/WI 67310037SARM gem5 Developers bool secure_lookup = haveSecurity && 67410037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 67510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 67610037SARM gem5 Developers if (!secure_lookup) { 67713581Sgabeblack@google.com RegVal mask = readMiscRegNoEffect(MISCREG_NSACR); 67810037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 67910037SARM gem5 Developers } 68010037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 68110037SARM gem5 Developers val |= 0x33FF; 68210037SARM gem5 Developers return (val); 68310037SARM gem5 Developers } 68410037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 68510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 68610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 68710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 68810844Sandreas.sandberg@arm.com 68911772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 69011772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 69111772SCurtis.Dunham@arm.com return 0x00000031; 69211772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 69311774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 69411774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 69511774SCurtis.Dunham@arm.com return 0x00000001 69611774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 69711774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 69811774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 69911774SCurtis.Dunham@arm.com } 70011773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 70113531Sjairo.balart@metempsy.com return 0x0000000000000002 | // AArch{64,32} supported at EL0 70213531Sjairo.balart@metempsy.com 0x0000000000000020 | // EL1 70313531Sjairo.balart@metempsy.com (haveVirtualization ? 0x0000000000000200 : 0) | // EL2 70413531Sjairo.balart@metempsy.com (haveSecurity ? 0x0000000000002000 : 0) | // EL3 70513759Sgiacomo.gabrielli@arm.com (haveSVE ? 0x0000000100000000 : 0) | // SVE 70613531Sjairo.balart@metempsy.com (haveGICv3CPUInterface ? 0x0000000001000000 : 0); 70711773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 70811773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 70911772SCurtis.Dunham@arm.com 71010037SARM gem5 Developers // Generic Timer registers 71112816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 71212816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 71312816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 71410844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 71510844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 71610844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 71710844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 71810844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 71910844Sandreas.sandberg@arm.com 72013531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 72113531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 72213531Sjairo.balart@metempsy.com return getGICv3CPUInterface(tc).readMiscReg(misc_reg); 72313531Sjairo.balart@metempsy.com 72410188Sgeoffrey.blake@arm.com default: 72510037SARM gem5 Developers break; 72610037SARM gem5 Developers 7277405SAli.Saidi@ARM.com } 7287405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 7297405SAli.Saidi@ARM.com} 7307405SAli.Saidi@ARM.com 7317405SAli.Saidi@ARM.comvoid 73213582Sgabeblack@google.comISA::setMiscRegNoEffect(int misc_reg, RegVal val) 7337405SAli.Saidi@ARM.com{ 7347405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 7357614Sminkyu.jeong@arm.com 73612478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 73712478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 73812478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 73912478SCurtis.Dunham@arm.com 74012478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 74111771SCurtis.Dunham@arm.com if (upper > 0) { 74212478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 74312478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 74410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 74512478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 74610037SARM gem5 Developers } else { 74712478SCurtis.Dunham@arm.com miscRegs[lower] = v; 74810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 74912478SCurtis.Dunham@arm.com misc_reg, lower, v); 75010037SARM gem5 Developers } 7517405SAli.Saidi@ARM.com} 7527405SAli.Saidi@ARM.com 7537405SAli.Saidi@ARM.comvoid 75413582Sgabeblack@google.comISA::setMiscReg(int misc_reg, RegVal val, ThreadContext *tc) 7557405SAli.Saidi@ARM.com{ 7567749SAli.Saidi@ARM.com 75713581Sgabeblack@google.com RegVal newVal = val; 75810037SARM gem5 Developers bool secure_lookup; 75910037SARM gem5 Developers SCR scr; 7608284SAli.Saidi@ARM.com 7617405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7627405SAli.Saidi@ARM.com updateRegMap(val); 7637749SAli.Saidi@ARM.com 7647749SAli.Saidi@ARM.com 7657749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7667749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 7677405SAli.Saidi@ARM.com CPSR cpsr = val; 76812510Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 76912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 77012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 7717749SAli.Saidi@ARM.com } 7727749SAli.Saidi@ARM.com 7737614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7747614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7757720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7767720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 7777720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 77812763Sgiacomo.travaglini@arm.com pc.illegalExec(cpsr.il == 1); 7798887Sgeoffrey.blake@arm.com 78013759Sgiacomo.gabrielli@arm.com tc->getDecoderPtr()->setSveLen((getCurSveVecLenInBits(tc) >> 7) - 1); 78113759Sgiacomo.gabrielli@arm.com 7828887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 7838887Sgeoffrey.blake@arm.com // is connected 7848887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 7858887Sgeoffrey.blake@arm.com if (checker) { 7868887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 7878887Sgeoffrey.blake@arm.com } else { 7888887Sgeoffrey.blake@arm.com tc->pcState(pc); 7898887Sgeoffrey.blake@arm.com } 7907408Sgblack@eecs.umich.edu } else { 79110037SARM gem5 Developers#ifndef NDEBUG 79210037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 79310037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 79410037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 79510037SARM gem5 Developers miscRegName[misc_reg], val); 79610037SARM gem5 Developers else 79710037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 79810037SARM gem5 Developers miscRegName[misc_reg], val); 79910037SARM gem5 Developers } 80010037SARM gem5 Developers#endif 80110037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 8027408Sgblack@eecs.umich.edu case MISCREG_CPACR: 8037408Sgblack@eecs.umich.edu { 8048206SWilliam.Wang@arm.com 8058206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 8068206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 8078206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 8088206SWilliam.Wang@arm.com // be writable 8098206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 8108206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 8118206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 81210037SARM gem5 Developers 81310037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 81410037SARM gem5 Developers if (haveSecurity) { 81510037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 81610037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 81712667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 81810037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 81910037SARM gem5 Developers // NB: Skipping the full loop, here 82010037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 82110037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 82210037SARM gem5 Developers } 82310037SARM gem5 Developers } 82410037SARM gem5 Developers 82513581Sgabeblack@google.com RegVal old_val = readMiscRegNoEffect(MISCREG_CPACR); 8268206SWilliam.Wang@arm.com newVal &= cpacrMask; 82710037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 82810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 82910037SARM gem5 Developers miscRegName[misc_reg], newVal); 83010037SARM gem5 Developers } 83110037SARM gem5 Developers break; 83213759Sgiacomo.gabrielli@arm.com case MISCREG_CPACR_EL1: 83313759Sgiacomo.gabrielli@arm.com { 83413759Sgiacomo.gabrielli@arm.com const uint32_t ones = (uint32_t)(-1); 83513759Sgiacomo.gabrielli@arm.com CPACR cpacrMask = 0; 83613759Sgiacomo.gabrielli@arm.com cpacrMask.tta = ones; 83713759Sgiacomo.gabrielli@arm.com cpacrMask.fpen = ones; 83813759Sgiacomo.gabrielli@arm.com if (haveSVE) { 83913759Sgiacomo.gabrielli@arm.com cpacrMask.zen = ones; 84013759Sgiacomo.gabrielli@arm.com } 84113759Sgiacomo.gabrielli@arm.com newVal &= cpacrMask; 84213759Sgiacomo.gabrielli@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 84313759Sgiacomo.gabrielli@arm.com miscRegName[misc_reg], newVal); 84413759Sgiacomo.gabrielli@arm.com } 84513759Sgiacomo.gabrielli@arm.com break; 84610037SARM gem5 Developers case MISCREG_CPTR_EL2: 84710037SARM gem5 Developers { 84810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 84910037SARM gem5 Developers CPTR cptrMask = 0; 85010037SARM gem5 Developers cptrMask.tcpac = ones; 85110037SARM gem5 Developers cptrMask.tta = ones; 85210037SARM gem5 Developers cptrMask.tfp = ones; 85313759Sgiacomo.gabrielli@arm.com if (haveSVE) { 85413759Sgiacomo.gabrielli@arm.com cptrMask.tz = ones; 85513759Sgiacomo.gabrielli@arm.com } 85610037SARM gem5 Developers newVal &= cptrMask; 85710037SARM gem5 Developers cptrMask = 0; 85810037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 85913759Sgiacomo.gabrielli@arm.com cptrMask.res1_7_0_el2 = ones; 86013759Sgiacomo.gabrielli@arm.com if (!haveSVE) { 86113759Sgiacomo.gabrielli@arm.com cptrMask.res1_8_el2 = ones; 86213759Sgiacomo.gabrielli@arm.com } 86313759Sgiacomo.gabrielli@arm.com cptrMask.res1_9_el2 = ones; 86410037SARM gem5 Developers newVal |= cptrMask; 86510037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 86610037SARM gem5 Developers miscRegName[misc_reg], newVal); 86710037SARM gem5 Developers } 86810037SARM gem5 Developers break; 86910037SARM gem5 Developers case MISCREG_CPTR_EL3: 87010037SARM gem5 Developers { 87110037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87210037SARM gem5 Developers CPTR cptrMask = 0; 87310037SARM gem5 Developers cptrMask.tcpac = ones; 87410037SARM gem5 Developers cptrMask.tta = ones; 87510037SARM gem5 Developers cptrMask.tfp = ones; 87613759Sgiacomo.gabrielli@arm.com if (haveSVE) { 87713759Sgiacomo.gabrielli@arm.com cptrMask.ez = ones; 87813759Sgiacomo.gabrielli@arm.com } 87910037SARM gem5 Developers newVal &= cptrMask; 8808206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8818206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 8827408Sgblack@eecs.umich.edu } 8837408Sgblack@eecs.umich.edu break; 8847408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 8857731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 8868206SWilliam.Wang@arm.com return; 88710037SARM gem5 Developers 88810037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 88910037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 89010037SARM gem5 Developers return; 89110037SARM gem5 Developers 8927408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 8937408Sgblack@eecs.umich.edu { 8947408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8957408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 8967408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8977408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8987408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8997408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 9007408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 9017408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 90210037SARM gem5 Developers fpscrMask.ioe = ones; 90310037SARM gem5 Developers fpscrMask.dze = ones; 90410037SARM gem5 Developers fpscrMask.ofe = ones; 90510037SARM gem5 Developers fpscrMask.ufe = ones; 90610037SARM gem5 Developers fpscrMask.ixe = ones; 90710037SARM gem5 Developers fpscrMask.ide = ones; 9087408Sgblack@eecs.umich.edu fpscrMask.len = ones; 90913759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 9107408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 9117408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 9127408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 9137408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 9147408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 9157408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 9167408Sgblack@eecs.umich.edu fpscrMask.v = ones; 9177408Sgblack@eecs.umich.edu fpscrMask.c = ones; 9187408Sgblack@eecs.umich.edu fpscrMask.z = ones; 9197408Sgblack@eecs.umich.edu fpscrMask.n = ones; 9207408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 92110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 92210037SARM gem5 Developers ~(uint32_t)fpscrMask); 9239377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 9247408Sgblack@eecs.umich.edu } 9257408Sgblack@eecs.umich.edu break; 92610037SARM gem5 Developers case MISCREG_FPSR: 92710037SARM gem5 Developers { 92810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 92910037SARM gem5 Developers FPSCR fpscrMask = 0; 93010037SARM gem5 Developers fpscrMask.ioc = ones; 93110037SARM gem5 Developers fpscrMask.dzc = ones; 93210037SARM gem5 Developers fpscrMask.ofc = ones; 93310037SARM gem5 Developers fpscrMask.ufc = ones; 93410037SARM gem5 Developers fpscrMask.ixc = ones; 93510037SARM gem5 Developers fpscrMask.idc = ones; 93610037SARM gem5 Developers fpscrMask.qc = ones; 93710037SARM gem5 Developers fpscrMask.v = ones; 93810037SARM gem5 Developers fpscrMask.c = ones; 93910037SARM gem5 Developers fpscrMask.z = ones; 94010037SARM gem5 Developers fpscrMask.n = ones; 94110037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 94210037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 94310037SARM gem5 Developers ~(uint32_t)fpscrMask); 94410037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 94510037SARM gem5 Developers } 94610037SARM gem5 Developers break; 94710037SARM gem5 Developers case MISCREG_FPCR: 94810037SARM gem5 Developers { 94910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 95010037SARM gem5 Developers FPSCR fpscrMask = 0; 95110037SARM gem5 Developers fpscrMask.len = ones; 95213759Sgiacomo.gabrielli@arm.com fpscrMask.fz16 = ones; 95310037SARM gem5 Developers fpscrMask.stride = ones; 95410037SARM gem5 Developers fpscrMask.rMode = ones; 95510037SARM gem5 Developers fpscrMask.fz = ones; 95610037SARM gem5 Developers fpscrMask.dn = ones; 95710037SARM gem5 Developers fpscrMask.ahp = ones; 95810037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 95910037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 96010037SARM gem5 Developers ~(uint32_t)fpscrMask); 96110037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 96210037SARM gem5 Developers } 96310037SARM gem5 Developers break; 9648302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 9658302SAli.Saidi@ARM.com { 9668302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 96710037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 9688302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 9698302SAli.Saidi@ARM.com } 9708302SAli.Saidi@ARM.com break; 9717783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 9727783SGiacomo.Gabrielli@arm.com { 97310037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 97410037SARM gem5 Developers (newVal & FpscrQcMask); 9757783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9767783SGiacomo.Gabrielli@arm.com } 9777783SGiacomo.Gabrielli@arm.com break; 9787783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 9797783SGiacomo.Gabrielli@arm.com { 98010037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 98110037SARM gem5 Developers (newVal & FpscrExcMask); 9827783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9837783SGiacomo.Gabrielli@arm.com } 9847783SGiacomo.Gabrielli@arm.com break; 9857408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 9867408Sgblack@eecs.umich.edu { 9878206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 9888206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 9897408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 9907408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 99110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 9927408Sgblack@eecs.umich.edu } 9937408Sgblack@eecs.umich.edu break; 99410037SARM gem5 Developers case MISCREG_HCR: 99510037SARM gem5 Developers { 99610037SARM gem5 Developers if (!haveVirtualization) 99710037SARM gem5 Developers return; 99810037SARM gem5 Developers } 99910037SARM gem5 Developers break; 100010037SARM gem5 Developers case MISCREG_IFSR: 100110037SARM gem5 Developers { 100210037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 100310037SARM gem5 Developers const uint32_t ifsrMask = 100410037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 100510037SARM gem5 Developers newVal = newVal & ~ifsrMask; 100610037SARM gem5 Developers } 100710037SARM gem5 Developers break; 100810037SARM gem5 Developers case MISCREG_DFSR: 100910037SARM gem5 Developers { 101010037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 101110037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 101210037SARM gem5 Developers newVal = newVal & ~dfsrMask; 101310037SARM gem5 Developers } 101410037SARM gem5 Developers break; 101510037SARM gem5 Developers case MISCREG_AMAIR0: 101610037SARM gem5 Developers case MISCREG_AMAIR1: 101710037SARM gem5 Developers { 101810037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 101910037SARM gem5 Developers // Valid only with LPAE 102010037SARM gem5 Developers if (!haveLPAE) 102110037SARM gem5 Developers return; 102210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 102310037SARM gem5 Developers } 102410037SARM gem5 Developers break; 102510037SARM gem5 Developers case MISCREG_SCR: 102612406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 102712406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 102810037SARM gem5 Developers break; 10297408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 10307408Sgblack@eecs.umich.edu { 10317408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 103210037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 103312639Sgiacomo.travaglini@arm.com 103412639Sgiacomo.travaglini@arm.com MiscRegIndex sctlr_idx; 103512639Sgiacomo.travaglini@arm.com if (haveSecurity && !highestELIs64 && !scr.ns) { 103612639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_S; 103712639Sgiacomo.travaglini@arm.com } else { 103812639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_NS; 103912639Sgiacomo.travaglini@arm.com } 104012639Sgiacomo.travaglini@arm.com 104110037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 10427408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 104310037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 104413581Sgabeblack@google.com miscRegs[sctlr_idx] = (RegVal)new_sctlr; 104512406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 104612406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 10477408Sgblack@eecs.umich.edu } 10489385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 10499385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 10509385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 105110461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 10529385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 10539385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 10549385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 10559385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 10569385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 10579385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 10589385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 10599385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 10609385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 10619385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 10629385SAndreas.Sandberg@arm.com 10639385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 10649385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 10657408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 10667408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 10677408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 106810037SARM gem5 Developers 106910037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 107010037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 107110037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 107210037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 107310037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 107410037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 107510037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 107610037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 107713116Sgiacomo.travaglini@arm.com case MISCREG_ID_AA64MMFR2_EL1: 107810037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 107910037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 10809385SAndreas.Sandberg@arm.com // ID registers are constants. 10817408Sgblack@eecs.umich.edu return; 10829385SAndreas.Sandberg@arm.com 108312605Sgiacomo.travaglini@arm.com // TLB Invalidate All 108412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 108512605Sgiacomo.travaglini@arm.com { 108612605Sgiacomo.travaglini@arm.com assert32(tc); 108712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 108812605Sgiacomo.travaglini@arm.com 108912605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 109012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 109112605Sgiacomo.travaglini@arm.com return; 109212605Sgiacomo.travaglini@arm.com } 109312605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 10947408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 109512605Sgiacomo.travaglini@arm.com { 109612605Sgiacomo.travaglini@arm.com assert32(tc); 109712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 109812605Sgiacomo.travaglini@arm.com 109912605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 110012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 110112605Sgiacomo.travaglini@arm.com return; 110212605Sgiacomo.travaglini@arm.com } 110312605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 11047408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 110512605Sgiacomo.travaglini@arm.com { 110612605Sgiacomo.travaglini@arm.com assert32(tc); 110712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 110812605Sgiacomo.travaglini@arm.com 110912605Sgiacomo.travaglini@arm.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 111012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 111112605Sgiacomo.travaglini@arm.com return; 111212605Sgiacomo.travaglini@arm.com } 111312605Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 11147408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 111512605Sgiacomo.travaglini@arm.com { 111612605Sgiacomo.travaglini@arm.com assert32(tc); 111712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 111812605Sgiacomo.travaglini@arm.com 111912605Sgiacomo.travaglini@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 112012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 112112605Sgiacomo.travaglini@arm.com return; 112212605Sgiacomo.travaglini@arm.com } 112312605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA 112412605Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 112512605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 112612605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 112712605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 112812576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 112912605Sgiacomo.travaglini@arm.com { 113012605Sgiacomo.travaglini@arm.com assert32(tc); 113112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 113212605Sgiacomo.travaglini@arm.com 113312605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 113412605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 113512605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 113612605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 113712605Sgiacomo.travaglini@arm.com 113812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 113912605Sgiacomo.travaglini@arm.com return; 114012605Sgiacomo.travaglini@arm.com } 114112605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Inner Shareable 114212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAIS: 114312576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 114412605Sgiacomo.travaglini@arm.com { 114512605Sgiacomo.travaglini@arm.com assert32(tc); 114612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 114712605Sgiacomo.travaglini@arm.com 114812605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 114912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 115012605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 115112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 115212605Sgiacomo.travaglini@arm.com 115312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 115412605Sgiacomo.travaglini@arm.com return; 115512605Sgiacomo.travaglini@arm.com } 115612605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match 115712605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASID: 115812605Sgiacomo.travaglini@arm.com { 115912605Sgiacomo.travaglini@arm.com assert32(tc); 116012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 116112605Sgiacomo.travaglini@arm.com 116212605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 116312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 116412605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 116512605Sgiacomo.travaglini@arm.com 116612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 116712605Sgiacomo.travaglini@arm.com return; 116812605Sgiacomo.travaglini@arm.com } 116912605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match, Inner Shareable 11707408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 117112605Sgiacomo.travaglini@arm.com { 117212605Sgiacomo.travaglini@arm.com assert32(tc); 117312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 117412605Sgiacomo.travaglini@arm.com 117512605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 117612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 117712605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 117812605Sgiacomo.travaglini@arm.com 117912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 118012605Sgiacomo.travaglini@arm.com return; 118112605Sgiacomo.travaglini@arm.com } 118212605Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 118312605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 118412605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 118512605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID 118612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 118712576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 118812605Sgiacomo.travaglini@arm.com { 118912605Sgiacomo.travaglini@arm.com assert32(tc); 119012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 119112605Sgiacomo.travaglini@arm.com 119212605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 119312605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 119412605Sgiacomo.travaglini@arm.com 119512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 119612605Sgiacomo.travaglini@arm.com return; 119712605Sgiacomo.travaglini@arm.com } 119812605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 119912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAIS: 120012576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 120112605Sgiacomo.travaglini@arm.com { 120212605Sgiacomo.travaglini@arm.com assert32(tc); 120312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 120412605Sgiacomo.travaglini@arm.com 120512605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 120612605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 120712605Sgiacomo.travaglini@arm.com 120812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 120912605Sgiacomo.travaglini@arm.com return; 121012605Sgiacomo.travaglini@arm.com } 121112605Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 121212605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 121312605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 121412605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode 121512605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAH: 121612576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 121712605Sgiacomo.travaglini@arm.com { 121812605Sgiacomo.travaglini@arm.com assert32(tc); 121912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 122012605Sgiacomo.travaglini@arm.com 122112605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 122212605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 122312605Sgiacomo.travaglini@arm.com 122412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 122512605Sgiacomo.travaglini@arm.com return; 122612605Sgiacomo.travaglini@arm.com } 122712605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode, Inner Shareable 122812605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAHIS: 122912576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 123012605Sgiacomo.travaglini@arm.com { 123112605Sgiacomo.travaglini@arm.com assert32(tc); 123212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 123312605Sgiacomo.travaglini@arm.com 123412605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 123512605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 123612605Sgiacomo.travaglini@arm.com 123712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 123812605Sgiacomo.travaglini@arm.com return; 123912605Sgiacomo.travaglini@arm.com } 124012605Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 124112605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 124212605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 124312605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2 124412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 124512577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 124612605Sgiacomo.travaglini@arm.com { 124712605Sgiacomo.travaglini@arm.com assert32(tc); 124812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 124912605Sgiacomo.travaglini@arm.com 125012605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 125112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 125212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 125312605Sgiacomo.travaglini@arm.com 125412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 125512605Sgiacomo.travaglini@arm.com return; 125612605Sgiacomo.travaglini@arm.com } 125712605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2, 125812605Sgiacomo.travaglini@arm.com // Inner Shareable 125912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 126012577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 126112605Sgiacomo.travaglini@arm.com { 126212605Sgiacomo.travaglini@arm.com assert32(tc); 126312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 126412605Sgiacomo.travaglini@arm.com 126512605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 126612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 126712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 126812605Sgiacomo.travaglini@arm.com 126912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 127012605Sgiacomo.travaglini@arm.com return; 127112605Sgiacomo.travaglini@arm.com } 127212605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by VA 127310037SARM gem5 Developers case MISCREG_ITLBIMVA: 127412605Sgiacomo.travaglini@arm.com { 127512605Sgiacomo.travaglini@arm.com assert32(tc); 127612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 127712605Sgiacomo.travaglini@arm.com 127812605Sgiacomo.travaglini@arm.com ITLBIMVA tlbiOp(EL1, 127912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 128012605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 128112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 128212605Sgiacomo.travaglini@arm.com 128312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 128412605Sgiacomo.travaglini@arm.com return; 128512605Sgiacomo.travaglini@arm.com } 128612605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by VA 128710037SARM gem5 Developers case MISCREG_DTLBIMVA: 128812605Sgiacomo.travaglini@arm.com { 128912605Sgiacomo.travaglini@arm.com assert32(tc); 129012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 129112605Sgiacomo.travaglini@arm.com 129212605Sgiacomo.travaglini@arm.com DTLBIMVA tlbiOp(EL1, 129312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 129412605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 129512605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 129612605Sgiacomo.travaglini@arm.com 129712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 129812605Sgiacomo.travaglini@arm.com return; 129912605Sgiacomo.travaglini@arm.com } 130012605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by ASID match 130110037SARM gem5 Developers case MISCREG_ITLBIASID: 130212605Sgiacomo.travaglini@arm.com { 130312605Sgiacomo.travaglini@arm.com assert32(tc); 130412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 130512605Sgiacomo.travaglini@arm.com 130612605Sgiacomo.travaglini@arm.com ITLBIASID tlbiOp(EL1, 130712605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 130812605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 130912605Sgiacomo.travaglini@arm.com 131012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 131112605Sgiacomo.travaglini@arm.com return; 131212605Sgiacomo.travaglini@arm.com } 131312605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by ASID match 131410037SARM gem5 Developers case MISCREG_DTLBIASID: 131512605Sgiacomo.travaglini@arm.com { 131612605Sgiacomo.travaglini@arm.com assert32(tc); 131712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 131812605Sgiacomo.travaglini@arm.com 131912605Sgiacomo.travaglini@arm.com DTLBIASID tlbiOp(EL1, 132012605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 132112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 132212605Sgiacomo.travaglini@arm.com 132312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 132412605Sgiacomo.travaglini@arm.com return; 132512605Sgiacomo.travaglini@arm.com } 132612605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp 132710037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 132812605Sgiacomo.travaglini@arm.com { 132912605Sgiacomo.travaglini@arm.com assert32(tc); 133012605Sgiacomo.travaglini@arm.com 133112605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 133212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 133312605Sgiacomo.travaglini@arm.com return; 133412605Sgiacomo.travaglini@arm.com } 133512605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 133610037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 133712605Sgiacomo.travaglini@arm.com { 133812605Sgiacomo.travaglini@arm.com assert32(tc); 133912605Sgiacomo.travaglini@arm.com 134012605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 134112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 134212605Sgiacomo.travaglini@arm.com return; 134312605Sgiacomo.travaglini@arm.com } 134412605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode 134510037SARM gem5 Developers case MISCREG_TLBIALLH: 134612605Sgiacomo.travaglini@arm.com { 134712605Sgiacomo.travaglini@arm.com assert32(tc); 134812605Sgiacomo.travaglini@arm.com 134912605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 135012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 135112605Sgiacomo.travaglini@arm.com return; 135212605Sgiacomo.travaglini@arm.com } 135312605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode, Inner Shareable 135410037SARM gem5 Developers case MISCREG_TLBIALLHIS: 135512605Sgiacomo.travaglini@arm.com { 135612605Sgiacomo.travaglini@arm.com assert32(tc); 135712605Sgiacomo.travaglini@arm.com 135812605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 135912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 136012605Sgiacomo.travaglini@arm.com return; 136112605Sgiacomo.travaglini@arm.com } 136212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3 136312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3: 136412605Sgiacomo.travaglini@arm.com { 136512605Sgiacomo.travaglini@arm.com assert64(tc); 136612605Sgiacomo.travaglini@arm.com 136712605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 136812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 136912605Sgiacomo.travaglini@arm.com return; 137012605Sgiacomo.travaglini@arm.com } 137112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3, Inner Shareable 137210037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 137312605Sgiacomo.travaglini@arm.com { 137412605Sgiacomo.travaglini@arm.com assert64(tc); 137512605Sgiacomo.travaglini@arm.com 137612605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 137712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 137812605Sgiacomo.travaglini@arm.com return; 137912605Sgiacomo.travaglini@arm.com } 138013549Sanouk.vanlaer@arm.com // AArch64 TLB Invalidate All, EL2, Inner Shareable 138113549Sanouk.vanlaer@arm.com case MISCREG_TLBI_ALLE2: 138213549Sanouk.vanlaer@arm.com case MISCREG_TLBI_ALLE2IS: 138313549Sanouk.vanlaer@arm.com { 138413549Sanouk.vanlaer@arm.com assert64(tc); 138513549Sanouk.vanlaer@arm.com scr = readMiscReg(MISCREG_SCR, tc); 138613549Sanouk.vanlaer@arm.com 138713549Sanouk.vanlaer@arm.com TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns); 138813549Sanouk.vanlaer@arm.com tlbiOp(tc); 138913549Sanouk.vanlaer@arm.com return; 139013549Sanouk.vanlaer@arm.com } 139112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1 139210037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 139310037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 139410037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 139510037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 139612605Sgiacomo.travaglini@arm.com { 139712605Sgiacomo.travaglini@arm.com assert64(tc); 139812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 139912605Sgiacomo.travaglini@arm.com 140012605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 140112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 140212605Sgiacomo.travaglini@arm.com return; 140312605Sgiacomo.travaglini@arm.com } 140412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 140512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE1IS: 140612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 140712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLS12E1IS: 140812605Sgiacomo.travaglini@arm.com // @todo: handle VMID and stage 2 to enable Virtualization 140912605Sgiacomo.travaglini@arm.com { 141012605Sgiacomo.travaglini@arm.com assert64(tc); 141112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 141212605Sgiacomo.travaglini@arm.com 141312605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 141412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 141512605Sgiacomo.travaglini@arm.com return; 141612605Sgiacomo.travaglini@arm.com } 141712605Sgiacomo.travaglini@arm.com // VAEx(IS) and VALEx(IS) are the same because TLBs 141812605Sgiacomo.travaglini@arm.com // only store entries 141910037SARM gem5 Developers // from the last level of translation table walks 142010037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 142112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3 142212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE3_Xt: 142312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE3_Xt: 142412605Sgiacomo.travaglini@arm.com { 142512605Sgiacomo.travaglini@arm.com assert64(tc); 142612605Sgiacomo.travaglini@arm.com 142712605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 142812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 142912605Sgiacomo.travaglini@arm.com 0xbeef); 143012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 143112605Sgiacomo.travaglini@arm.com return; 143212605Sgiacomo.travaglini@arm.com } 143312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 143410037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 143510037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 143612605Sgiacomo.travaglini@arm.com { 143712605Sgiacomo.travaglini@arm.com assert64(tc); 143812605Sgiacomo.travaglini@arm.com 143912605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 144012605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 144112605Sgiacomo.travaglini@arm.com 0xbeef); 144212605Sgiacomo.travaglini@arm.com 144312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 144412605Sgiacomo.travaglini@arm.com return; 144512605Sgiacomo.travaglini@arm.com } 144612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2 144712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2_Xt: 144812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2_Xt: 144912605Sgiacomo.travaglini@arm.com { 145012605Sgiacomo.travaglini@arm.com assert64(tc); 145112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 145212605Sgiacomo.travaglini@arm.com 145312605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 145412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 145512605Sgiacomo.travaglini@arm.com 0xbeef); 145612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 145712605Sgiacomo.travaglini@arm.com return; 145812605Sgiacomo.travaglini@arm.com } 145912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 146010037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 146110037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 146212605Sgiacomo.travaglini@arm.com { 146312605Sgiacomo.travaglini@arm.com assert64(tc); 146412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 146512605Sgiacomo.travaglini@arm.com 146612605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 146712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 146812605Sgiacomo.travaglini@arm.com 0xbeef); 146912605Sgiacomo.travaglini@arm.com 147012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 147112605Sgiacomo.travaglini@arm.com return; 147212605Sgiacomo.travaglini@arm.com } 147312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1 147412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 147512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1_Xt: 147612605Sgiacomo.travaglini@arm.com { 147712605Sgiacomo.travaglini@arm.com assert64(tc); 147812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147912605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 148012605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 148112605Sgiacomo.travaglini@arm.com 148212605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 148312605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 148412605Sgiacomo.travaglini@arm.com asid); 148512605Sgiacomo.travaglini@arm.com 148612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 148712605Sgiacomo.travaglini@arm.com return; 148812605Sgiacomo.travaglini@arm.com } 148912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 149010037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 149110037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 149212605Sgiacomo.travaglini@arm.com { 149312605Sgiacomo.travaglini@arm.com assert64(tc); 149412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 149512605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 149612605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 149712605Sgiacomo.travaglini@arm.com 149812605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 149912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 150012605Sgiacomo.travaglini@arm.com asid); 150112605Sgiacomo.travaglini@arm.com 150212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 150312605Sgiacomo.travaglini@arm.com return; 150412605Sgiacomo.travaglini@arm.com } 150512605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1 150610037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 150712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 150812605Sgiacomo.travaglini@arm.com { 150912605Sgiacomo.travaglini@arm.com assert64(tc); 151012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 151112605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 151212605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 151312605Sgiacomo.travaglini@arm.com 151412605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 151512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 151612605Sgiacomo.travaglini@arm.com return; 151712605Sgiacomo.travaglini@arm.com } 151812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 151910037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 152012605Sgiacomo.travaglini@arm.com { 152112605Sgiacomo.travaglini@arm.com assert64(tc); 152212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 152312605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 152412605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 152512605Sgiacomo.travaglini@arm.com 152612605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 152712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 152812605Sgiacomo.travaglini@arm.com return; 152912605Sgiacomo.travaglini@arm.com } 153010037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 153110037SARM gem5 Developers // entries from the last level of translation table walks 153212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 153312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 153412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1_Xt: 153512605Sgiacomo.travaglini@arm.com { 153612605Sgiacomo.travaglini@arm.com assert64(tc); 153712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 153812605Sgiacomo.travaglini@arm.com 153912605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 154012605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 154112605Sgiacomo.travaglini@arm.com 154212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 154312605Sgiacomo.travaglini@arm.com return; 154412605Sgiacomo.travaglini@arm.com } 154512605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 154610037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 154710037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 154812605Sgiacomo.travaglini@arm.com { 154912605Sgiacomo.travaglini@arm.com assert64(tc); 155012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 155112605Sgiacomo.travaglini@arm.com 155212605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 155312605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 155412605Sgiacomo.travaglini@arm.com 155512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 155612605Sgiacomo.travaglini@arm.com return; 155712605Sgiacomo.travaglini@arm.com } 155812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 155912605Sgiacomo.travaglini@arm.com // Stage 2, EL1 156012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1_Xt: 156112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2LE1_Xt: 156212605Sgiacomo.travaglini@arm.com { 156312605Sgiacomo.travaglini@arm.com assert64(tc); 156412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 156512605Sgiacomo.travaglini@arm.com 156612605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 156712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 156812605Sgiacomo.travaglini@arm.com 156912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 157012605Sgiacomo.travaglini@arm.com return; 157112605Sgiacomo.travaglini@arm.com } 157212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 157312605Sgiacomo.travaglini@arm.com // Stage 2, EL1, Inner Shareable 157412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1IS_Xt: 157510037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 157612605Sgiacomo.travaglini@arm.com { 157712605Sgiacomo.travaglini@arm.com assert64(tc); 157812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 157912605Sgiacomo.travaglini@arm.com 158012605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 158112605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 158212605Sgiacomo.travaglini@arm.com 158312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 158412605Sgiacomo.travaglini@arm.com return; 158512605Sgiacomo.travaglini@arm.com } 15867583SAli.Saidi@arm.com case MISCREG_ACTLR: 15877583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 15887583SAli.Saidi@arm.com break; 158910461SAndreas.Sandberg@ARM.com 159010461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 159110461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 159210461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 159310461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 159410461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 15957583SAli.Saidi@arm.com break; 159610461SAndreas.Sandberg@ARM.com 159710461SAndreas.Sandberg@ARM.com 159810037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 159910037SARM gem5 Developers { 160010037SARM gem5 Developers HSTR hstrMask = 0; 160110037SARM gem5 Developers hstrMask.tjdbx = 1; 160210037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 160310037SARM gem5 Developers break; 160410037SARM gem5 Developers } 160510037SARM gem5 Developers case MISCREG_HCPTR: 160610037SARM gem5 Developers { 160710037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 160810037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 160910037SARM gem5 Developers secure_lookup = haveSecurity && 161010037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 161110037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 161210037SARM gem5 Developers if (!secure_lookup) { 161313581Sgabeblack@google.com RegVal oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 161413581Sgabeblack@google.com RegVal mask = 161513581Sgabeblack@google.com (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 161610037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 161710037SARM gem5 Developers } 161810037SARM gem5 Developers break; 161910037SARM gem5 Developers } 162010037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 162110037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 162210037SARM gem5 Developers break; 162310037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 162410037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 162510037SARM gem5 Developers break; 162610037SARM gem5 Developers case MISCREG_ATS1CPR: 162710037SARM gem5 Developers case MISCREG_ATS1CPW: 162810037SARM gem5 Developers case MISCREG_ATS1CUR: 162910037SARM gem5 Developers case MISCREG_ATS1CUW: 163010037SARM gem5 Developers case MISCREG_ATS12NSOPR: 163110037SARM gem5 Developers case MISCREG_ATS12NSOPW: 163210037SARM gem5 Developers case MISCREG_ATS12NSOUR: 163310037SARM gem5 Developers case MISCREG_ATS12NSOUW: 163410037SARM gem5 Developers case MISCREG_ATS1HR: 163510037SARM gem5 Developers case MISCREG_ATS1HW: 16367436Sdam.sunwoo@arm.com { 163711608Snikos.nikoleris@arm.com Request::Flags flags = 0; 163810037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 163910037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 16407436Sdam.sunwoo@arm.com Fault fault; 16417436Sdam.sunwoo@arm.com switch(misc_reg) { 164210037SARM gem5 Developers case MISCREG_ATS1CPR: 164310037SARM gem5 Developers flags = TLB::MustBeOne; 164410037SARM gem5 Developers tranType = TLB::S1CTran; 164510037SARM gem5 Developers mode = BaseTLB::Read; 164610037SARM gem5 Developers break; 164710037SARM gem5 Developers case MISCREG_ATS1CPW: 164810037SARM gem5 Developers flags = TLB::MustBeOne; 164910037SARM gem5 Developers tranType = TLB::S1CTran; 165010037SARM gem5 Developers mode = BaseTLB::Write; 165110037SARM gem5 Developers break; 165210037SARM gem5 Developers case MISCREG_ATS1CUR: 165310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 165410037SARM gem5 Developers tranType = TLB::S1CTran; 165510037SARM gem5 Developers mode = BaseTLB::Read; 165610037SARM gem5 Developers break; 165710037SARM gem5 Developers case MISCREG_ATS1CUW: 165810037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 165910037SARM gem5 Developers tranType = TLB::S1CTran; 166010037SARM gem5 Developers mode = BaseTLB::Write; 166110037SARM gem5 Developers break; 166210037SARM gem5 Developers case MISCREG_ATS12NSOPR: 166310037SARM gem5 Developers if (!haveSecurity) 166410037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 166510037SARM gem5 Developers flags = TLB::MustBeOne; 166610037SARM gem5 Developers tranType = TLB::S1S2NsTran; 166710037SARM gem5 Developers mode = BaseTLB::Read; 166810037SARM gem5 Developers break; 166910037SARM gem5 Developers case MISCREG_ATS12NSOPW: 167010037SARM gem5 Developers if (!haveSecurity) 167110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 167210037SARM gem5 Developers flags = TLB::MustBeOne; 167310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 167410037SARM gem5 Developers mode = BaseTLB::Write; 167510037SARM gem5 Developers break; 167610037SARM gem5 Developers case MISCREG_ATS12NSOUR: 167710037SARM gem5 Developers if (!haveSecurity) 167810037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 167910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168010037SARM gem5 Developers tranType = TLB::S1S2NsTran; 168110037SARM gem5 Developers mode = BaseTLB::Read; 168210037SARM gem5 Developers break; 168310037SARM gem5 Developers case MISCREG_ATS12NSOUW: 168410037SARM gem5 Developers if (!haveSecurity) 168510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 168610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 168710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 168810037SARM gem5 Developers mode = BaseTLB::Write; 168910037SARM gem5 Developers break; 169010037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 169110037SARM gem5 Developers flags = TLB::MustBeOne; 169210037SARM gem5 Developers tranType = TLB::HypMode; 169310037SARM gem5 Developers mode = BaseTLB::Read; 169410037SARM gem5 Developers break; 169510037SARM gem5 Developers case MISCREG_ATS1HW: 169610037SARM gem5 Developers flags = TLB::MustBeOne; 169710037SARM gem5 Developers tranType = TLB::HypMode; 169810037SARM gem5 Developers mode = BaseTLB::Write; 169910037SARM gem5 Developers break; 17007436Sdam.sunwoo@arm.com } 170110037SARM gem5 Developers // If we're in timing mode then doing the translation in 170210037SARM gem5 Developers // functional mode then we're slightly distorting performance 170310037SARM gem5 Developers // results obtained from simulations. The translation should be 170410037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 170510037SARM gem5 Developers // can't be an atomic translation because that causes problems 170610037SARM gem5 Developers // with unexpected atomic snoop requests. 170713417Sgiacomo.travaglini@arm.com warn("Translating via %s in functional mode! Fix Me!\n", 170813417Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 170912749Sgiacomo.travaglini@arm.com 171012749Sgiacomo.travaglini@arm.com auto req = std::make_shared<Request>( 171112749Sgiacomo.travaglini@arm.com 0, val, 0, flags, Request::funcMasterId, 171212749Sgiacomo.travaglini@arm.com tc->pcState().pc(), tc->contextId()); 171312749Sgiacomo.travaglini@arm.com 171412406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 171512749Sgiacomo.travaglini@arm.com req, tc, mode, tranType); 171612749Sgiacomo.travaglini@arm.com 171710037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 171810037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 171910037SARM gem5 Developers 172013581Sgabeblack@google.com RegVal newVal; 17217436Sdam.sunwoo@arm.com if (fault == NoFault) { 172212749Sgiacomo.travaglini@arm.com Addr paddr = req->getPaddr(); 172310037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 172410037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 172510037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 172612406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 172710037SARM gem5 Developers } else { 172810037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 172912406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 173010037SARM gem5 Developers } 17317436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 17327436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 173310037SARM gem5 Developers val, newVal); 173410037SARM gem5 Developers } else { 173512524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 173612570Sgiacomo.travaglini@arm.com armFault->update(tc); 173710037SARM gem5 Developers // Set fault bit and FSR 173810037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 173910037SARM gem5 Developers 174010037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 174110037SARM gem5 Developers if (newVal) { 174210037SARM gem5 Developers // LPAE - rearange fault status 174310037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 174410037SARM gem5 Developers } else { 174510037SARM gem5 Developers // VMSA - rearange fault status 174610037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 174710037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 174810037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 174910037SARM gem5 Developers } 175010037SARM gem5 Developers newVal |= 0x1; // F bit 175110037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 175210037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 175310037SARM gem5 Developers DPRINTF(MiscRegs, 175410037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 175510037SARM gem5 Developers val, fsr, newVal); 17567436Sdam.sunwoo@arm.com } 175710037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 17587436Sdam.sunwoo@arm.com return; 17597436Sdam.sunwoo@arm.com } 176010037SARM gem5 Developers case MISCREG_TTBCR: 176110037SARM gem5 Developers { 176210037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 176310037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 176410037SARM gem5 Developers TTBCR ttbcrMask = 0; 176510037SARM gem5 Developers TTBCR ttbcrNew = newVal; 176610037SARM gem5 Developers 176710037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 176810037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 176910037SARM gem5 Developers if (haveSecurity) { 177010037SARM gem5 Developers ttbcrMask.pd0 = ones; 177110037SARM gem5 Developers ttbcrMask.pd1 = ones; 177210037SARM gem5 Developers } 177310037SARM gem5 Developers ttbcrMask.epd0 = ones; 177410037SARM gem5 Developers ttbcrMask.irgn0 = ones; 177510037SARM gem5 Developers ttbcrMask.orgn0 = ones; 177610037SARM gem5 Developers ttbcrMask.sh0 = ones; 177710037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 177810037SARM gem5 Developers ttbcrMask.a1 = ones; 177910037SARM gem5 Developers ttbcrMask.epd1 = ones; 178010037SARM gem5 Developers ttbcrMask.irgn1 = ones; 178110037SARM gem5 Developers ttbcrMask.orgn1 = ones; 178210037SARM gem5 Developers ttbcrMask.sh1 = ones; 178310037SARM gem5 Developers if (haveLPAE) 178410037SARM gem5 Developers ttbcrMask.eae = ones; 178510037SARM gem5 Developers 178610037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 178710037SARM gem5 Developers newVal = newVal & ttbcrMask; 178810037SARM gem5 Developers } else { 178910037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 179010037SARM gem5 Developers } 179112666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 179212666Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 179312666Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 179412666Sgiacomo.travaglini@arm.com break; 179510037SARM gem5 Developers } 179610037SARM gem5 Developers case MISCREG_TTBR0: 179710037SARM gem5 Developers case MISCREG_TTBR1: 179810037SARM gem5 Developers { 179910037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 180010037SARM gem5 Developers if (haveLPAE) { 180110037SARM gem5 Developers if (ttbcr.eae) { 180210037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 180310037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 180410037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 180510037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 180610037SARM gem5 Developers } 180710037SARM gem5 Developers } 180812666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 180912406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 181012406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 181112666Sgiacomo.travaglini@arm.com break; 181210508SAli.Saidi@ARM.com } 181312666Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL1: 18147749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 18157749SAli.Saidi@ARM.com case MISCREG_PRRR: 18167749SAli.Saidi@ARM.com case MISCREG_NMRR: 181710037SARM gem5 Developers case MISCREG_MAIR0: 181810037SARM gem5 Developers case MISCREG_MAIR1: 18197749SAli.Saidi@ARM.com case MISCREG_DACR: 182010037SARM gem5 Developers case MISCREG_VTTBR: 182110037SARM gem5 Developers case MISCREG_SCR_EL3: 182211575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 182310037SARM gem5 Developers case MISCREG_TCR_EL1: 182410037SARM gem5 Developers case MISCREG_TCR_EL2: 182510037SARM gem5 Developers case MISCREG_TCR_EL3: 182610508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 182710508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 182811573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 182910037SARM gem5 Developers case MISCREG_TTBR0_EL1: 183010037SARM gem5 Developers case MISCREG_TTBR1_EL1: 183110037SARM gem5 Developers case MISCREG_TTBR0_EL2: 183212675Sgiacomo.travaglini@arm.com case MISCREG_TTBR1_EL2: 183310037SARM gem5 Developers case MISCREG_TTBR0_EL3: 183412406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 183512406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 18367749SAli.Saidi@ARM.com break; 183710037SARM gem5 Developers case MISCREG_NZCV: 183810037SARM gem5 Developers { 183910037SARM gem5 Developers CPSR cpsr = val; 184010037SARM gem5 Developers 184110338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 184210338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 184310338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 184410037SARM gem5 Developers } 184510037SARM gem5 Developers break; 184610037SARM gem5 Developers case MISCREG_DAIF: 184710037SARM gem5 Developers { 184810037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 184910037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 185010037SARM gem5 Developers newVal = cpsr; 185110037SARM gem5 Developers misc_reg = MISCREG_CPSR; 185210037SARM gem5 Developers } 185310037SARM gem5 Developers break; 185410037SARM gem5 Developers case MISCREG_SP_EL0: 185510037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 185610037SARM gem5 Developers break; 185710037SARM gem5 Developers case MISCREG_SP_EL1: 185810037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 185910037SARM gem5 Developers break; 186010037SARM gem5 Developers case MISCREG_SP_EL2: 186110037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 186210037SARM gem5 Developers break; 186310037SARM gem5 Developers case MISCREG_SPSEL: 186410037SARM gem5 Developers { 186510037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 186610037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 186710037SARM gem5 Developers newVal = cpsr; 186810037SARM gem5 Developers misc_reg = MISCREG_CPSR; 186910037SARM gem5 Developers } 187010037SARM gem5 Developers break; 187110037SARM gem5 Developers case MISCREG_CURRENTEL: 187210037SARM gem5 Developers { 187310037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 187410037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 187510037SARM gem5 Developers newVal = cpsr; 187610037SARM gem5 Developers misc_reg = MISCREG_CPSR; 187710037SARM gem5 Developers } 187810037SARM gem5 Developers break; 187910037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 188010037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 188110037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 188210037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 188310037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 188410037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 188510037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 188610037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 188710037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 188810037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 188910037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 189010037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 189110037SARM gem5 Developers { 189212749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(); 189311608Snikos.nikoleris@arm.com Request::Flags flags = 0; 189410037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 189510037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 189610037SARM gem5 Developers Fault fault; 189710037SARM gem5 Developers switch(misc_reg) { 189810037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 189910037SARM gem5 Developers flags = TLB::MustBeOne; 190011577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 190110037SARM gem5 Developers mode = BaseTLB::Read; 190210037SARM gem5 Developers break; 190310037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 190410037SARM gem5 Developers flags = TLB::MustBeOne; 190511577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 190610037SARM gem5 Developers mode = BaseTLB::Write; 190710037SARM gem5 Developers break; 190810037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 190910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 191011577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 191110037SARM gem5 Developers mode = BaseTLB::Read; 191210037SARM gem5 Developers break; 191310037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 191410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 191511577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 191610037SARM gem5 Developers mode = BaseTLB::Write; 191710037SARM gem5 Developers break; 191810037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 191910037SARM gem5 Developers flags = TLB::MustBeOne; 192011577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 192110037SARM gem5 Developers mode = BaseTLB::Read; 192210037SARM gem5 Developers break; 192310037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 192410037SARM gem5 Developers flags = TLB::MustBeOne; 192511577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 192610037SARM gem5 Developers mode = BaseTLB::Write; 192710037SARM gem5 Developers break; 192810037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 192910037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 193011577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 193110037SARM gem5 Developers mode = BaseTLB::Read; 193210037SARM gem5 Developers break; 193310037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 193410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 193511577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 193610037SARM gem5 Developers mode = BaseTLB::Write; 193710037SARM gem5 Developers break; 193810037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 193910037SARM gem5 Developers flags = TLB::MustBeOne; 194011577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 194110037SARM gem5 Developers mode = BaseTLB::Read; 194210037SARM gem5 Developers break; 194310037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 194410037SARM gem5 Developers flags = TLB::MustBeOne; 194511577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 194610037SARM gem5 Developers mode = BaseTLB::Write; 194710037SARM gem5 Developers break; 194810037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 194910037SARM gem5 Developers flags = TLB::MustBeOne; 195011577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 195110037SARM gem5 Developers mode = BaseTLB::Read; 195210037SARM gem5 Developers break; 195310037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 195410037SARM gem5 Developers flags = TLB::MustBeOne; 195511577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 195610037SARM gem5 Developers mode = BaseTLB::Write; 195710037SARM gem5 Developers break; 195810037SARM gem5 Developers } 195910037SARM gem5 Developers // If we're in timing mode then doing the translation in 196010037SARM gem5 Developers // functional mode then we're slightly distorting performance 196110037SARM gem5 Developers // results obtained from simulations. The translation should be 196210037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 196310037SARM gem5 Developers // can't be an atomic translation because that causes problems 196410037SARM gem5 Developers // with unexpected atomic snoop requests. 196513417Sgiacomo.travaglini@arm.com warn("Translating via %s in functional mode! Fix Me!\n", 196613417Sgiacomo.travaglini@arm.com miscRegName[misc_reg]); 196713417Sgiacomo.travaglini@arm.com 196811560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 196910037SARM gem5 Developers tc->pcState().pc()); 197011435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 197112406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 197212406Sgabeblack@google.com tranType); 197310037SARM gem5 Developers 197413581Sgabeblack@google.com RegVal newVal; 197510037SARM gem5 Developers if (fault == NoFault) { 197610037SARM gem5 Developers Addr paddr = req->getPaddr(); 197712406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 197810037SARM gem5 Developers uint64_t attr1 = attr >> 56; 197910037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 198010037SARM gem5 Developers attr |= 0x100; 198110037SARM gem5 Developers attr &= ~ uint64_t(0x80); 198210037SARM gem5 Developers } 198310037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 198410037SARM gem5 Developers DPRINTF(MiscRegs, 198510037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 198610037SARM gem5 Developers val, newVal); 198710037SARM gem5 Developers } else { 198812524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 198912570Sgiacomo.travaglini@arm.com armFault->update(tc); 199010037SARM gem5 Developers // Set fault bit and FSR 199110037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 199210037SARM gem5 Developers 199311577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 199411577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 199511577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 199611577SDylan.Johnson@ARM.com // rearrange fault status 199711577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 199811577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 199911577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 200011577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 200111577SDylan.Johnson@ARM.com } else { // AArch64 200211577SDylan.Johnson@ARM.com newVal = 1; // F bit 200311577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 200411577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 200511577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 200611577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 200711577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 200811577SDylan.Johnson@ARM.com } 200910037SARM gem5 Developers DPRINTF(MiscRegs, 201010037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 201110037SARM gem5 Developers val, fsr, newVal); 201210037SARM gem5 Developers } 201310037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 201410037SARM gem5 Developers return; 201510037SARM gem5 Developers } 201610037SARM gem5 Developers case MISCREG_SPSR_EL3: 201710037SARM gem5 Developers case MISCREG_SPSR_EL2: 201810037SARM gem5 Developers case MISCREG_SPSR_EL1: 201910037SARM gem5 Developers // Force bits 23:21 to 0 202010037SARM gem5 Developers newVal = val & ~(0x7 << 21); 202110037SARM gem5 Developers break; 20228549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 20238549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 20248549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 202510037SARM gem5 Developers break; 202610037SARM gem5 Developers 202710037SARM gem5 Developers // Generic Timer registers 202812816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 202912816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 203012816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 203110844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 203210844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 203310844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 203410844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 203510844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 203610037SARM gem5 Developers break; 203713531Sjairo.balart@metempsy.com case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3: 203813531Sjairo.balart@metempsy.com case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2: 203913531Sjairo.balart@metempsy.com getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal); 204013531Sjairo.balart@metempsy.com return; 204113759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL3: 204213759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL2: 204313759Sgiacomo.gabrielli@arm.com case MISCREG_ZCR_EL1: 204413759Sgiacomo.gabrielli@arm.com tc->getDecoderPtr()->setSveLen( 204513759Sgiacomo.gabrielli@arm.com (getCurSveVecLenInBits(tc) >> 7) - 1); 204613759Sgiacomo.gabrielli@arm.com break; 20477405SAli.Saidi@ARM.com } 20487405SAli.Saidi@ARM.com } 20497405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 20507405SAli.Saidi@ARM.com} 20517405SAli.Saidi@ARM.com 205210844Sandreas.sandberg@arm.comBaseISADevice & 205310844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 205410037SARM gem5 Developers{ 205510844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 205610844Sandreas.sandberg@arm.com // to access the timer. 205710844Sandreas.sandberg@arm.com if (timer) 205810844Sandreas.sandberg@arm.com return *timer.get(); 205910844Sandreas.sandberg@arm.com 206010844Sandreas.sandberg@arm.com assert(system); 206110844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 206210844Sandreas.sandberg@arm.com if (!generic_timer) { 206310844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 206410844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 206510037SARM gem5 Developers } 206610037SARM gem5 Developers 206711150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 206812972Sandreas.sandberg@arm.com timer->setThreadContext(tc); 206912972Sandreas.sandberg@arm.com 207010844Sandreas.sandberg@arm.com return *timer.get(); 207110037SARM gem5 Developers} 207210037SARM gem5 Developers 207313531Sjairo.balart@metempsy.comBaseISADevice & 207413531Sjairo.balart@metempsy.comISA::getGICv3CPUInterface(ThreadContext *tc) 207513531Sjairo.balart@metempsy.com{ 207613531Sjairo.balart@metempsy.com panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!"); 207713531Sjairo.balart@metempsy.com return *gicv3CpuInterface.get(); 207813531Sjairo.balart@metempsy.com} 207913531Sjairo.balart@metempsy.com 208013759Sgiacomo.gabrielli@arm.comunsigned 208113759Sgiacomo.gabrielli@arm.comISA::getCurSveVecLenInBits(ThreadContext *tc) const 208213759Sgiacomo.gabrielli@arm.com{ 208313759Sgiacomo.gabrielli@arm.com if (!FullSystem) { 208413759Sgiacomo.gabrielli@arm.com return sveVL * 128; 208513759Sgiacomo.gabrielli@arm.com } 208613759Sgiacomo.gabrielli@arm.com 208713759Sgiacomo.gabrielli@arm.com panic_if(!tc, 208813759Sgiacomo.gabrielli@arm.com "A ThreadContext is needed to determine the SVE vector length " 208913759Sgiacomo.gabrielli@arm.com "in full-system mode"); 209013759Sgiacomo.gabrielli@arm.com 209113759Sgiacomo.gabrielli@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 209213759Sgiacomo.gabrielli@arm.com ExceptionLevel el = (ExceptionLevel) (uint8_t) cpsr.el; 209313759Sgiacomo.gabrielli@arm.com 209413759Sgiacomo.gabrielli@arm.com unsigned len = 0; 209513759Sgiacomo.gabrielli@arm.com 209613759Sgiacomo.gabrielli@arm.com if (el == EL1 || (el == EL0 && !ELIsInHost(tc, el))) { 209713759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL1]).len; 209813759Sgiacomo.gabrielli@arm.com } 209913759Sgiacomo.gabrielli@arm.com 210013759Sgiacomo.gabrielli@arm.com if (el == EL2 || (el == EL0 && ELIsInHost(tc, el))) { 210113759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len; 210213759Sgiacomo.gabrielli@arm.com } else if (haveVirtualization && !inSecureState(tc) && 210313759Sgiacomo.gabrielli@arm.com (el == EL0 || el == EL1)) { 210413759Sgiacomo.gabrielli@arm.com len = std::min( 210513759Sgiacomo.gabrielli@arm.com len, 210613759Sgiacomo.gabrielli@arm.com static_cast<unsigned>( 210713759Sgiacomo.gabrielli@arm.com static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL2]).len)); 210813759Sgiacomo.gabrielli@arm.com } 210913759Sgiacomo.gabrielli@arm.com 211013759Sgiacomo.gabrielli@arm.com if (el == EL3) { 211113759Sgiacomo.gabrielli@arm.com len = static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len; 211213759Sgiacomo.gabrielli@arm.com } else if (haveSecurity) { 211313759Sgiacomo.gabrielli@arm.com len = std::min( 211413759Sgiacomo.gabrielli@arm.com len, 211513759Sgiacomo.gabrielli@arm.com static_cast<unsigned>( 211613759Sgiacomo.gabrielli@arm.com static_cast<ZCR>(miscRegs[MISCREG_ZCR_EL3]).len)); 211713759Sgiacomo.gabrielli@arm.com } 211813759Sgiacomo.gabrielli@arm.com 211913759Sgiacomo.gabrielli@arm.com len = std::min(len, sveVL - 1); 212013759Sgiacomo.gabrielli@arm.com 212113759Sgiacomo.gabrielli@arm.com return (len + 1) * 128; 21227405SAli.Saidi@ARM.com} 21239384SAndreas.Sandberg@arm.com 212413759Sgiacomo.gabrielli@arm.comvoid 212513759Sgiacomo.gabrielli@arm.comISA::zeroSveVecRegUpperPart(VecRegContainer &vc, unsigned eCount) 212613759Sgiacomo.gabrielli@arm.com{ 212713759Sgiacomo.gabrielli@arm.com auto vv = vc.as<uint64_t>(); 212813759Sgiacomo.gabrielli@arm.com for (int i = 2; i < eCount; ++i) { 212913759Sgiacomo.gabrielli@arm.com vv[i] = 0; 213013759Sgiacomo.gabrielli@arm.com } 213113759Sgiacomo.gabrielli@arm.com} 213213759Sgiacomo.gabrielli@arm.com 213313759Sgiacomo.gabrielli@arm.com} // namespace ArmISA 213413759Sgiacomo.gabrielli@arm.com 21359384SAndreas.Sandberg@arm.comArmISA::ISA * 21369384SAndreas.Sandberg@arm.comArmISAParams::create() 21379384SAndreas.Sandberg@arm.com{ 21389384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 21399384SAndreas.Sandberg@arm.com} 2140