isa.cc revision 13550
17405SAli.Saidi@ARM.com/*
212667Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited
37405SAli.Saidi@ARM.com * All rights reserved
47405SAli.Saidi@ARM.com *
57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97405SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137405SAli.Saidi@ARM.com *
147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
237405SAli.Saidi@ARM.com * this software without specific prior written permission.
247405SAli.Saidi@ARM.com *
257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
367405SAli.Saidi@ARM.com *
377405SAli.Saidi@ARM.com * Authors: Gabe Black
387405SAli.Saidi@ARM.com *          Ali Saidi
397405SAli.Saidi@ARM.com */
407405SAli.Saidi@ARM.com
417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh"
4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh"
439050Schander.sudanthi@arm.com#include "arch/arm/system.hh"
4412406Sgabeblack@google.com#include "arch/arm/tlb.hh"
4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh"
4611793Sbrandon.potter@amd.com#include "cpu/base.hh"
478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh"
488232Snate@binkert.org#include "debug/Arm.hh"
498232Snate@binkert.org#include "debug/MiscRegs.hh"
5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh"
5113531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3.hh"
5213531Sjairo.balart@metempsy.com#include "dev/arm/gic_v3_cpu_interface.hh"
539384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh"
547678Sgblack@eecs.umich.edu#include "sim/faults.hh"
558059SAli.Saidi@ARM.com#include "sim/stat_control.hh"
568284SAli.Saidi@ARM.com#include "sim/system.hh"
577405SAli.Saidi@ARM.com
587405SAli.Saidi@ARM.comnamespace ArmISA
597405SAli.Saidi@ARM.com{
607405SAli.Saidi@ARM.com
619384SAndreas.Sandberg@arm.comISA::ISA(Params *p)
6210461SAndreas.Sandberg@ARM.com    : SimObject(p),
6310461SAndreas.Sandberg@ARM.com      system(NULL),
6411165SRekai.GonzalezAlberquilla@arm.com      _decoderFlavour(p->decoderFlavour),
6512109SRekai.GonzalezAlberquilla@arm.com      _vecRegRenameMode(p->vecRegRenameMode),
6612714Sgiacomo.travaglini@arm.com      pmu(p->pmu),
6712714Sgiacomo.travaglini@arm.com      impdefAsNop(p->impdef_nop)
689384SAndreas.Sandberg@arm.com{
6911770SCurtis.Dunham@arm.com    miscRegs[MISCREG_SCTLR_RST] = 0;
7010037SARM gem5 Developers
7110461SAndreas.Sandberg@ARM.com    // Hook up a dummy device if we haven't been configured with a
7210461SAndreas.Sandberg@ARM.com    // real PMU. By using a dummy device, we don't need to check that
7310461SAndreas.Sandberg@ARM.com    // the PMU exist every time we try to access a PMU register.
7410461SAndreas.Sandberg@ARM.com    if (!pmu)
7510461SAndreas.Sandberg@ARM.com        pmu = &dummyDevice;
7610461SAndreas.Sandberg@ARM.com
7710609Sandreas.sandberg@arm.com    // Give all ISA devices a pointer to this ISA
7810609Sandreas.sandberg@arm.com    pmu->setISA(this);
7910609Sandreas.sandberg@arm.com
8010037SARM gem5 Developers    system = dynamic_cast<ArmSystem *>(p->system);
8110037SARM gem5 Developers
8210037SARM gem5 Developers    // Cache system-level properties
8310037SARM gem5 Developers    if (FullSystem && system) {
8411771SCurtis.Dunham@arm.com        highestELIs64 = system->highestELIs64();
8510037SARM gem5 Developers        haveSecurity = system->haveSecurity();
8610037SARM gem5 Developers        haveLPAE = system->haveLPAE();
8713173Sgiacomo.travaglini@arm.com        haveCrypto = system->haveCrypto();
8810037SARM gem5 Developers        haveVirtualization = system->haveVirtualization();
8910037SARM gem5 Developers        haveLargeAsid64 = system->haveLargeAsid64();
9013114Sgiacomo.travaglini@arm.com        physAddrRange = system->physAddrRange();
9110037SARM gem5 Developers    } else {
9211771SCurtis.Dunham@arm.com        highestELIs64 = true; // ArmSystem::highestELIs64 does the same
9310037SARM gem5 Developers        haveSecurity = haveLPAE = haveVirtualization = false;
9413499Sgiacomo.travaglini@arm.com        haveCrypto = true;
9510037SARM gem5 Developers        haveLargeAsid64 = false;
9613114Sgiacomo.travaglini@arm.com        physAddrRange = 32;  // dummy value
9710037SARM gem5 Developers    }
9810037SARM gem5 Developers
9913531Sjairo.balart@metempsy.com    // GICv3 CPU interface system registers are supported
10013531Sjairo.balart@metempsy.com    haveGICv3CPUInterface = false;
10113531Sjairo.balart@metempsy.com
10213531Sjairo.balart@metempsy.com    if (system && dynamic_cast<Gicv3 *>(system->getGIC())) {
10313531Sjairo.balart@metempsy.com        haveGICv3CPUInterface = true;
10413531Sjairo.balart@metempsy.com    }
10513531Sjairo.balart@metempsy.com
10612477SCurtis.Dunham@arm.com    initializeMiscRegMetadata();
10710037SARM gem5 Developers    preUnflattenMiscReg();
10810037SARM gem5 Developers
1099384SAndreas.Sandberg@arm.com    clear();
1109384SAndreas.Sandberg@arm.com}
1119384SAndreas.Sandberg@arm.com
11212479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS);
11312479SCurtis.Dunham@arm.com
1149384SAndreas.Sandberg@arm.comconst ArmISAParams *
1159384SAndreas.Sandberg@arm.comISA::params() const
1169384SAndreas.Sandberg@arm.com{
1179384SAndreas.Sandberg@arm.com    return dynamic_cast<const Params *>(_params);
1189384SAndreas.Sandberg@arm.com}
1199384SAndreas.Sandberg@arm.com
1207427Sgblack@eecs.umich.eduvoid
1217427Sgblack@eecs.umich.eduISA::clear()
1227427Sgblack@eecs.umich.edu{
1239385SAndreas.Sandberg@arm.com    const Params *p(params());
1249385SAndreas.Sandberg@arm.com
1257427Sgblack@eecs.umich.edu    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
1267427Sgblack@eecs.umich.edu    memset(miscRegs, 0, sizeof(miscRegs));
12710037SARM gem5 Developers
12813114Sgiacomo.travaglini@arm.com    initID32(p);
12910037SARM gem5 Developers
13013114Sgiacomo.travaglini@arm.com    // We always initialize AArch64 ID registers even
13113114Sgiacomo.travaglini@arm.com    // if we are in AArch32. This is done since if we
13213114Sgiacomo.travaglini@arm.com    // are in SE mode we don't know if our ArmProcess is
13313114Sgiacomo.travaglini@arm.com    // AArch32 or AArch64
13413114Sgiacomo.travaglini@arm.com    initID64(p);
13512690Sgiacomo.travaglini@arm.com
13610037SARM gem5 Developers    // Start with an event in the mailbox
1377427Sgblack@eecs.umich.edu    miscRegs[MISCREG_SEV_MAILBOX] = 1;
1387427Sgblack@eecs.umich.edu
13910037SARM gem5 Developers    // Separate Instruction and Data TLBs
1407427Sgblack@eecs.umich.edu    miscRegs[MISCREG_TLBTR] = 1;
1417427Sgblack@eecs.umich.edu
1427427Sgblack@eecs.umich.edu    MVFR0 mvfr0 = 0;
1437427Sgblack@eecs.umich.edu    mvfr0.advSimdRegisters = 2;
1447427Sgblack@eecs.umich.edu    mvfr0.singlePrecision = 2;
1457427Sgblack@eecs.umich.edu    mvfr0.doublePrecision = 2;
1467427Sgblack@eecs.umich.edu    mvfr0.vfpExceptionTrapping = 0;
1477427Sgblack@eecs.umich.edu    mvfr0.divide = 1;
1487427Sgblack@eecs.umich.edu    mvfr0.squareRoot = 1;
1497427Sgblack@eecs.umich.edu    mvfr0.shortVectors = 1;
1507427Sgblack@eecs.umich.edu    mvfr0.roundingModes = 1;
1517427Sgblack@eecs.umich.edu    miscRegs[MISCREG_MVFR0] = mvfr0;
1527427Sgblack@eecs.umich.edu
1537427Sgblack@eecs.umich.edu    MVFR1 mvfr1 = 0;
1547427Sgblack@eecs.umich.edu    mvfr1.flushToZero = 1;
1557427Sgblack@eecs.umich.edu    mvfr1.defaultNaN = 1;
1567427Sgblack@eecs.umich.edu    mvfr1.advSimdLoadStore = 1;
1577427Sgblack@eecs.umich.edu    mvfr1.advSimdInteger = 1;
1587427Sgblack@eecs.umich.edu    mvfr1.advSimdSinglePrecision = 1;
1597427Sgblack@eecs.umich.edu    mvfr1.advSimdHalfPrecision = 1;
1607427Sgblack@eecs.umich.edu    mvfr1.vfpHalfPrecision = 1;
1617427Sgblack@eecs.umich.edu    miscRegs[MISCREG_MVFR1] = mvfr1;
1627427Sgblack@eecs.umich.edu
1637436Sdam.sunwoo@arm.com    // Reset values of PRRR and NMRR are implementation dependent
1647436Sdam.sunwoo@arm.com
16510037SARM gem5 Developers    // @todo: PRRR and NMRR in secure state?
16610037SARM gem5 Developers    miscRegs[MISCREG_PRRR_NS] =
1677436Sdam.sunwoo@arm.com        (1 << 19) | // 19
1687436Sdam.sunwoo@arm.com        (0 << 18) | // 18
1697436Sdam.sunwoo@arm.com        (0 << 17) | // 17
1707436Sdam.sunwoo@arm.com        (1 << 16) | // 16
1717436Sdam.sunwoo@arm.com        (2 << 14) | // 15:14
1727436Sdam.sunwoo@arm.com        (0 << 12) | // 13:12
1737436Sdam.sunwoo@arm.com        (2 << 10) | // 11:10
1747436Sdam.sunwoo@arm.com        (2 << 8)  | // 9:8
1757436Sdam.sunwoo@arm.com        (2 << 6)  | // 7:6
1767436Sdam.sunwoo@arm.com        (2 << 4)  | // 5:4
1777436Sdam.sunwoo@arm.com        (1 << 2)  | // 3:2
1787436Sdam.sunwoo@arm.com        0;          // 1:0
17913393Sgiacomo.travaglini@arm.com
18010037SARM gem5 Developers    miscRegs[MISCREG_NMRR_NS] =
1817436Sdam.sunwoo@arm.com        (1 << 30) | // 31:30
1827436Sdam.sunwoo@arm.com        (0 << 26) | // 27:26
1837436Sdam.sunwoo@arm.com        (0 << 24) | // 25:24
1847436Sdam.sunwoo@arm.com        (3 << 22) | // 23:22
1857436Sdam.sunwoo@arm.com        (2 << 20) | // 21:20
1867436Sdam.sunwoo@arm.com        (0 << 18) | // 19:18
1877436Sdam.sunwoo@arm.com        (0 << 16) | // 17:16
1887436Sdam.sunwoo@arm.com        (1 << 14) | // 15:14
1897436Sdam.sunwoo@arm.com        (0 << 12) | // 13:12
1907436Sdam.sunwoo@arm.com        (2 << 10) | // 11:10
1917436Sdam.sunwoo@arm.com        (0 << 8)  | // 9:8
1927436Sdam.sunwoo@arm.com        (3 << 6)  | // 7:6
1937436Sdam.sunwoo@arm.com        (2 << 4)  | // 5:4
1947436Sdam.sunwoo@arm.com        (0 << 2)  | // 3:2
1957436Sdam.sunwoo@arm.com        0;          // 1:0
1967436Sdam.sunwoo@arm.com
19713393Sgiacomo.travaglini@arm.com    if (FullSystem && system->highestELIs64()) {
19813393Sgiacomo.travaglini@arm.com        // Initialize AArch64 state
19913393Sgiacomo.travaglini@arm.com        clear64(p);
20013393Sgiacomo.travaglini@arm.com        return;
20113393Sgiacomo.travaglini@arm.com    }
20213393Sgiacomo.travaglini@arm.com
20313393Sgiacomo.travaglini@arm.com    // Initialize AArch32 state...
20413393Sgiacomo.travaglini@arm.com    clear32(p, sctlr_rst);
20513393Sgiacomo.travaglini@arm.com}
20613393Sgiacomo.travaglini@arm.com
20713393Sgiacomo.travaglini@arm.comvoid
20813393Sgiacomo.travaglini@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst)
20913393Sgiacomo.travaglini@arm.com{
21013393Sgiacomo.travaglini@arm.com    CPSR cpsr = 0;
21113393Sgiacomo.travaglini@arm.com    cpsr.mode = MODE_USER;
21213393Sgiacomo.travaglini@arm.com
21313396Sgiacomo.travaglini@arm.com    if (FullSystem) {
21413396Sgiacomo.travaglini@arm.com        miscRegs[MISCREG_MVBAR] = system->resetAddr();
21513396Sgiacomo.travaglini@arm.com    }
21613396Sgiacomo.travaglini@arm.com
21713393Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_CPSR] = cpsr;
21813393Sgiacomo.travaglini@arm.com    updateRegMap(cpsr);
21913393Sgiacomo.travaglini@arm.com
22013393Sgiacomo.travaglini@arm.com    SCTLR sctlr = 0;
22113393Sgiacomo.travaglini@arm.com    sctlr.te = (bool) sctlr_rst.te;
22213393Sgiacomo.travaglini@arm.com    sctlr.nmfi = (bool) sctlr_rst.nmfi;
22313393Sgiacomo.travaglini@arm.com    sctlr.v = (bool) sctlr_rst.v;
22413393Sgiacomo.travaglini@arm.com    sctlr.u = 1;
22513393Sgiacomo.travaglini@arm.com    sctlr.xp = 1;
22613393Sgiacomo.travaglini@arm.com    sctlr.rao2 = 1;
22713393Sgiacomo.travaglini@arm.com    sctlr.rao3 = 1;
22813393Sgiacomo.travaglini@arm.com    sctlr.rao4 = 0xf;  // SCTLR[6:3]
22913393Sgiacomo.travaglini@arm.com    sctlr.uci = 1;
23013393Sgiacomo.travaglini@arm.com    sctlr.dze = 1;
23113393Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_SCTLR_NS] = sctlr;
23213393Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
23313393Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_HCPTR] = 0;
23413393Sgiacomo.travaglini@arm.com
2357644Sali.saidi@arm.com    miscRegs[MISCREG_CPACR] = 0;
2368147SAli.Saidi@ARM.com
2379385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_FPSID] = p->fpsid;
2389385SAndreas.Sandberg@arm.com
23910037SARM gem5 Developers    if (haveLPAE) {
24010037SARM gem5 Developers        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
24110037SARM gem5 Developers        ttbcr.eae = 0;
24210037SARM gem5 Developers        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
24310037SARM gem5 Developers        // Enforce consistency with system-level settings
24410037SARM gem5 Developers        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
24510037SARM gem5 Developers    }
24610037SARM gem5 Developers
24710037SARM gem5 Developers    if (haveSecurity) {
24810037SARM gem5 Developers        miscRegs[MISCREG_SCTLR_S] = sctlr;
24910037SARM gem5 Developers        miscRegs[MISCREG_SCR] = 0;
25010037SARM gem5 Developers        miscRegs[MISCREG_VBAR_S] = 0;
25110037SARM gem5 Developers    } else {
25210037SARM gem5 Developers        // we're always non-secure
25310037SARM gem5 Developers        miscRegs[MISCREG_SCR] = 1;
25410037SARM gem5 Developers    }
2558147SAli.Saidi@ARM.com
2567427Sgblack@eecs.umich.edu    //XXX We need to initialize the rest of the state.
2577427Sgblack@eecs.umich.edu}
2587427Sgblack@eecs.umich.edu
25910037SARM gem5 Developersvoid
26010037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p)
26110037SARM gem5 Developers{
26210037SARM gem5 Developers    CPSR cpsr = 0;
26313396Sgiacomo.travaglini@arm.com    Addr rvbar = system->resetAddr();
26410037SARM gem5 Developers    switch (system->highestEL()) {
26510037SARM gem5 Developers        // Set initial EL to highest implemented EL using associated stack
26610037SARM gem5 Developers        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
26710037SARM gem5 Developers        // value
26810037SARM gem5 Developers      case EL3:
26910037SARM gem5 Developers        cpsr.mode = MODE_EL3H;
27010037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
27110037SARM gem5 Developers        break;
27210037SARM gem5 Developers      case EL2:
27310037SARM gem5 Developers        cpsr.mode = MODE_EL2H;
27410037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
27510037SARM gem5 Developers        break;
27610037SARM gem5 Developers      case EL1:
27710037SARM gem5 Developers        cpsr.mode = MODE_EL1H;
27810037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
27910037SARM gem5 Developers        break;
28010037SARM gem5 Developers      default:
28110037SARM gem5 Developers        panic("Invalid highest implemented exception level");
28210037SARM gem5 Developers        break;
28310037SARM gem5 Developers    }
28410037SARM gem5 Developers
28510037SARM gem5 Developers    // Initialize rest of CPSR
28610037SARM gem5 Developers    cpsr.daif = 0xf;  // Mask all interrupts
28710037SARM gem5 Developers    cpsr.ss = 0;
28810037SARM gem5 Developers    cpsr.il = 0;
28910037SARM gem5 Developers    miscRegs[MISCREG_CPSR] = cpsr;
29010037SARM gem5 Developers    updateRegMap(cpsr);
29110037SARM gem5 Developers
29210037SARM gem5 Developers    // Initialize other control registers
29310037SARM gem5 Developers    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
29410037SARM gem5 Developers    if (haveSecurity) {
29511770SCurtis.Dunham@arm.com        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830;
29610037SARM gem5 Developers        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
29711574SCurtis.Dunham@arm.com    } else if (haveVirtualization) {
29811770SCurtis.Dunham@arm.com        // also  MISCREG_SCTLR_EL2 (by mapping)
29911770SCurtis.Dunham@arm.com        miscRegs[MISCREG_HSCTLR] = 0x30c50830;
30010037SARM gem5 Developers    } else {
30111770SCurtis.Dunham@arm.com        // also  MISCREG_SCTLR_EL1 (by mapping)
30211770SCurtis.Dunham@arm.com        miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init
30310037SARM gem5 Developers        // Always non-secure
30410037SARM gem5 Developers        miscRegs[MISCREG_SCR_EL3] = 1;
30510037SARM gem5 Developers    }
30613114Sgiacomo.travaglini@arm.com}
30710037SARM gem5 Developers
30813114Sgiacomo.travaglini@arm.comvoid
30913114Sgiacomo.travaglini@arm.comISA::initID32(const ArmISAParams *p)
31013114Sgiacomo.travaglini@arm.com{
31113114Sgiacomo.travaglini@arm.com    // Initialize configurable default values
31213114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_MIDR] = p->midr;
31313114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_MIDR_EL1] = p->midr;
31413114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_VPIDR] = p->midr;
31513114Sgiacomo.travaglini@arm.com
31613114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
31713114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
31813114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
31913114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
32013114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
32113114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
32213114Sgiacomo.travaglini@arm.com
32313114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
32413114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
32513114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
32613114Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
32713499Sgiacomo.travaglini@arm.com
32813499Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_ISAR5] = insertBits(
32913499Sgiacomo.travaglini@arm.com        miscRegs[MISCREG_ID_ISAR5], 19, 4,
33013499Sgiacomo.travaglini@arm.com        haveCrypto ? 0x1112 : 0x0);
33113114Sgiacomo.travaglini@arm.com}
33213114Sgiacomo.travaglini@arm.com
33313114Sgiacomo.travaglini@arm.comvoid
33413114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p)
33513114Sgiacomo.travaglini@arm.com{
33610037SARM gem5 Developers    // Initialize configurable id registers
33710037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
33810037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
33910461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
34010461SAndreas.Sandberg@ARM.com        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
34110461SAndreas.Sandberg@ARM.com        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
34210461SAndreas.Sandberg@ARM.com
34310037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
34410037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
34510037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
34610037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
34710037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
34813116Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1;
34910037SARM gem5 Developers
35010461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_DFR0_EL1] =
35110461SAndreas.Sandberg@ARM.com        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
35210461SAndreas.Sandberg@ARM.com
35310461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
35410461SAndreas.Sandberg@ARM.com
35510037SARM gem5 Developers    // Enforce consistency with system-level settings...
35610037SARM gem5 Developers
35710037SARM gem5 Developers    // EL3
35810037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
35910037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
36011574SCurtis.Dunham@arm.com        haveSecurity ? 0x2 : 0x0);
36110037SARM gem5 Developers    // EL2
36210037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
36310037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
36411574SCurtis.Dunham@arm.com        haveVirtualization ? 0x2 : 0x0);
36510037SARM gem5 Developers    // Large ASID support
36610037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
36710037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
36810037SARM gem5 Developers        haveLargeAsid64 ? 0x2 : 0x0);
36910037SARM gem5 Developers    // Physical address size
37010037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
37110037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
37213114Sgiacomo.travaglini@arm.com        encodePhysAddrRange64(physAddrRange));
37313173Sgiacomo.travaglini@arm.com    // Crypto
37413173Sgiacomo.travaglini@arm.com    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits(
37513173Sgiacomo.travaglini@arm.com        miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4,
37613173Sgiacomo.travaglini@arm.com        haveCrypto ? 0x1112 : 0x0);
37710037SARM gem5 Developers}
37810037SARM gem5 Developers
37912972Sandreas.sandberg@arm.comvoid
38012972Sandreas.sandberg@arm.comISA::startup(ThreadContext *tc)
38112972Sandreas.sandberg@arm.com{
38212972Sandreas.sandberg@arm.com    pmu->setThreadContext(tc);
38312972Sandreas.sandberg@arm.com
38413531Sjairo.balart@metempsy.com    if (system) {
38513531Sjairo.balart@metempsy.com        Gicv3 *gicv3 = dynamic_cast<Gicv3 *>(system->getGIC());
38613531Sjairo.balart@metempsy.com        if (gicv3) {
38713531Sjairo.balart@metempsy.com            gicv3CpuInterface.reset(gicv3->getCPUInterface(tc->contextId()));
38813531Sjairo.balart@metempsy.com            gicv3CpuInterface->setISA(this);
38913531Sjairo.balart@metempsy.com        }
39013531Sjairo.balart@metempsy.com    }
39112972Sandreas.sandberg@arm.com}
39212972Sandreas.sandberg@arm.com
39312972Sandreas.sandberg@arm.com
3947405SAli.Saidi@ARM.comMiscReg
39510035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const
3967405SAli.Saidi@ARM.com{
3977405SAli.Saidi@ARM.com    assert(misc_reg < NumMiscRegs);
3987614Sminkyu.jeong@arm.com
39912478SCurtis.Dunham@arm.com    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
40012478SCurtis.Dunham@arm.com    const auto &map = getMiscIndices(misc_reg);
40112478SCurtis.Dunham@arm.com    int lower = map.first, upper = map.second;
40212478SCurtis.Dunham@arm.com    // NB!: apply architectural masks according to desired register,
40312478SCurtis.Dunham@arm.com    // despite possibly getting value from different (mapped) register.
40412478SCurtis.Dunham@arm.com    auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32))
40512478SCurtis.Dunham@arm.com                                          |(miscRegs[upper] << 32));
40612478SCurtis.Dunham@arm.com    if (val & reg.res0()) {
40712478SCurtis.Dunham@arm.com        DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n",
40812478SCurtis.Dunham@arm.com                miscRegName[misc_reg], val & reg.res0());
40912478SCurtis.Dunham@arm.com    }
41012478SCurtis.Dunham@arm.com    if ((val & reg.res1()) != reg.res1()) {
41112478SCurtis.Dunham@arm.com        DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n",
41212478SCurtis.Dunham@arm.com                miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1());
41312478SCurtis.Dunham@arm.com    }
41412478SCurtis.Dunham@arm.com    return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao
4157405SAli.Saidi@ARM.com}
4167405SAli.Saidi@ARM.com
4177405SAli.Saidi@ARM.com
4187405SAli.Saidi@ARM.comMiscReg
4197405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc)
4207405SAli.Saidi@ARM.com{
42110037SARM gem5 Developers    CPSR cpsr = 0;
42210037SARM gem5 Developers    PCState pc = 0;
42310037SARM gem5 Developers    SCR scr = 0;
4249050Schander.sudanthi@arm.com
4257405SAli.Saidi@ARM.com    if (misc_reg == MISCREG_CPSR) {
42610037SARM gem5 Developers        cpsr = miscRegs[misc_reg];
42710037SARM gem5 Developers        pc = tc->pcState();
4287720Sgblack@eecs.umich.edu        cpsr.j = pc.jazelle() ? 1 : 0;
4297720Sgblack@eecs.umich.edu        cpsr.t = pc.thumb() ? 1 : 0;
4307405SAli.Saidi@ARM.com        return cpsr;
4317405SAli.Saidi@ARM.com    }
4327757SAli.Saidi@ARM.com
43310037SARM gem5 Developers#ifndef NDEBUG
43410037SARM gem5 Developers    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
43510037SARM gem5 Developers        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
43610037SARM gem5 Developers            warn("Unimplemented system register %s read.\n",
43710037SARM gem5 Developers                 miscRegName[misc_reg]);
43810037SARM gem5 Developers        else
43910037SARM gem5 Developers            panic("Unimplemented system register %s read.\n",
44010037SARM gem5 Developers                  miscRegName[misc_reg]);
44110037SARM gem5 Developers    }
44210037SARM gem5 Developers#endif
44310037SARM gem5 Developers
44410037SARM gem5 Developers    switch (unflattenMiscReg(misc_reg)) {
44510037SARM gem5 Developers      case MISCREG_HCR:
44610037SARM gem5 Developers        {
44710037SARM gem5 Developers            if (!haveVirtualization)
44810037SARM gem5 Developers                return 0;
44910037SARM gem5 Developers            else
45010037SARM gem5 Developers                return readMiscRegNoEffect(MISCREG_HCR);
45110037SARM gem5 Developers        }
45210037SARM gem5 Developers      case MISCREG_CPACR:
45310037SARM gem5 Developers        {
45410037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
45510037SARM gem5 Developers            CPACR cpacrMask = 0;
45610037SARM gem5 Developers            // Only cp10, cp11, and ase are implemented, nothing else should
45710037SARM gem5 Developers            // be readable? (straight copy from the write code)
45810037SARM gem5 Developers            cpacrMask.cp10 = ones;
45910037SARM gem5 Developers            cpacrMask.cp11 = ones;
46010037SARM gem5 Developers            cpacrMask.asedis = ones;
46110037SARM gem5 Developers
46210037SARM gem5 Developers            // Security Extensions may limit the readability of CPACR
46310037SARM gem5 Developers            if (haveSecurity) {
46410037SARM gem5 Developers                scr = readMiscRegNoEffect(MISCREG_SCR);
46510037SARM gem5 Developers                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
46612667Schuan.zhu@arm.com                if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
46710037SARM gem5 Developers                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
46810037SARM gem5 Developers                    // NB: Skipping the full loop, here
46910037SARM gem5 Developers                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
47010037SARM gem5 Developers                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
47110037SARM gem5 Developers                }
47210037SARM gem5 Developers            }
47310037SARM gem5 Developers            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
47410037SARM gem5 Developers            val &= cpacrMask;
47510037SARM gem5 Developers            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
47610037SARM gem5 Developers                    miscRegName[misc_reg], val);
47710037SARM gem5 Developers            return val;
47810037SARM gem5 Developers        }
4798284SAli.Saidi@ARM.com      case MISCREG_MPIDR:
48010037SARM gem5 Developers      case MISCREG_MPIDR_EL1:
48113550Sgiacomo.travaglini@arm.com        return readMPIDR(system, tc);
48210037SARM gem5 Developers      case MISCREG_VMPIDR:
48313550Sgiacomo.travaglini@arm.com      case MISCREG_VMPIDR_EL2:
48410037SARM gem5 Developers        // top bit defined as RES1
48510037SARM gem5 Developers        return readMiscRegNoEffect(misc_reg) | 0x80000000;
48610037SARM gem5 Developers      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
48710037SARM gem5 Developers      case MISCREG_REVIDR:  // not implemented, so alias MIDR
48810037SARM gem5 Developers      case MISCREG_MIDR:
48910037SARM gem5 Developers        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
49010037SARM gem5 Developers        scr  = readMiscRegNoEffect(MISCREG_SCR);
49110037SARM gem5 Developers        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
49210037SARM gem5 Developers            return readMiscRegNoEffect(misc_reg);
49310037SARM gem5 Developers        } else {
49410037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_VPIDR);
4959050Schander.sudanthi@arm.com        }
4968284SAli.Saidi@ARM.com        break;
49710037SARM gem5 Developers      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
49810037SARM gem5 Developers      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
49910037SARM gem5 Developers      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
50010037SARM gem5 Developers      case MISCREG_AIDR:  // AUX ID set to 0
50110037SARM gem5 Developers      case MISCREG_TCMTR: // No TCM's
50210037SARM gem5 Developers        return 0;
50310037SARM gem5 Developers
5047405SAli.Saidi@ARM.com      case MISCREG_CLIDR:
5057731SAli.Saidi@ARM.com        warn_once("The clidr register always reports 0 caches.\n");
5068468Swade.walker@arm.com        warn_once("clidr LoUIS field of 0b001 to match current "
5078468Swade.walker@arm.com                  "ARM implementations.\n");
5088468Swade.walker@arm.com        return 0x00200000;
5097405SAli.Saidi@ARM.com      case MISCREG_CCSIDR:
5107731SAli.Saidi@ARM.com        warn_once("The ccsidr register isn't implemented and "
5117405SAli.Saidi@ARM.com                "always reads as 0.\n");
5127405SAli.Saidi@ARM.com        break;
51311809Sbaz21@cam.ac.uk      case MISCREG_CTR:                 // AArch32, ARMv7, top bit set
51411809Sbaz21@cam.ac.uk      case MISCREG_CTR_EL0:             // AArch64
5159130Satgutier@umich.edu        {
5169130Satgutier@umich.edu            //all caches have the same line size in gem5
5179130Satgutier@umich.edu            //4 byte words in ARM
5189130Satgutier@umich.edu            unsigned lineSizeWords =
5199814Sandreas.hansson@arm.com                tc->getSystemPtr()->cacheLineSize() / 4;
5209130Satgutier@umich.edu            unsigned log2LineSizeWords = 0;
5219130Satgutier@umich.edu
5229130Satgutier@umich.edu            while (lineSizeWords >>= 1) {
5239130Satgutier@umich.edu                ++log2LineSizeWords;
5249130Satgutier@umich.edu            }
5259130Satgutier@umich.edu
5269130Satgutier@umich.edu            CTR ctr = 0;
5279130Satgutier@umich.edu            //log2 of minimun i-cache line size (words)
5289130Satgutier@umich.edu            ctr.iCacheLineSize = log2LineSizeWords;
5299130Satgutier@umich.edu            //b11 - gem5 uses pipt
5309130Satgutier@umich.edu            ctr.l1IndexPolicy = 0x3;
5319130Satgutier@umich.edu            //log2 of minimum d-cache line size (words)
5329130Satgutier@umich.edu            ctr.dCacheLineSize = log2LineSizeWords;
5339130Satgutier@umich.edu            //log2 of max reservation size (words)
5349130Satgutier@umich.edu            ctr.erg = log2LineSizeWords;
5359130Satgutier@umich.edu            //log2 of max writeback size (words)
5369130Satgutier@umich.edu            ctr.cwg = log2LineSizeWords;
5379130Satgutier@umich.edu            //b100 - gem5 format is ARMv7
5389130Satgutier@umich.edu            ctr.format = 0x4;
5399130Satgutier@umich.edu
5409130Satgutier@umich.edu            return ctr;
5419130Satgutier@umich.edu        }
5427583SAli.Saidi@arm.com      case MISCREG_ACTLR:
5437583SAli.Saidi@arm.com        warn("Not doing anything for miscreg ACTLR\n");
5447583SAli.Saidi@arm.com        break;
54510461SAndreas.Sandberg@ARM.com
54610461SAndreas.Sandberg@ARM.com      case MISCREG_PMXEVTYPER_PMCCFILTR:
54710461SAndreas.Sandberg@ARM.com      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
54810461SAndreas.Sandberg@ARM.com      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
54910461SAndreas.Sandberg@ARM.com      case MISCREG_PMCR ... MISCREG_PMOVSSET:
55010461SAndreas.Sandberg@ARM.com        return pmu->readMiscReg(misc_reg);
55110461SAndreas.Sandberg@ARM.com
5528302SAli.Saidi@ARM.com      case MISCREG_CPSR_Q:
5538302SAli.Saidi@ARM.com        panic("shouldn't be reading this register seperately\n");
5547783SGiacomo.Gabrielli@arm.com      case MISCREG_FPSCR_QC:
5557783SGiacomo.Gabrielli@arm.com        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
5567783SGiacomo.Gabrielli@arm.com      case MISCREG_FPSCR_EXC:
5577783SGiacomo.Gabrielli@arm.com        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
55810037SARM gem5 Developers      case MISCREG_FPSR:
55910037SARM gem5 Developers        {
56010037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
56110037SARM gem5 Developers            FPSCR fpscrMask = 0;
56210037SARM gem5 Developers            fpscrMask.ioc = ones;
56310037SARM gem5 Developers            fpscrMask.dzc = ones;
56410037SARM gem5 Developers            fpscrMask.ofc = ones;
56510037SARM gem5 Developers            fpscrMask.ufc = ones;
56610037SARM gem5 Developers            fpscrMask.ixc = ones;
56710037SARM gem5 Developers            fpscrMask.idc = ones;
56810037SARM gem5 Developers            fpscrMask.qc = ones;
56910037SARM gem5 Developers            fpscrMask.v = ones;
57010037SARM gem5 Developers            fpscrMask.c = ones;
57110037SARM gem5 Developers            fpscrMask.z = ones;
57210037SARM gem5 Developers            fpscrMask.n = ones;
57310037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
57410037SARM gem5 Developers        }
57510037SARM gem5 Developers      case MISCREG_FPCR:
57610037SARM gem5 Developers        {
57710037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
57810037SARM gem5 Developers            FPSCR fpscrMask  = 0;
57910037SARM gem5 Developers            fpscrMask.len    = ones;
58010037SARM gem5 Developers            fpscrMask.stride = ones;
58110037SARM gem5 Developers            fpscrMask.rMode  = ones;
58210037SARM gem5 Developers            fpscrMask.fz     = ones;
58310037SARM gem5 Developers            fpscrMask.dn     = ones;
58410037SARM gem5 Developers            fpscrMask.ahp    = ones;
58510037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
58610037SARM gem5 Developers        }
58710037SARM gem5 Developers      case MISCREG_NZCV:
58810037SARM gem5 Developers        {
58910037SARM gem5 Developers            CPSR cpsr = 0;
59010338SCurtis.Dunham@arm.com            cpsr.nz   = tc->readCCReg(CCREG_NZ);
59110338SCurtis.Dunham@arm.com            cpsr.c    = tc->readCCReg(CCREG_C);
59210338SCurtis.Dunham@arm.com            cpsr.v    = tc->readCCReg(CCREG_V);
59310037SARM gem5 Developers            return cpsr;
59410037SARM gem5 Developers        }
59510037SARM gem5 Developers      case MISCREG_DAIF:
59610037SARM gem5 Developers        {
59710037SARM gem5 Developers            CPSR cpsr = 0;
59810037SARM gem5 Developers            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
59910037SARM gem5 Developers            return cpsr;
60010037SARM gem5 Developers        }
60110037SARM gem5 Developers      case MISCREG_SP_EL0:
60210037SARM gem5 Developers        {
60310037SARM gem5 Developers            return tc->readIntReg(INTREG_SP0);
60410037SARM gem5 Developers        }
60510037SARM gem5 Developers      case MISCREG_SP_EL1:
60610037SARM gem5 Developers        {
60710037SARM gem5 Developers            return tc->readIntReg(INTREG_SP1);
60810037SARM gem5 Developers        }
60910037SARM gem5 Developers      case MISCREG_SP_EL2:
61010037SARM gem5 Developers        {
61110037SARM gem5 Developers            return tc->readIntReg(INTREG_SP2);
61210037SARM gem5 Developers        }
61310037SARM gem5 Developers      case MISCREG_SPSEL:
61410037SARM gem5 Developers        {
61510037SARM gem5 Developers            return miscRegs[MISCREG_CPSR] & 0x1;
61610037SARM gem5 Developers        }
61710037SARM gem5 Developers      case MISCREG_CURRENTEL:
61810037SARM gem5 Developers        {
61910037SARM gem5 Developers            return miscRegs[MISCREG_CPSR] & 0xc;
62010037SARM gem5 Developers        }
6218549Sdaniel.johnson@arm.com      case MISCREG_L2CTLR:
6228868SMatt.Horsnell@arm.com        {
6238868SMatt.Horsnell@arm.com            // mostly unimplemented, just set NumCPUs field from sim and return
6248868SMatt.Horsnell@arm.com            L2CTLR l2ctlr = 0;
6258868SMatt.Horsnell@arm.com            // b00:1CPU to b11:4CPUs
6268868SMatt.Horsnell@arm.com            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
6278868SMatt.Horsnell@arm.com            return l2ctlr;
6288868SMatt.Horsnell@arm.com        }
6298868SMatt.Horsnell@arm.com      case MISCREG_DBGDIDR:
6308868SMatt.Horsnell@arm.com        /* For now just implement the version number.
63110461SAndreas.Sandberg@ARM.com         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
6328868SMatt.Horsnell@arm.com         */
63310461SAndreas.Sandberg@ARM.com        return 0x5 << 16;
63410037SARM gem5 Developers      case MISCREG_DBGDSCRint:
6358868SMatt.Horsnell@arm.com        return 0;
63610037SARM gem5 Developers      case MISCREG_ISR:
63711150Smitch.hayenga@arm.com        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
63810037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_HCR),
63910037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_CPSR),
64010037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_SCR));
64110037SARM gem5 Developers      case MISCREG_ISR_EL1:
64211150Smitch.hayenga@arm.com        return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR(
64310037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_HCR_EL2),
64410037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_CPSR),
64510037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_SCR_EL3));
64610037SARM gem5 Developers      case MISCREG_DCZID_EL0:
64710037SARM gem5 Developers        return 0x04;  // DC ZVA clear 64-byte chunks
64810037SARM gem5 Developers      case MISCREG_HCPTR:
64910037SARM gem5 Developers        {
65010037SARM gem5 Developers            MiscReg val = readMiscRegNoEffect(misc_reg);
65110037SARM gem5 Developers            // The trap bit associated with CP14 is defined as RAZ
65210037SARM gem5 Developers            val &= ~(1 << 14);
65310037SARM gem5 Developers            // If a CP bit in NSACR is 0 then the corresponding bit in
65410037SARM gem5 Developers            // HCPTR is RAO/WI
65510037SARM gem5 Developers            bool secure_lookup = haveSecurity &&
65610037SARM gem5 Developers                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
65710037SARM gem5 Developers                              readMiscRegNoEffect(MISCREG_CPSR));
65810037SARM gem5 Developers            if (!secure_lookup) {
65910037SARM gem5 Developers                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
66010037SARM gem5 Developers                val |= (mask ^ 0x7FFF) & 0xBFFF;
66110037SARM gem5 Developers            }
66210037SARM gem5 Developers            // Set the bits for unimplemented coprocessors to RAO/WI
66310037SARM gem5 Developers            val |= 0x33FF;
66410037SARM gem5 Developers            return (val);
66510037SARM gem5 Developers        }
66610037SARM gem5 Developers      case MISCREG_HDFAR: // alias for secure DFAR
66710037SARM gem5 Developers        return readMiscRegNoEffect(MISCREG_DFAR_S);
66810037SARM gem5 Developers      case MISCREG_HIFAR: // alias for secure IFAR
66910037SARM gem5 Developers        return readMiscRegNoEffect(MISCREG_IFAR_S);
67010844Sandreas.sandberg@arm.com
67111772SCurtis.Dunham@arm.com      case MISCREG_ID_PFR0:
67211772SCurtis.Dunham@arm.com        // !ThumbEE | !Jazelle | Thumb | ARM
67311772SCurtis.Dunham@arm.com        return 0x00000031;
67411772SCurtis.Dunham@arm.com      case MISCREG_ID_PFR1:
67511774SCurtis.Dunham@arm.com        {   // Timer | Virti | !M Profile | TrustZone | ARMv4
67611774SCurtis.Dunham@arm.com            bool haveTimer = (system->getGenericTimer() != NULL);
67711774SCurtis.Dunham@arm.com            return 0x00000001
67811774SCurtis.Dunham@arm.com                 | (haveSecurity       ? 0x00000010 : 0x0)
67911774SCurtis.Dunham@arm.com                 | (haveVirtualization ? 0x00001000 : 0x0)
68011774SCurtis.Dunham@arm.com                 | (haveTimer          ? 0x00010000 : 0x0);
68111774SCurtis.Dunham@arm.com        }
68211773SCurtis.Dunham@arm.com      case MISCREG_ID_AA64PFR0_EL1:
68313531Sjairo.balart@metempsy.com        return 0x0000000000000002 | // AArch{64,32} supported at EL0
68413531Sjairo.balart@metempsy.com               0x0000000000000020                               | // EL1
68513531Sjairo.balart@metempsy.com               (haveVirtualization    ? 0x0000000000000200 : 0) | // EL2
68613531Sjairo.balart@metempsy.com               (haveSecurity          ? 0x0000000000002000 : 0) | // EL3
68713531Sjairo.balart@metempsy.com               (haveGICv3CPUInterface ? 0x0000000001000000 : 0);
68811773SCurtis.Dunham@arm.com      case MISCREG_ID_AA64PFR1_EL1:
68911773SCurtis.Dunham@arm.com        return 0; // bits [63:0] RES0 (reserved for future use)
69011772SCurtis.Dunham@arm.com
69110037SARM gem5 Developers      // Generic Timer registers
69212816Sgiacomo.travaglini@arm.com      case MISCREG_CNTHV_CTL_EL2:
69312816Sgiacomo.travaglini@arm.com      case MISCREG_CNTHV_CVAL_EL2:
69412816Sgiacomo.travaglini@arm.com      case MISCREG_CNTHV_TVAL_EL2:
69510844Sandreas.sandberg@arm.com      case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
69610844Sandreas.sandberg@arm.com      case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
69710844Sandreas.sandberg@arm.com      case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
69810844Sandreas.sandberg@arm.com      case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
69910844Sandreas.sandberg@arm.com        return getGenericTimer(tc).readMiscReg(misc_reg);
70010844Sandreas.sandberg@arm.com
70113531Sjairo.balart@metempsy.com      case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
70213531Sjairo.balart@metempsy.com      case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
70313531Sjairo.balart@metempsy.com        return getGICv3CPUInterface(tc).readMiscReg(misc_reg);
70413531Sjairo.balart@metempsy.com
70510188Sgeoffrey.blake@arm.com      default:
70610037SARM gem5 Developers        break;
70710037SARM gem5 Developers
7087405SAli.Saidi@ARM.com    }
7097405SAli.Saidi@ARM.com    return readMiscRegNoEffect(misc_reg);
7107405SAli.Saidi@ARM.com}
7117405SAli.Saidi@ARM.com
7127405SAli.Saidi@ARM.comvoid
7137405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
7147405SAli.Saidi@ARM.com{
7157405SAli.Saidi@ARM.com    assert(misc_reg < NumMiscRegs);
7167614Sminkyu.jeong@arm.com
71712478SCurtis.Dunham@arm.com    const auto &reg = lookUpMiscReg[misc_reg]; // bit masks
71812478SCurtis.Dunham@arm.com    const auto &map = getMiscIndices(misc_reg);
71912478SCurtis.Dunham@arm.com    int lower = map.first, upper = map.second;
72012478SCurtis.Dunham@arm.com
72112478SCurtis.Dunham@arm.com    auto v = (val & ~reg.wi()) | reg.rao();
72211771SCurtis.Dunham@arm.com    if (upper > 0) {
72312478SCurtis.Dunham@arm.com        miscRegs[lower] = bits(v, 31, 0);
72412478SCurtis.Dunham@arm.com        miscRegs[upper] = bits(v, 63, 32);
72510037SARM gem5 Developers        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
72612478SCurtis.Dunham@arm.com                misc_reg, lower, upper, v);
72710037SARM gem5 Developers    } else {
72812478SCurtis.Dunham@arm.com        miscRegs[lower] = v;
72910037SARM gem5 Developers        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
73012478SCurtis.Dunham@arm.com                misc_reg, lower, v);
73110037SARM gem5 Developers    }
7327405SAli.Saidi@ARM.com}
7337405SAli.Saidi@ARM.com
7347405SAli.Saidi@ARM.comvoid
7357405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
7367405SAli.Saidi@ARM.com{
7377749SAli.Saidi@ARM.com
7387405SAli.Saidi@ARM.com    MiscReg newVal = val;
73910037SARM gem5 Developers    bool secure_lookup;
74010037SARM gem5 Developers    SCR scr;
7418284SAli.Saidi@ARM.com
7427405SAli.Saidi@ARM.com    if (misc_reg == MISCREG_CPSR) {
7437405SAli.Saidi@ARM.com        updateRegMap(val);
7447749SAli.Saidi@ARM.com
7457749SAli.Saidi@ARM.com
7467749SAli.Saidi@ARM.com        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
7477749SAli.Saidi@ARM.com        int old_mode = old_cpsr.mode;
7487405SAli.Saidi@ARM.com        CPSR cpsr = val;
74912510Sgiacomo.travaglini@arm.com        if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) {
75012406Sgabeblack@google.com            getITBPtr(tc)->invalidateMiscReg();
75112406Sgabeblack@google.com            getDTBPtr(tc)->invalidateMiscReg();
7527749SAli.Saidi@ARM.com        }
7537749SAli.Saidi@ARM.com
7547614Sminkyu.jeong@arm.com        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
7557614Sminkyu.jeong@arm.com                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
7567720Sgblack@eecs.umich.edu        PCState pc = tc->pcState();
7577720Sgblack@eecs.umich.edu        pc.nextThumb(cpsr.t);
7587720Sgblack@eecs.umich.edu        pc.nextJazelle(cpsr.j);
75912763Sgiacomo.travaglini@arm.com        pc.illegalExec(cpsr.il == 1);
7608887Sgeoffrey.blake@arm.com
7618887Sgeoffrey.blake@arm.com        // Follow slightly different semantics if a CheckerCPU object
7628887Sgeoffrey.blake@arm.com        // is connected
7638887Sgeoffrey.blake@arm.com        CheckerCPU *checker = tc->getCheckerCpuPtr();
7648887Sgeoffrey.blake@arm.com        if (checker) {
7658887Sgeoffrey.blake@arm.com            tc->pcStateNoRecord(pc);
7668887Sgeoffrey.blake@arm.com        } else {
7678887Sgeoffrey.blake@arm.com            tc->pcState(pc);
7688887Sgeoffrey.blake@arm.com        }
7697408Sgblack@eecs.umich.edu    } else {
77010037SARM gem5 Developers#ifndef NDEBUG
77110037SARM gem5 Developers        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
77210037SARM gem5 Developers            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
77310037SARM gem5 Developers                warn("Unimplemented system register %s write with %#x.\n",
77410037SARM gem5 Developers                    miscRegName[misc_reg], val);
77510037SARM gem5 Developers            else
77610037SARM gem5 Developers                panic("Unimplemented system register %s write with %#x.\n",
77710037SARM gem5 Developers                    miscRegName[misc_reg], val);
77810037SARM gem5 Developers        }
77910037SARM gem5 Developers#endif
78010037SARM gem5 Developers        switch (unflattenMiscReg(misc_reg)) {
7817408Sgblack@eecs.umich.edu          case MISCREG_CPACR:
7827408Sgblack@eecs.umich.edu            {
7838206SWilliam.Wang@arm.com
7848206SWilliam.Wang@arm.com                const uint32_t ones = (uint32_t)(-1);
7858206SWilliam.Wang@arm.com                CPACR cpacrMask = 0;
7868206SWilliam.Wang@arm.com                // Only cp10, cp11, and ase are implemented, nothing else should
7878206SWilliam.Wang@arm.com                // be writable
7888206SWilliam.Wang@arm.com                cpacrMask.cp10 = ones;
7898206SWilliam.Wang@arm.com                cpacrMask.cp11 = ones;
7908206SWilliam.Wang@arm.com                cpacrMask.asedis = ones;
79110037SARM gem5 Developers
79210037SARM gem5 Developers                // Security Extensions may limit the writability of CPACR
79310037SARM gem5 Developers                if (haveSecurity) {
79410037SARM gem5 Developers                    scr = readMiscRegNoEffect(MISCREG_SCR);
79510037SARM gem5 Developers                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
79612667Schuan.zhu@arm.com                    if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) {
79710037SARM gem5 Developers                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
79810037SARM gem5 Developers                        // NB: Skipping the full loop, here
79910037SARM gem5 Developers                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
80010037SARM gem5 Developers                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
80110037SARM gem5 Developers                    }
80210037SARM gem5 Developers                }
80310037SARM gem5 Developers
80410037SARM gem5 Developers                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
8058206SWilliam.Wang@arm.com                newVal &= cpacrMask;
80610037SARM gem5 Developers                newVal |= old_val & ~cpacrMask;
80710037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
80810037SARM gem5 Developers                        miscRegName[misc_reg], newVal);
80910037SARM gem5 Developers            }
81010037SARM gem5 Developers            break;
81110037SARM gem5 Developers          case MISCREG_CPTR_EL2:
81210037SARM gem5 Developers            {
81310037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
81410037SARM gem5 Developers                CPTR cptrMask = 0;
81510037SARM gem5 Developers                cptrMask.tcpac = ones;
81610037SARM gem5 Developers                cptrMask.tta = ones;
81710037SARM gem5 Developers                cptrMask.tfp = ones;
81810037SARM gem5 Developers                newVal &= cptrMask;
81910037SARM gem5 Developers                cptrMask = 0;
82010037SARM gem5 Developers                cptrMask.res1_13_12_el2 = ones;
82110037SARM gem5 Developers                cptrMask.res1_9_0_el2 = ones;
82210037SARM gem5 Developers                newVal |= cptrMask;
82310037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
82410037SARM gem5 Developers                        miscRegName[misc_reg], newVal);
82510037SARM gem5 Developers            }
82610037SARM gem5 Developers            break;
82710037SARM gem5 Developers          case MISCREG_CPTR_EL3:
82810037SARM gem5 Developers            {
82910037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
83010037SARM gem5 Developers                CPTR cptrMask = 0;
83110037SARM gem5 Developers                cptrMask.tcpac = ones;
83210037SARM gem5 Developers                cptrMask.tta = ones;
83310037SARM gem5 Developers                cptrMask.tfp = ones;
83410037SARM gem5 Developers                newVal &= cptrMask;
8358206SWilliam.Wang@arm.com                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
8368206SWilliam.Wang@arm.com                        miscRegName[misc_reg], newVal);
8377408Sgblack@eecs.umich.edu            }
8387408Sgblack@eecs.umich.edu            break;
8397408Sgblack@eecs.umich.edu          case MISCREG_CSSELR:
8407731SAli.Saidi@ARM.com            warn_once("The csselr register isn't implemented.\n");
8418206SWilliam.Wang@arm.com            return;
84210037SARM gem5 Developers
84310037SARM gem5 Developers          case MISCREG_DC_ZVA_Xt:
84410037SARM gem5 Developers            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
84510037SARM gem5 Developers            return;
84610037SARM gem5 Developers
8477408Sgblack@eecs.umich.edu          case MISCREG_FPSCR:
8487408Sgblack@eecs.umich.edu            {
8497408Sgblack@eecs.umich.edu                const uint32_t ones = (uint32_t)(-1);
8507408Sgblack@eecs.umich.edu                FPSCR fpscrMask = 0;
8517408Sgblack@eecs.umich.edu                fpscrMask.ioc = ones;
8527408Sgblack@eecs.umich.edu                fpscrMask.dzc = ones;
8537408Sgblack@eecs.umich.edu                fpscrMask.ofc = ones;
8547408Sgblack@eecs.umich.edu                fpscrMask.ufc = ones;
8557408Sgblack@eecs.umich.edu                fpscrMask.ixc = ones;
8567408Sgblack@eecs.umich.edu                fpscrMask.idc = ones;
85710037SARM gem5 Developers                fpscrMask.ioe = ones;
85810037SARM gem5 Developers                fpscrMask.dze = ones;
85910037SARM gem5 Developers                fpscrMask.ofe = ones;
86010037SARM gem5 Developers                fpscrMask.ufe = ones;
86110037SARM gem5 Developers                fpscrMask.ixe = ones;
86210037SARM gem5 Developers                fpscrMask.ide = ones;
8637408Sgblack@eecs.umich.edu                fpscrMask.len = ones;
8647408Sgblack@eecs.umich.edu                fpscrMask.stride = ones;
8657408Sgblack@eecs.umich.edu                fpscrMask.rMode = ones;
8667408Sgblack@eecs.umich.edu                fpscrMask.fz = ones;
8677408Sgblack@eecs.umich.edu                fpscrMask.dn = ones;
8687408Sgblack@eecs.umich.edu                fpscrMask.ahp = ones;
8697408Sgblack@eecs.umich.edu                fpscrMask.qc = ones;
8707408Sgblack@eecs.umich.edu                fpscrMask.v = ones;
8717408Sgblack@eecs.umich.edu                fpscrMask.c = ones;
8727408Sgblack@eecs.umich.edu                fpscrMask.z = ones;
8737408Sgblack@eecs.umich.edu                fpscrMask.n = ones;
8747408Sgblack@eecs.umich.edu                newVal = (newVal & (uint32_t)fpscrMask) |
87510037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
87610037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
8779377Sgblack@eecs.umich.edu                tc->getDecoderPtr()->setContext(newVal);
8787408Sgblack@eecs.umich.edu            }
8797408Sgblack@eecs.umich.edu            break;
88010037SARM gem5 Developers          case MISCREG_FPSR:
88110037SARM gem5 Developers            {
88210037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
88310037SARM gem5 Developers                FPSCR fpscrMask = 0;
88410037SARM gem5 Developers                fpscrMask.ioc = ones;
88510037SARM gem5 Developers                fpscrMask.dzc = ones;
88610037SARM gem5 Developers                fpscrMask.ofc = ones;
88710037SARM gem5 Developers                fpscrMask.ufc = ones;
88810037SARM gem5 Developers                fpscrMask.ixc = ones;
88910037SARM gem5 Developers                fpscrMask.idc = ones;
89010037SARM gem5 Developers                fpscrMask.qc = ones;
89110037SARM gem5 Developers                fpscrMask.v = ones;
89210037SARM gem5 Developers                fpscrMask.c = ones;
89310037SARM gem5 Developers                fpscrMask.z = ones;
89410037SARM gem5 Developers                fpscrMask.n = ones;
89510037SARM gem5 Developers                newVal = (newVal & (uint32_t)fpscrMask) |
89610037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
89710037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
89810037SARM gem5 Developers                misc_reg = MISCREG_FPSCR;
89910037SARM gem5 Developers            }
90010037SARM gem5 Developers            break;
90110037SARM gem5 Developers          case MISCREG_FPCR:
90210037SARM gem5 Developers            {
90310037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
90410037SARM gem5 Developers                FPSCR fpscrMask  = 0;
90510037SARM gem5 Developers                fpscrMask.len    = ones;
90610037SARM gem5 Developers                fpscrMask.stride = ones;
90710037SARM gem5 Developers                fpscrMask.rMode  = ones;
90810037SARM gem5 Developers                fpscrMask.fz     = ones;
90910037SARM gem5 Developers                fpscrMask.dn     = ones;
91010037SARM gem5 Developers                fpscrMask.ahp    = ones;
91110037SARM gem5 Developers                newVal = (newVal & (uint32_t)fpscrMask) |
91210037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
91310037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
91410037SARM gem5 Developers                misc_reg = MISCREG_FPSCR;
91510037SARM gem5 Developers            }
91610037SARM gem5 Developers            break;
9178302SAli.Saidi@ARM.com          case MISCREG_CPSR_Q:
9188302SAli.Saidi@ARM.com            {
9198302SAli.Saidi@ARM.com                assert(!(newVal & ~CpsrMaskQ));
92010037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
9218302SAli.Saidi@ARM.com                misc_reg = MISCREG_CPSR;
9228302SAli.Saidi@ARM.com            }
9238302SAli.Saidi@ARM.com            break;
9247783SGiacomo.Gabrielli@arm.com          case MISCREG_FPSCR_QC:
9257783SGiacomo.Gabrielli@arm.com            {
92610037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
92710037SARM gem5 Developers                         (newVal & FpscrQcMask);
9287783SGiacomo.Gabrielli@arm.com                misc_reg = MISCREG_FPSCR;
9297783SGiacomo.Gabrielli@arm.com            }
9307783SGiacomo.Gabrielli@arm.com            break;
9317783SGiacomo.Gabrielli@arm.com          case MISCREG_FPSCR_EXC:
9327783SGiacomo.Gabrielli@arm.com            {
93310037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
93410037SARM gem5 Developers                         (newVal & FpscrExcMask);
9357783SGiacomo.Gabrielli@arm.com                misc_reg = MISCREG_FPSCR;
9367783SGiacomo.Gabrielli@arm.com            }
9377783SGiacomo.Gabrielli@arm.com            break;
9387408Sgblack@eecs.umich.edu          case MISCREG_FPEXC:
9397408Sgblack@eecs.umich.edu            {
9408206SWilliam.Wang@arm.com                // vfpv3 architecture, section B.6.1 of DDI04068
9418206SWilliam.Wang@arm.com                // bit 29 - valid only if fpexc[31] is 0
9427408Sgblack@eecs.umich.edu                const uint32_t fpexcMask = 0x60000000;
9437408Sgblack@eecs.umich.edu                newVal = (newVal & fpexcMask) |
94410037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
9457408Sgblack@eecs.umich.edu            }
9467408Sgblack@eecs.umich.edu            break;
94710037SARM gem5 Developers          case MISCREG_HCR:
94810037SARM gem5 Developers            {
94910037SARM gem5 Developers                if (!haveVirtualization)
95010037SARM gem5 Developers                    return;
95110037SARM gem5 Developers            }
95210037SARM gem5 Developers            break;
95310037SARM gem5 Developers          case MISCREG_IFSR:
95410037SARM gem5 Developers            {
95510037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.96
95610037SARM gem5 Developers                const uint32_t ifsrMask =
95710037SARM gem5 Developers                    mask(31, 13) | mask(11, 11) | mask(8, 6);
95810037SARM gem5 Developers                newVal = newVal & ~ifsrMask;
95910037SARM gem5 Developers            }
96010037SARM gem5 Developers            break;
96110037SARM gem5 Developers          case MISCREG_DFSR:
96210037SARM gem5 Developers            {
96310037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.52
96410037SARM gem5 Developers                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
96510037SARM gem5 Developers                newVal = newVal & ~dfsrMask;
96610037SARM gem5 Developers            }
96710037SARM gem5 Developers            break;
96810037SARM gem5 Developers          case MISCREG_AMAIR0:
96910037SARM gem5 Developers          case MISCREG_AMAIR1:
97010037SARM gem5 Developers            {
97110037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.5
97210037SARM gem5 Developers                // Valid only with LPAE
97310037SARM gem5 Developers                if (!haveLPAE)
97410037SARM gem5 Developers                    return;
97510037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
97610037SARM gem5 Developers            }
97710037SARM gem5 Developers            break;
97810037SARM gem5 Developers          case MISCREG_SCR:
97912406Sgabeblack@google.com            getITBPtr(tc)->invalidateMiscReg();
98012406Sgabeblack@google.com            getDTBPtr(tc)->invalidateMiscReg();
98110037SARM gem5 Developers            break;
9827408Sgblack@eecs.umich.edu          case MISCREG_SCTLR:
9837408Sgblack@eecs.umich.edu            {
9847408Sgblack@eecs.umich.edu                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
98510037SARM gem5 Developers                scr = readMiscRegNoEffect(MISCREG_SCR);
98612639Sgiacomo.travaglini@arm.com
98712639Sgiacomo.travaglini@arm.com                MiscRegIndex sctlr_idx;
98812639Sgiacomo.travaglini@arm.com                if (haveSecurity && !highestELIs64 && !scr.ns) {
98912639Sgiacomo.travaglini@arm.com                    sctlr_idx = MISCREG_SCTLR_S;
99012639Sgiacomo.travaglini@arm.com                } else {
99112639Sgiacomo.travaglini@arm.com                    sctlr_idx =  MISCREG_SCTLR_NS;
99212639Sgiacomo.travaglini@arm.com                }
99312639Sgiacomo.travaglini@arm.com
99410037SARM gem5 Developers                SCTLR sctlr = miscRegs[sctlr_idx];
9957408Sgblack@eecs.umich.edu                SCTLR new_sctlr = newVal;
99610037SARM gem5 Developers                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
99710037SARM gem5 Developers                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
99812406Sgabeblack@google.com                getITBPtr(tc)->invalidateMiscReg();
99912406Sgabeblack@google.com                getDTBPtr(tc)->invalidateMiscReg();
10007408Sgblack@eecs.umich.edu            }
10019385SAndreas.Sandberg@arm.com          case MISCREG_MIDR:
10029385SAndreas.Sandberg@arm.com          case MISCREG_ID_PFR0:
10039385SAndreas.Sandberg@arm.com          case MISCREG_ID_PFR1:
100410461SAndreas.Sandberg@ARM.com          case MISCREG_ID_DFR0:
10059385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR0:
10069385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR1:
10079385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR2:
10089385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR3:
10099385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR0:
10109385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR1:
10119385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR2:
10129385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR3:
10139385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR4:
10149385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR5:
10159385SAndreas.Sandberg@arm.com
10169385SAndreas.Sandberg@arm.com          case MISCREG_MPIDR:
10179385SAndreas.Sandberg@arm.com          case MISCREG_FPSID:
10187408Sgblack@eecs.umich.edu          case MISCREG_TLBTR:
10197408Sgblack@eecs.umich.edu          case MISCREG_MVFR0:
10207408Sgblack@eecs.umich.edu          case MISCREG_MVFR1:
102110037SARM gem5 Developers
102210037SARM gem5 Developers          case MISCREG_ID_AA64AFR0_EL1:
102310037SARM gem5 Developers          case MISCREG_ID_AA64AFR1_EL1:
102410037SARM gem5 Developers          case MISCREG_ID_AA64DFR0_EL1:
102510037SARM gem5 Developers          case MISCREG_ID_AA64DFR1_EL1:
102610037SARM gem5 Developers          case MISCREG_ID_AA64ISAR0_EL1:
102710037SARM gem5 Developers          case MISCREG_ID_AA64ISAR1_EL1:
102810037SARM gem5 Developers          case MISCREG_ID_AA64MMFR0_EL1:
102910037SARM gem5 Developers          case MISCREG_ID_AA64MMFR1_EL1:
103013116Sgiacomo.travaglini@arm.com          case MISCREG_ID_AA64MMFR2_EL1:
103110037SARM gem5 Developers          case MISCREG_ID_AA64PFR0_EL1:
103210037SARM gem5 Developers          case MISCREG_ID_AA64PFR1_EL1:
10339385SAndreas.Sandberg@arm.com            // ID registers are constants.
10347408Sgblack@eecs.umich.edu            return;
10359385SAndreas.Sandberg@arm.com
103612605Sgiacomo.travaglini@arm.com          // TLB Invalidate All
103712605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
103812605Sgiacomo.travaglini@arm.com            {
103912605Sgiacomo.travaglini@arm.com                assert32(tc);
104012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
104112605Sgiacomo.travaglini@arm.com
104212605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
104312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
104412605Sgiacomo.travaglini@arm.com                return;
104512605Sgiacomo.travaglini@arm.com            }
104612605Sgiacomo.travaglini@arm.com          // TLB Invalidate All, Inner Shareable
10477408Sgblack@eecs.umich.edu          case MISCREG_TLBIALLIS:
104812605Sgiacomo.travaglini@arm.com            {
104912605Sgiacomo.travaglini@arm.com                assert32(tc);
105012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
105112605Sgiacomo.travaglini@arm.com
105212605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
105312605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
105412605Sgiacomo.travaglini@arm.com                return;
105512605Sgiacomo.travaglini@arm.com            }
105612605Sgiacomo.travaglini@arm.com          // Instruction TLB Invalidate All
10577408Sgblack@eecs.umich.edu          case MISCREG_ITLBIALL:
105812605Sgiacomo.travaglini@arm.com            {
105912605Sgiacomo.travaglini@arm.com                assert32(tc);
106012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
106112605Sgiacomo.travaglini@arm.com
106212605Sgiacomo.travaglini@arm.com                ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
106312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
106412605Sgiacomo.travaglini@arm.com                return;
106512605Sgiacomo.travaglini@arm.com            }
106612605Sgiacomo.travaglini@arm.com          // Data TLB Invalidate All
10677408Sgblack@eecs.umich.edu          case MISCREG_DTLBIALL:
106812605Sgiacomo.travaglini@arm.com            {
106912605Sgiacomo.travaglini@arm.com                assert32(tc);
107012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
107112605Sgiacomo.travaglini@arm.com
107212605Sgiacomo.travaglini@arm.com                DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
107312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
107412605Sgiacomo.travaglini@arm.com                return;
107512605Sgiacomo.travaglini@arm.com            }
107612605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA
107712605Sgiacomo.travaglini@arm.com          // mcr tlbimval(is) is invalidating all matching entries
107812605Sgiacomo.travaglini@arm.com          // regardless of the level of lookup, since in gem5 we cache
107912605Sgiacomo.travaglini@arm.com          // in the tlb the last level of lookup only.
108012605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVA:
108112576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAL:
108212605Sgiacomo.travaglini@arm.com            {
108312605Sgiacomo.travaglini@arm.com                assert32(tc);
108412605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
108512605Sgiacomo.travaglini@arm.com
108612605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL1,
108712605Sgiacomo.travaglini@arm.com                               haveSecurity && !scr.ns,
108812605Sgiacomo.travaglini@arm.com                               mbits(newVal, 31, 12),
108912605Sgiacomo.travaglini@arm.com                               bits(newVal, 7,0));
109012605Sgiacomo.travaglini@arm.com
109112605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
109212605Sgiacomo.travaglini@arm.com                return;
109312605Sgiacomo.travaglini@arm.com            }
109412605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA, Inner Shareable
109512605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAIS:
109612576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVALIS:
109712605Sgiacomo.travaglini@arm.com            {
109812605Sgiacomo.travaglini@arm.com                assert32(tc);
109912605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
110012605Sgiacomo.travaglini@arm.com
110112605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL1,
110212605Sgiacomo.travaglini@arm.com                               haveSecurity && !scr.ns,
110312605Sgiacomo.travaglini@arm.com                               mbits(newVal, 31, 12),
110412605Sgiacomo.travaglini@arm.com                               bits(newVal, 7,0));
110512605Sgiacomo.travaglini@arm.com
110612605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
110712605Sgiacomo.travaglini@arm.com                return;
110812605Sgiacomo.travaglini@arm.com            }
110912605Sgiacomo.travaglini@arm.com          // TLB Invalidate by ASID match
111012605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIASID:
111112605Sgiacomo.travaglini@arm.com            {
111212605Sgiacomo.travaglini@arm.com                assert32(tc);
111312605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
111412605Sgiacomo.travaglini@arm.com
111512605Sgiacomo.travaglini@arm.com                TLBIASID tlbiOp(EL1,
111612605Sgiacomo.travaglini@arm.com                                haveSecurity && !scr.ns,
111712605Sgiacomo.travaglini@arm.com                                bits(newVal, 7,0));
111812605Sgiacomo.travaglini@arm.com
111912605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
112012605Sgiacomo.travaglini@arm.com                return;
112112605Sgiacomo.travaglini@arm.com            }
112212605Sgiacomo.travaglini@arm.com          // TLB Invalidate by ASID match, Inner Shareable
11237408Sgblack@eecs.umich.edu          case MISCREG_TLBIASIDIS:
112412605Sgiacomo.travaglini@arm.com            {
112512605Sgiacomo.travaglini@arm.com                assert32(tc);
112612605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
112712605Sgiacomo.travaglini@arm.com
112812605Sgiacomo.travaglini@arm.com                TLBIASID tlbiOp(EL1,
112912605Sgiacomo.travaglini@arm.com                                haveSecurity && !scr.ns,
113012605Sgiacomo.travaglini@arm.com                                bits(newVal, 7,0));
113112605Sgiacomo.travaglini@arm.com
113212605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
113312605Sgiacomo.travaglini@arm.com                return;
113412605Sgiacomo.travaglini@arm.com            }
113512605Sgiacomo.travaglini@arm.com          // mcr tlbimvaal(is) is invalidating all matching entries
113612605Sgiacomo.travaglini@arm.com          // regardless of the level of lookup, since in gem5 we cache
113712605Sgiacomo.travaglini@arm.com          // in the tlb the last level of lookup only.
113812605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA, All ASID
113912605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAA:
114012576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAAL:
114112605Sgiacomo.travaglini@arm.com            {
114212605Sgiacomo.travaglini@arm.com                assert32(tc);
114312605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
114412605Sgiacomo.travaglini@arm.com
114512605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
114612605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31,12), false);
114712605Sgiacomo.travaglini@arm.com
114812605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
114912605Sgiacomo.travaglini@arm.com                return;
115012605Sgiacomo.travaglini@arm.com            }
115112605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA, All ASID, Inner Shareable
115212605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAAIS:
115312576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAALIS:
115412605Sgiacomo.travaglini@arm.com            {
115512605Sgiacomo.travaglini@arm.com                assert32(tc);
115612605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
115712605Sgiacomo.travaglini@arm.com
115812605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
115912605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31,12), false);
116012605Sgiacomo.travaglini@arm.com
116112605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
116212605Sgiacomo.travaglini@arm.com                return;
116312605Sgiacomo.travaglini@arm.com            }
116412605Sgiacomo.travaglini@arm.com          // mcr tlbimvalh(is) is invalidating all matching entries
116512605Sgiacomo.travaglini@arm.com          // regardless of the level of lookup, since in gem5 we cache
116612605Sgiacomo.travaglini@arm.com          // in the tlb the last level of lookup only.
116712605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA, Hyp mode
116812605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAH:
116912576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVALH:
117012605Sgiacomo.travaglini@arm.com            {
117112605Sgiacomo.travaglini@arm.com                assert32(tc);
117212605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
117312605Sgiacomo.travaglini@arm.com
117412605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
117512605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31,12), true);
117612605Sgiacomo.travaglini@arm.com
117712605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
117812605Sgiacomo.travaglini@arm.com                return;
117912605Sgiacomo.travaglini@arm.com            }
118012605Sgiacomo.travaglini@arm.com          // TLB Invalidate by VA, Hyp mode, Inner Shareable
118112605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVAHIS:
118212576Sgiacomo.travaglini@arm.com          case MISCREG_TLBIMVALHIS:
118312605Sgiacomo.travaglini@arm.com            {
118412605Sgiacomo.travaglini@arm.com                assert32(tc);
118512605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
118612605Sgiacomo.travaglini@arm.com
118712605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
118812605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31,12), true);
118912605Sgiacomo.travaglini@arm.com
119012605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
119112605Sgiacomo.travaglini@arm.com                return;
119212605Sgiacomo.travaglini@arm.com            }
119312605Sgiacomo.travaglini@arm.com          // mcr tlbiipas2l(is) is invalidating all matching entries
119412605Sgiacomo.travaglini@arm.com          // regardless of the level of lookup, since in gem5 we cache
119512605Sgiacomo.travaglini@arm.com          // in the tlb the last level of lookup only.
119612605Sgiacomo.travaglini@arm.com          // TLB Invalidate by Intermediate Physical Address, Stage 2
119712605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIIPAS2:
119812577Sgiacomo.travaglini@arm.com          case MISCREG_TLBIIPAS2L:
119912605Sgiacomo.travaglini@arm.com            {
120012605Sgiacomo.travaglini@arm.com                assert32(tc);
120112605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
120212605Sgiacomo.travaglini@arm.com
120312605Sgiacomo.travaglini@arm.com                TLBIIPA tlbiOp(EL1,
120412605Sgiacomo.travaglini@arm.com                               haveSecurity && !scr.ns,
120512605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
120612605Sgiacomo.travaglini@arm.com
120712605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
120812605Sgiacomo.travaglini@arm.com                return;
120912605Sgiacomo.travaglini@arm.com            }
121012605Sgiacomo.travaglini@arm.com          // TLB Invalidate by Intermediate Physical Address, Stage 2,
121112605Sgiacomo.travaglini@arm.com          // Inner Shareable
121212605Sgiacomo.travaglini@arm.com          case MISCREG_TLBIIPAS2IS:
121312577Sgiacomo.travaglini@arm.com          case MISCREG_TLBIIPAS2LIS:
121412605Sgiacomo.travaglini@arm.com            {
121512605Sgiacomo.travaglini@arm.com                assert32(tc);
121612605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
121712605Sgiacomo.travaglini@arm.com
121812605Sgiacomo.travaglini@arm.com                TLBIIPA tlbiOp(EL1,
121912605Sgiacomo.travaglini@arm.com                               haveSecurity && !scr.ns,
122012605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
122112605Sgiacomo.travaglini@arm.com
122212605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
122312605Sgiacomo.travaglini@arm.com                return;
122412605Sgiacomo.travaglini@arm.com            }
122512605Sgiacomo.travaglini@arm.com          // Instruction TLB Invalidate by VA
122610037SARM gem5 Developers          case MISCREG_ITLBIMVA:
122712605Sgiacomo.travaglini@arm.com            {
122812605Sgiacomo.travaglini@arm.com                assert32(tc);
122912605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
123012605Sgiacomo.travaglini@arm.com
123112605Sgiacomo.travaglini@arm.com                ITLBIMVA tlbiOp(EL1,
123212605Sgiacomo.travaglini@arm.com                                haveSecurity && !scr.ns,
123312605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31, 12),
123412605Sgiacomo.travaglini@arm.com                                bits(newVal, 7,0));
123512605Sgiacomo.travaglini@arm.com
123612605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
123712605Sgiacomo.travaglini@arm.com                return;
123812605Sgiacomo.travaglini@arm.com            }
123912605Sgiacomo.travaglini@arm.com          // Data TLB Invalidate by VA
124010037SARM gem5 Developers          case MISCREG_DTLBIMVA:
124112605Sgiacomo.travaglini@arm.com            {
124212605Sgiacomo.travaglini@arm.com                assert32(tc);
124312605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
124412605Sgiacomo.travaglini@arm.com
124512605Sgiacomo.travaglini@arm.com                DTLBIMVA tlbiOp(EL1,
124612605Sgiacomo.travaglini@arm.com                                haveSecurity && !scr.ns,
124712605Sgiacomo.travaglini@arm.com                                mbits(newVal, 31, 12),
124812605Sgiacomo.travaglini@arm.com                                bits(newVal, 7,0));
124912605Sgiacomo.travaglini@arm.com
125012605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
125112605Sgiacomo.travaglini@arm.com                return;
125212605Sgiacomo.travaglini@arm.com            }
125312605Sgiacomo.travaglini@arm.com          // Instruction TLB Invalidate by ASID match
125410037SARM gem5 Developers          case MISCREG_ITLBIASID:
125512605Sgiacomo.travaglini@arm.com            {
125612605Sgiacomo.travaglini@arm.com                assert32(tc);
125712605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
125812605Sgiacomo.travaglini@arm.com
125912605Sgiacomo.travaglini@arm.com                ITLBIASID tlbiOp(EL1,
126012605Sgiacomo.travaglini@arm.com                                 haveSecurity && !scr.ns,
126112605Sgiacomo.travaglini@arm.com                                 bits(newVal, 7,0));
126212605Sgiacomo.travaglini@arm.com
126312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
126412605Sgiacomo.travaglini@arm.com                return;
126512605Sgiacomo.travaglini@arm.com            }
126612605Sgiacomo.travaglini@arm.com          // Data TLB Invalidate by ASID match
126710037SARM gem5 Developers          case MISCREG_DTLBIASID:
126812605Sgiacomo.travaglini@arm.com            {
126912605Sgiacomo.travaglini@arm.com                assert32(tc);
127012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
127112605Sgiacomo.travaglini@arm.com
127212605Sgiacomo.travaglini@arm.com                DTLBIASID tlbiOp(EL1,
127312605Sgiacomo.travaglini@arm.com                                 haveSecurity && !scr.ns,
127412605Sgiacomo.travaglini@arm.com                                 bits(newVal, 7,0));
127512605Sgiacomo.travaglini@arm.com
127612605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
127712605Sgiacomo.travaglini@arm.com                return;
127812605Sgiacomo.travaglini@arm.com            }
127912605Sgiacomo.travaglini@arm.com          // TLB Invalidate All, Non-Secure Non-Hyp
128010037SARM gem5 Developers          case MISCREG_TLBIALLNSNH:
128112605Sgiacomo.travaglini@arm.com            {
128212605Sgiacomo.travaglini@arm.com                assert32(tc);
128312605Sgiacomo.travaglini@arm.com
128412605Sgiacomo.travaglini@arm.com                TLBIALLN tlbiOp(EL1, false);
128512605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
128612605Sgiacomo.travaglini@arm.com                return;
128712605Sgiacomo.travaglini@arm.com            }
128812605Sgiacomo.travaglini@arm.com          // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable
128910037SARM gem5 Developers          case MISCREG_TLBIALLNSNHIS:
129012605Sgiacomo.travaglini@arm.com            {
129112605Sgiacomo.travaglini@arm.com                assert32(tc);
129212605Sgiacomo.travaglini@arm.com
129312605Sgiacomo.travaglini@arm.com                TLBIALLN tlbiOp(EL1, false);
129412605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
129512605Sgiacomo.travaglini@arm.com                return;
129612605Sgiacomo.travaglini@arm.com            }
129712605Sgiacomo.travaglini@arm.com          // TLB Invalidate All, Hyp mode
129810037SARM gem5 Developers          case MISCREG_TLBIALLH:
129912605Sgiacomo.travaglini@arm.com            {
130012605Sgiacomo.travaglini@arm.com                assert32(tc);
130112605Sgiacomo.travaglini@arm.com
130212605Sgiacomo.travaglini@arm.com                TLBIALLN tlbiOp(EL1, true);
130312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
130412605Sgiacomo.travaglini@arm.com                return;
130512605Sgiacomo.travaglini@arm.com            }
130612605Sgiacomo.travaglini@arm.com          // TLB Invalidate All, Hyp mode, Inner Shareable
130710037SARM gem5 Developers          case MISCREG_TLBIALLHIS:
130812605Sgiacomo.travaglini@arm.com            {
130912605Sgiacomo.travaglini@arm.com                assert32(tc);
131012605Sgiacomo.travaglini@arm.com
131112605Sgiacomo.travaglini@arm.com                TLBIALLN tlbiOp(EL1, true);
131212605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
131312605Sgiacomo.travaglini@arm.com                return;
131412605Sgiacomo.travaglini@arm.com            }
131512605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate All, EL3
131612605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_ALLE3:
131712605Sgiacomo.travaglini@arm.com            {
131812605Sgiacomo.travaglini@arm.com                assert64(tc);
131912605Sgiacomo.travaglini@arm.com
132012605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL3, true);
132112605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
132212605Sgiacomo.travaglini@arm.com                return;
132312605Sgiacomo.travaglini@arm.com            }
132412605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate All, EL3, Inner Shareable
132510037SARM gem5 Developers          case MISCREG_TLBI_ALLE3IS:
132612605Sgiacomo.travaglini@arm.com            {
132712605Sgiacomo.travaglini@arm.com                assert64(tc);
132812605Sgiacomo.travaglini@arm.com
132912605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL3, true);
133012605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
133112605Sgiacomo.travaglini@arm.com                return;
133212605Sgiacomo.travaglini@arm.com            }
133313549Sanouk.vanlaer@arm.com          // AArch64 TLB Invalidate All, EL2, Inner Shareable
133413549Sanouk.vanlaer@arm.com          case MISCREG_TLBI_ALLE2:
133513549Sanouk.vanlaer@arm.com          case MISCREG_TLBI_ALLE2IS:
133613549Sanouk.vanlaer@arm.com            {
133713549Sanouk.vanlaer@arm.com                assert64(tc);
133813549Sanouk.vanlaer@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
133913549Sanouk.vanlaer@arm.com
134013549Sanouk.vanlaer@arm.com                TLBIALL tlbiOp(EL2, haveSecurity && !scr.ns);
134113549Sanouk.vanlaer@arm.com                tlbiOp(tc);
134213549Sanouk.vanlaer@arm.com                return;
134313549Sanouk.vanlaer@arm.com            }
134412605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate All, EL1
134510037SARM gem5 Developers          case MISCREG_TLBI_ALLE1:
134610037SARM gem5 Developers          case MISCREG_TLBI_VMALLE1:
134710037SARM gem5 Developers          case MISCREG_TLBI_VMALLS12E1:
134810037SARM gem5 Developers            // @todo: handle VMID and stage 2 to enable Virtualization
134912605Sgiacomo.travaglini@arm.com            {
135012605Sgiacomo.travaglini@arm.com                assert64(tc);
135112605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
135212605Sgiacomo.travaglini@arm.com
135312605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
135412605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
135512605Sgiacomo.travaglini@arm.com                return;
135612605Sgiacomo.travaglini@arm.com            }
135712605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate All, EL1, Inner Shareable
135812605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_ALLE1IS:
135912605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VMALLE1IS:
136012605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VMALLS12E1IS:
136112605Sgiacomo.travaglini@arm.com            // @todo: handle VMID and stage 2 to enable Virtualization
136212605Sgiacomo.travaglini@arm.com            {
136312605Sgiacomo.travaglini@arm.com                assert64(tc);
136412605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
136512605Sgiacomo.travaglini@arm.com
136612605Sgiacomo.travaglini@arm.com                TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns);
136712605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
136812605Sgiacomo.travaglini@arm.com                return;
136912605Sgiacomo.travaglini@arm.com            }
137012605Sgiacomo.travaglini@arm.com          // VAEx(IS) and VALEx(IS) are the same because TLBs
137112605Sgiacomo.travaglini@arm.com          // only store entries
137210037SARM gem5 Developers          // from the last level of translation table walks
137310037SARM gem5 Developers          // @todo: handle VMID to enable Virtualization
137412605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL3
137512605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VAE3_Xt:
137612605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VALE3_Xt:
137712605Sgiacomo.travaglini@arm.com            {
137812605Sgiacomo.travaglini@arm.com                assert64(tc);
137912605Sgiacomo.travaglini@arm.com
138012605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL3, true,
138112605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
138212605Sgiacomo.travaglini@arm.com                               0xbeef);
138312605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
138412605Sgiacomo.travaglini@arm.com                return;
138512605Sgiacomo.travaglini@arm.com            }
138612605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL3, Inner Shareable
138710037SARM gem5 Developers          case MISCREG_TLBI_VAE3IS_Xt:
138810037SARM gem5 Developers          case MISCREG_TLBI_VALE3IS_Xt:
138912605Sgiacomo.travaglini@arm.com            {
139012605Sgiacomo.travaglini@arm.com                assert64(tc);
139112605Sgiacomo.travaglini@arm.com
139212605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL3, true,
139312605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
139412605Sgiacomo.travaglini@arm.com                               0xbeef);
139512605Sgiacomo.travaglini@arm.com
139612605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
139712605Sgiacomo.travaglini@arm.com                return;
139812605Sgiacomo.travaglini@arm.com            }
139912605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL2
140012605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VAE2_Xt:
140112605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VALE2_Xt:
140212605Sgiacomo.travaglini@arm.com            {
140312605Sgiacomo.travaglini@arm.com                assert64(tc);
140412605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
140512605Sgiacomo.travaglini@arm.com
140612605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
140712605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
140812605Sgiacomo.travaglini@arm.com                               0xbeef);
140912605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
141012605Sgiacomo.travaglini@arm.com                return;
141112605Sgiacomo.travaglini@arm.com            }
141212605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL2, Inner Shareable
141310037SARM gem5 Developers          case MISCREG_TLBI_VAE2IS_Xt:
141410037SARM gem5 Developers          case MISCREG_TLBI_VALE2IS_Xt:
141512605Sgiacomo.travaglini@arm.com            {
141612605Sgiacomo.travaglini@arm.com                assert64(tc);
141712605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
141812605Sgiacomo.travaglini@arm.com
141912605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns,
142012605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
142112605Sgiacomo.travaglini@arm.com                               0xbeef);
142212605Sgiacomo.travaglini@arm.com
142312605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
142412605Sgiacomo.travaglini@arm.com                return;
142512605Sgiacomo.travaglini@arm.com            }
142612605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL1
142712605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VAE1_Xt:
142812605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VALE1_Xt:
142912605Sgiacomo.travaglini@arm.com            {
143012605Sgiacomo.travaglini@arm.com                assert64(tc);
143112605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
143212605Sgiacomo.travaglini@arm.com                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
143312605Sgiacomo.travaglini@arm.com                                              bits(newVal, 55, 48);
143412605Sgiacomo.travaglini@arm.com
143512605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
143612605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
143712605Sgiacomo.travaglini@arm.com                               asid);
143812605Sgiacomo.travaglini@arm.com
143912605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
144012605Sgiacomo.travaglini@arm.com                return;
144112605Sgiacomo.travaglini@arm.com            }
144212605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, EL1, Inner Shareable
144310037SARM gem5 Developers          case MISCREG_TLBI_VAE1IS_Xt:
144410037SARM gem5 Developers          case MISCREG_TLBI_VALE1IS_Xt:
144512605Sgiacomo.travaglini@arm.com            {
144612605Sgiacomo.travaglini@arm.com                assert64(tc);
144712605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
144812605Sgiacomo.travaglini@arm.com                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
144912605Sgiacomo.travaglini@arm.com                                              bits(newVal, 55, 48);
145012605Sgiacomo.travaglini@arm.com
145112605Sgiacomo.travaglini@arm.com                TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns,
145212605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 43, 0)) << 12,
145312605Sgiacomo.travaglini@arm.com                               asid);
145412605Sgiacomo.travaglini@arm.com
145512605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
145612605Sgiacomo.travaglini@arm.com                return;
145712605Sgiacomo.travaglini@arm.com            }
145812605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by ASID, EL1
145910037SARM gem5 Developers          // @todo: handle VMID to enable Virtualization
146012605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_ASIDE1_Xt:
146112605Sgiacomo.travaglini@arm.com            {
146212605Sgiacomo.travaglini@arm.com                assert64(tc);
146312605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
146412605Sgiacomo.travaglini@arm.com                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
146512605Sgiacomo.travaglini@arm.com                                              bits(newVal, 55, 48);
146612605Sgiacomo.travaglini@arm.com
146712605Sgiacomo.travaglini@arm.com                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
146812605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
146912605Sgiacomo.travaglini@arm.com                return;
147012605Sgiacomo.travaglini@arm.com            }
147112605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable
147210037SARM gem5 Developers          case MISCREG_TLBI_ASIDE1IS_Xt:
147312605Sgiacomo.travaglini@arm.com            {
147412605Sgiacomo.travaglini@arm.com                assert64(tc);
147512605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
147612605Sgiacomo.travaglini@arm.com                auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) :
147712605Sgiacomo.travaglini@arm.com                                              bits(newVal, 55, 48);
147812605Sgiacomo.travaglini@arm.com
147912605Sgiacomo.travaglini@arm.com                TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid);
148012605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
148112605Sgiacomo.travaglini@arm.com                return;
148212605Sgiacomo.travaglini@arm.com            }
148310037SARM gem5 Developers          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
148410037SARM gem5 Developers          // entries from the last level of translation table walks
148512605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, All ASID, EL1
148612605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VAAE1_Xt:
148712605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_VAALE1_Xt:
148812605Sgiacomo.travaglini@arm.com            {
148912605Sgiacomo.travaglini@arm.com                assert64(tc);
149012605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
149112605Sgiacomo.travaglini@arm.com
149212605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
149312605Sgiacomo.travaglini@arm.com                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
149412605Sgiacomo.travaglini@arm.com
149512605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
149612605Sgiacomo.travaglini@arm.com                return;
149712605Sgiacomo.travaglini@arm.com            }
149812605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable
149910037SARM gem5 Developers          case MISCREG_TLBI_VAAE1IS_Xt:
150010037SARM gem5 Developers          case MISCREG_TLBI_VAALE1IS_Xt:
150112605Sgiacomo.travaglini@arm.com            {
150212605Sgiacomo.travaglini@arm.com                assert64(tc);
150312605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
150412605Sgiacomo.travaglini@arm.com
150512605Sgiacomo.travaglini@arm.com                TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns,
150612605Sgiacomo.travaglini@arm.com                    static_cast<Addr>(bits(newVal, 43, 0)) << 12, false);
150712605Sgiacomo.travaglini@arm.com
150812605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
150912605Sgiacomo.travaglini@arm.com                return;
151012605Sgiacomo.travaglini@arm.com            }
151112605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by Intermediate Physical Address,
151212605Sgiacomo.travaglini@arm.com          // Stage 2, EL1
151312605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_IPAS2E1_Xt:
151412605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_IPAS2LE1_Xt:
151512605Sgiacomo.travaglini@arm.com            {
151612605Sgiacomo.travaglini@arm.com                assert64(tc);
151712605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
151812605Sgiacomo.travaglini@arm.com
151912605Sgiacomo.travaglini@arm.com                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
152012605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
152112605Sgiacomo.travaglini@arm.com
152212605Sgiacomo.travaglini@arm.com                tlbiOp(tc);
152312605Sgiacomo.travaglini@arm.com                return;
152412605Sgiacomo.travaglini@arm.com            }
152512605Sgiacomo.travaglini@arm.com          // AArch64 TLB Invalidate by Intermediate Physical Address,
152612605Sgiacomo.travaglini@arm.com          // Stage 2, EL1, Inner Shareable
152712605Sgiacomo.travaglini@arm.com          case MISCREG_TLBI_IPAS2E1IS_Xt:
152810037SARM gem5 Developers          case MISCREG_TLBI_IPAS2LE1IS_Xt:
152912605Sgiacomo.travaglini@arm.com            {
153012605Sgiacomo.travaglini@arm.com                assert64(tc);
153112605Sgiacomo.travaglini@arm.com                scr = readMiscReg(MISCREG_SCR, tc);
153212605Sgiacomo.travaglini@arm.com
153312605Sgiacomo.travaglini@arm.com                TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns,
153412605Sgiacomo.travaglini@arm.com                               static_cast<Addr>(bits(newVal, 35, 0)) << 12);
153512605Sgiacomo.travaglini@arm.com
153612605Sgiacomo.travaglini@arm.com                tlbiOp.broadcast(tc);
153712605Sgiacomo.travaglini@arm.com                return;
153812605Sgiacomo.travaglini@arm.com            }
15397583SAli.Saidi@arm.com          case MISCREG_ACTLR:
15407583SAli.Saidi@arm.com            warn("Not doing anything for write of miscreg ACTLR\n");
15417583SAli.Saidi@arm.com            break;
154210461SAndreas.Sandberg@ARM.com
154310461SAndreas.Sandberg@ARM.com          case MISCREG_PMXEVTYPER_PMCCFILTR:
154410461SAndreas.Sandberg@ARM.com          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
154510461SAndreas.Sandberg@ARM.com          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
154610461SAndreas.Sandberg@ARM.com          case MISCREG_PMCR ... MISCREG_PMOVSSET:
154710461SAndreas.Sandberg@ARM.com            pmu->setMiscReg(misc_reg, newVal);
15487583SAli.Saidi@arm.com            break;
154910461SAndreas.Sandberg@ARM.com
155010461SAndreas.Sandberg@ARM.com
155110037SARM gem5 Developers          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
155210037SARM gem5 Developers            {
155310037SARM gem5 Developers                HSTR hstrMask = 0;
155410037SARM gem5 Developers                hstrMask.tjdbx = 1;
155510037SARM gem5 Developers                newVal &= ~((uint32_t) hstrMask);
155610037SARM gem5 Developers                break;
155710037SARM gem5 Developers            }
155810037SARM gem5 Developers          case MISCREG_HCPTR:
155910037SARM gem5 Developers            {
156010037SARM gem5 Developers                // If a CP bit in NSACR is 0 then the corresponding bit in
156110037SARM gem5 Developers                // HCPTR is RAO/WI. Same applies to NSASEDIS
156210037SARM gem5 Developers                secure_lookup = haveSecurity &&
156310037SARM gem5 Developers                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
156410037SARM gem5 Developers                                  readMiscRegNoEffect(MISCREG_CPSR));
156510037SARM gem5 Developers                if (!secure_lookup) {
156610037SARM gem5 Developers                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
156710037SARM gem5 Developers                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
156810037SARM gem5 Developers                    newVal = (newVal & ~mask) | (oldValue & mask);
156910037SARM gem5 Developers                }
157010037SARM gem5 Developers                break;
157110037SARM gem5 Developers            }
157210037SARM gem5 Developers          case MISCREG_HDFAR: // alias for secure DFAR
157310037SARM gem5 Developers            misc_reg = MISCREG_DFAR_S;
157410037SARM gem5 Developers            break;
157510037SARM gem5 Developers          case MISCREG_HIFAR: // alias for secure IFAR
157610037SARM gem5 Developers            misc_reg = MISCREG_IFAR_S;
157710037SARM gem5 Developers            break;
157810037SARM gem5 Developers          case MISCREG_ATS1CPR:
157910037SARM gem5 Developers          case MISCREG_ATS1CPW:
158010037SARM gem5 Developers          case MISCREG_ATS1CUR:
158110037SARM gem5 Developers          case MISCREG_ATS1CUW:
158210037SARM gem5 Developers          case MISCREG_ATS12NSOPR:
158310037SARM gem5 Developers          case MISCREG_ATS12NSOPW:
158410037SARM gem5 Developers          case MISCREG_ATS12NSOUR:
158510037SARM gem5 Developers          case MISCREG_ATS12NSOUW:
158610037SARM gem5 Developers          case MISCREG_ATS1HR:
158710037SARM gem5 Developers          case MISCREG_ATS1HW:
15887436Sdam.sunwoo@arm.com            {
158911608Snikos.nikoleris@arm.com              Request::Flags flags = 0;
159010037SARM gem5 Developers              BaseTLB::Mode mode = BaseTLB::Read;
159110037SARM gem5 Developers              TLB::ArmTranslationType tranType = TLB::NormalTran;
15927436Sdam.sunwoo@arm.com              Fault fault;
15937436Sdam.sunwoo@arm.com              switch(misc_reg) {
159410037SARM gem5 Developers                case MISCREG_ATS1CPR:
159510037SARM gem5 Developers                  flags    = TLB::MustBeOne;
159610037SARM gem5 Developers                  tranType = TLB::S1CTran;
159710037SARM gem5 Developers                  mode     = BaseTLB::Read;
159810037SARM gem5 Developers                  break;
159910037SARM gem5 Developers                case MISCREG_ATS1CPW:
160010037SARM gem5 Developers                  flags    = TLB::MustBeOne;
160110037SARM gem5 Developers                  tranType = TLB::S1CTran;
160210037SARM gem5 Developers                  mode     = BaseTLB::Write;
160310037SARM gem5 Developers                  break;
160410037SARM gem5 Developers                case MISCREG_ATS1CUR:
160510037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
160610037SARM gem5 Developers                  tranType = TLB::S1CTran;
160710037SARM gem5 Developers                  mode     = BaseTLB::Read;
160810037SARM gem5 Developers                  break;
160910037SARM gem5 Developers                case MISCREG_ATS1CUW:
161010037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
161110037SARM gem5 Developers                  tranType = TLB::S1CTran;
161210037SARM gem5 Developers                  mode     = BaseTLB::Write;
161310037SARM gem5 Developers                  break;
161410037SARM gem5 Developers                case MISCREG_ATS12NSOPR:
161510037SARM gem5 Developers                  if (!haveSecurity)
161610037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOPR");
161710037SARM gem5 Developers                  flags    = TLB::MustBeOne;
161810037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
161910037SARM gem5 Developers                  mode     = BaseTLB::Read;
162010037SARM gem5 Developers                  break;
162110037SARM gem5 Developers                case MISCREG_ATS12NSOPW:
162210037SARM gem5 Developers                  if (!haveSecurity)
162310037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOPW");
162410037SARM gem5 Developers                  flags    = TLB::MustBeOne;
162510037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
162610037SARM gem5 Developers                  mode     = BaseTLB::Write;
162710037SARM gem5 Developers                  break;
162810037SARM gem5 Developers                case MISCREG_ATS12NSOUR:
162910037SARM gem5 Developers                  if (!haveSecurity)
163010037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOUR");
163110037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
163210037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
163310037SARM gem5 Developers                  mode     = BaseTLB::Read;
163410037SARM gem5 Developers                  break;
163510037SARM gem5 Developers                case MISCREG_ATS12NSOUW:
163610037SARM gem5 Developers                  if (!haveSecurity)
163710037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOUW");
163810037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
163910037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
164010037SARM gem5 Developers                  mode     = BaseTLB::Write;
164110037SARM gem5 Developers                  break;
164210037SARM gem5 Developers                case MISCREG_ATS1HR: // only really useful from secure mode.
164310037SARM gem5 Developers                  flags    = TLB::MustBeOne;
164410037SARM gem5 Developers                  tranType = TLB::HypMode;
164510037SARM gem5 Developers                  mode     = BaseTLB::Read;
164610037SARM gem5 Developers                  break;
164710037SARM gem5 Developers                case MISCREG_ATS1HW:
164810037SARM gem5 Developers                  flags    = TLB::MustBeOne;
164910037SARM gem5 Developers                  tranType = TLB::HypMode;
165010037SARM gem5 Developers                  mode     = BaseTLB::Write;
165110037SARM gem5 Developers                  break;
16527436Sdam.sunwoo@arm.com              }
165310037SARM gem5 Developers              // If we're in timing mode then doing the translation in
165410037SARM gem5 Developers              // functional mode then we're slightly distorting performance
165510037SARM gem5 Developers              // results obtained from simulations. The translation should be
165610037SARM gem5 Developers              // done in the same mode the core is running in. NOTE: This
165710037SARM gem5 Developers              // can't be an atomic translation because that causes problems
165810037SARM gem5 Developers              // with unexpected atomic snoop requests.
165913417Sgiacomo.travaglini@arm.com              warn("Translating via %s in functional mode! Fix Me!\n",
166013417Sgiacomo.travaglini@arm.com                   miscRegName[misc_reg]);
166112749Sgiacomo.travaglini@arm.com
166212749Sgiacomo.travaglini@arm.com              auto req = std::make_shared<Request>(
166312749Sgiacomo.travaglini@arm.com                  0, val, 0, flags,  Request::funcMasterId,
166412749Sgiacomo.travaglini@arm.com                  tc->pcState().pc(), tc->contextId());
166512749Sgiacomo.travaglini@arm.com
166612406Sgabeblack@google.com              fault = getDTBPtr(tc)->translateFunctional(
166712749Sgiacomo.travaglini@arm.com                      req, tc, mode, tranType);
166812749Sgiacomo.travaglini@arm.com
166910037SARM gem5 Developers              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
167010037SARM gem5 Developers              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
167110037SARM gem5 Developers
167210037SARM gem5 Developers              MiscReg newVal;
16737436Sdam.sunwoo@arm.com              if (fault == NoFault) {
167412749Sgiacomo.travaglini@arm.com                  Addr paddr = req->getPaddr();
167510037SARM gem5 Developers                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
167610037SARM gem5 Developers                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
167710037SARM gem5 Developers                      newVal = (paddr & mask(39, 12)) |
167812406Sgabeblack@google.com                               (getDTBPtr(tc)->getAttr());
167910037SARM gem5 Developers                  } else {
168010037SARM gem5 Developers                      newVal = (paddr & 0xfffff000) |
168112406Sgabeblack@google.com                               (getDTBPtr(tc)->getAttr());
168210037SARM gem5 Developers                  }
16837436Sdam.sunwoo@arm.com                  DPRINTF(MiscRegs,
16847436Sdam.sunwoo@arm.com                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
168510037SARM gem5 Developers                          val, newVal);
168610037SARM gem5 Developers              } else {
168712524Sgiacomo.travaglini@arm.com                  ArmFault *armFault = static_cast<ArmFault *>(fault.get());
168812570Sgiacomo.travaglini@arm.com                  armFault->update(tc);
168910037SARM gem5 Developers                  // Set fault bit and FSR
169010037SARM gem5 Developers                  FSR fsr = armFault->getFsr(tc);
169110037SARM gem5 Developers
169210037SARM gem5 Developers                  newVal = ((fsr >> 9) & 1) << 11;
169310037SARM gem5 Developers                  if (newVal) {
169410037SARM gem5 Developers                    // LPAE - rearange fault status
169510037SARM gem5 Developers                    newVal |= ((fsr >>  0) & 0x3f) << 1;
169610037SARM gem5 Developers                  } else {
169710037SARM gem5 Developers                    // VMSA - rearange fault status
169810037SARM gem5 Developers                    newVal |= ((fsr >>  0) & 0xf) << 1;
169910037SARM gem5 Developers                    newVal |= ((fsr >> 10) & 0x1) << 5;
170010037SARM gem5 Developers                    newVal |= ((fsr >> 12) & 0x1) << 6;
170110037SARM gem5 Developers                  }
170210037SARM gem5 Developers                  newVal |= 0x1; // F bit
170310037SARM gem5 Developers                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
170410037SARM gem5 Developers                  newVal |= armFault->isStage2() ? 0x200 : 0;
170510037SARM gem5 Developers                  DPRINTF(MiscRegs,
170610037SARM gem5 Developers                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
170710037SARM gem5 Developers                          val, fsr, newVal);
17087436Sdam.sunwoo@arm.com              }
170910037SARM gem5 Developers              setMiscRegNoEffect(MISCREG_PAR, newVal);
17107436Sdam.sunwoo@arm.com              return;
17117436Sdam.sunwoo@arm.com            }
171210037SARM gem5 Developers          case MISCREG_TTBCR:
171310037SARM gem5 Developers            {
171410037SARM gem5 Developers                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
171510037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
171610037SARM gem5 Developers                TTBCR ttbcrMask = 0;
171710037SARM gem5 Developers                TTBCR ttbcrNew = newVal;
171810037SARM gem5 Developers
171910037SARM gem5 Developers                // ARM DDI 0406C.b, ARMv7-32
172010037SARM gem5 Developers                ttbcrMask.n = ones; // T0SZ
172110037SARM gem5 Developers                if (haveSecurity) {
172210037SARM gem5 Developers                    ttbcrMask.pd0 = ones;
172310037SARM gem5 Developers                    ttbcrMask.pd1 = ones;
172410037SARM gem5 Developers                }
172510037SARM gem5 Developers                ttbcrMask.epd0 = ones;
172610037SARM gem5 Developers                ttbcrMask.irgn0 = ones;
172710037SARM gem5 Developers                ttbcrMask.orgn0 = ones;
172810037SARM gem5 Developers                ttbcrMask.sh0 = ones;
172910037SARM gem5 Developers                ttbcrMask.ps = ones; // T1SZ
173010037SARM gem5 Developers                ttbcrMask.a1 = ones;
173110037SARM gem5 Developers                ttbcrMask.epd1 = ones;
173210037SARM gem5 Developers                ttbcrMask.irgn1 = ones;
173310037SARM gem5 Developers                ttbcrMask.orgn1 = ones;
173410037SARM gem5 Developers                ttbcrMask.sh1 = ones;
173510037SARM gem5 Developers                if (haveLPAE)
173610037SARM gem5 Developers                    ttbcrMask.eae = ones;
173710037SARM gem5 Developers
173810037SARM gem5 Developers                if (haveLPAE && ttbcrNew.eae) {
173910037SARM gem5 Developers                    newVal = newVal & ttbcrMask;
174010037SARM gem5 Developers                } else {
174110037SARM gem5 Developers                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
174210037SARM gem5 Developers                }
174312666Sgiacomo.travaglini@arm.com                // Invalidate TLB MiscReg
174412666Sgiacomo.travaglini@arm.com                getITBPtr(tc)->invalidateMiscReg();
174512666Sgiacomo.travaglini@arm.com                getDTBPtr(tc)->invalidateMiscReg();
174612666Sgiacomo.travaglini@arm.com                break;
174710037SARM gem5 Developers            }
174810037SARM gem5 Developers          case MISCREG_TTBR0:
174910037SARM gem5 Developers          case MISCREG_TTBR1:
175010037SARM gem5 Developers            {
175110037SARM gem5 Developers                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
175210037SARM gem5 Developers                if (haveLPAE) {
175310037SARM gem5 Developers                    if (ttbcr.eae) {
175410037SARM gem5 Developers                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
175510037SARM gem5 Developers                        // ARMv8 AArch32 bit 63-56 only
175610037SARM gem5 Developers                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
175710037SARM gem5 Developers                        newVal = (newVal & (~ttbrMask));
175810037SARM gem5 Developers                    }
175910037SARM gem5 Developers                }
176012666Sgiacomo.travaglini@arm.com                // Invalidate TLB MiscReg
176112406Sgabeblack@google.com                getITBPtr(tc)->invalidateMiscReg();
176212406Sgabeblack@google.com                getDTBPtr(tc)->invalidateMiscReg();
176312666Sgiacomo.travaglini@arm.com                break;
176410508SAli.Saidi@ARM.com            }
176512666Sgiacomo.travaglini@arm.com          case MISCREG_SCTLR_EL1:
17667749SAli.Saidi@ARM.com          case MISCREG_CONTEXTIDR:
17677749SAli.Saidi@ARM.com          case MISCREG_PRRR:
17687749SAli.Saidi@ARM.com          case MISCREG_NMRR:
176910037SARM gem5 Developers          case MISCREG_MAIR0:
177010037SARM gem5 Developers          case MISCREG_MAIR1:
17717749SAli.Saidi@ARM.com          case MISCREG_DACR:
177210037SARM gem5 Developers          case MISCREG_VTTBR:
177310037SARM gem5 Developers          case MISCREG_SCR_EL3:
177411575SDylan.Johnson@ARM.com          case MISCREG_HCR_EL2:
177510037SARM gem5 Developers          case MISCREG_TCR_EL1:
177610037SARM gem5 Developers          case MISCREG_TCR_EL2:
177710037SARM gem5 Developers          case MISCREG_TCR_EL3:
177810508SAli.Saidi@ARM.com          case MISCREG_SCTLR_EL2:
177910508SAli.Saidi@ARM.com          case MISCREG_SCTLR_EL3:
178011573SDylan.Johnson@ARM.com          case MISCREG_HSCTLR:
178110037SARM gem5 Developers          case MISCREG_TTBR0_EL1:
178210037SARM gem5 Developers          case MISCREG_TTBR1_EL1:
178310037SARM gem5 Developers          case MISCREG_TTBR0_EL2:
178412675Sgiacomo.travaglini@arm.com          case MISCREG_TTBR1_EL2:
178510037SARM gem5 Developers          case MISCREG_TTBR0_EL3:
178612406Sgabeblack@google.com            getITBPtr(tc)->invalidateMiscReg();
178712406Sgabeblack@google.com            getDTBPtr(tc)->invalidateMiscReg();
17887749SAli.Saidi@ARM.com            break;
178910037SARM gem5 Developers          case MISCREG_NZCV:
179010037SARM gem5 Developers            {
179110037SARM gem5 Developers                CPSR cpsr = val;
179210037SARM gem5 Developers
179310338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_NZ, cpsr.nz);
179410338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_C,  cpsr.c);
179510338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_V,  cpsr.v);
179610037SARM gem5 Developers            }
179710037SARM gem5 Developers            break;
179810037SARM gem5 Developers          case MISCREG_DAIF:
179910037SARM gem5 Developers            {
180010037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
180110037SARM gem5 Developers                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
180210037SARM gem5 Developers                newVal = cpsr;
180310037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
180410037SARM gem5 Developers            }
180510037SARM gem5 Developers            break;
180610037SARM gem5 Developers          case MISCREG_SP_EL0:
180710037SARM gem5 Developers            tc->setIntReg(INTREG_SP0, newVal);
180810037SARM gem5 Developers            break;
180910037SARM gem5 Developers          case MISCREG_SP_EL1:
181010037SARM gem5 Developers            tc->setIntReg(INTREG_SP1, newVal);
181110037SARM gem5 Developers            break;
181210037SARM gem5 Developers          case MISCREG_SP_EL2:
181310037SARM gem5 Developers            tc->setIntReg(INTREG_SP2, newVal);
181410037SARM gem5 Developers            break;
181510037SARM gem5 Developers          case MISCREG_SPSEL:
181610037SARM gem5 Developers            {
181710037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
181810037SARM gem5 Developers                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
181910037SARM gem5 Developers                newVal = cpsr;
182010037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
182110037SARM gem5 Developers            }
182210037SARM gem5 Developers            break;
182310037SARM gem5 Developers          case MISCREG_CURRENTEL:
182410037SARM gem5 Developers            {
182510037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
182610037SARM gem5 Developers                cpsr.el = (uint8_t) ((CPSR) newVal).el;
182710037SARM gem5 Developers                newVal = cpsr;
182810037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
182910037SARM gem5 Developers            }
183010037SARM gem5 Developers            break;
183110037SARM gem5 Developers          case MISCREG_AT_S1E1R_Xt:
183210037SARM gem5 Developers          case MISCREG_AT_S1E1W_Xt:
183310037SARM gem5 Developers          case MISCREG_AT_S1E0R_Xt:
183410037SARM gem5 Developers          case MISCREG_AT_S1E0W_Xt:
183510037SARM gem5 Developers          case MISCREG_AT_S1E2R_Xt:
183610037SARM gem5 Developers          case MISCREG_AT_S1E2W_Xt:
183710037SARM gem5 Developers          case MISCREG_AT_S12E1R_Xt:
183810037SARM gem5 Developers          case MISCREG_AT_S12E1W_Xt:
183910037SARM gem5 Developers          case MISCREG_AT_S12E0R_Xt:
184010037SARM gem5 Developers          case MISCREG_AT_S12E0W_Xt:
184110037SARM gem5 Developers          case MISCREG_AT_S1E3R_Xt:
184210037SARM gem5 Developers          case MISCREG_AT_S1E3W_Xt:
184310037SARM gem5 Developers            {
184412749Sgiacomo.travaglini@arm.com                RequestPtr req = std::make_shared<Request>();
184511608Snikos.nikoleris@arm.com                Request::Flags flags = 0;
184610037SARM gem5 Developers                BaseTLB::Mode mode = BaseTLB::Read;
184710037SARM gem5 Developers                TLB::ArmTranslationType tranType = TLB::NormalTran;
184810037SARM gem5 Developers                Fault fault;
184910037SARM gem5 Developers                switch(misc_reg) {
185010037SARM gem5 Developers                  case MISCREG_AT_S1E1R_Xt:
185110037SARM gem5 Developers                    flags    = TLB::MustBeOne;
185211577SDylan.Johnson@ARM.com                    tranType = TLB::S1E1Tran;
185310037SARM gem5 Developers                    mode     = BaseTLB::Read;
185410037SARM gem5 Developers                    break;
185510037SARM gem5 Developers                  case MISCREG_AT_S1E1W_Xt:
185610037SARM gem5 Developers                    flags    = TLB::MustBeOne;
185711577SDylan.Johnson@ARM.com                    tranType = TLB::S1E1Tran;
185810037SARM gem5 Developers                    mode     = BaseTLB::Write;
185910037SARM gem5 Developers                    break;
186010037SARM gem5 Developers                  case MISCREG_AT_S1E0R_Xt:
186110037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
186211577SDylan.Johnson@ARM.com                    tranType = TLB::S1E0Tran;
186310037SARM gem5 Developers                    mode     = BaseTLB::Read;
186410037SARM gem5 Developers                    break;
186510037SARM gem5 Developers                  case MISCREG_AT_S1E0W_Xt:
186610037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
186711577SDylan.Johnson@ARM.com                    tranType = TLB::S1E0Tran;
186810037SARM gem5 Developers                    mode     = BaseTLB::Write;
186910037SARM gem5 Developers                    break;
187010037SARM gem5 Developers                  case MISCREG_AT_S1E2R_Xt:
187110037SARM gem5 Developers                    flags    = TLB::MustBeOne;
187211577SDylan.Johnson@ARM.com                    tranType = TLB::S1E2Tran;
187310037SARM gem5 Developers                    mode     = BaseTLB::Read;
187410037SARM gem5 Developers                    break;
187510037SARM gem5 Developers                  case MISCREG_AT_S1E2W_Xt:
187610037SARM gem5 Developers                    flags    = TLB::MustBeOne;
187711577SDylan.Johnson@ARM.com                    tranType = TLB::S1E2Tran;
187810037SARM gem5 Developers                    mode     = BaseTLB::Write;
187910037SARM gem5 Developers                    break;
188010037SARM gem5 Developers                  case MISCREG_AT_S12E0R_Xt:
188110037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
188211577SDylan.Johnson@ARM.com                    tranType = TLB::S12E0Tran;
188310037SARM gem5 Developers                    mode     = BaseTLB::Read;
188410037SARM gem5 Developers                    break;
188510037SARM gem5 Developers                  case MISCREG_AT_S12E0W_Xt:
188610037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
188711577SDylan.Johnson@ARM.com                    tranType = TLB::S12E0Tran;
188810037SARM gem5 Developers                    mode     = BaseTLB::Write;
188910037SARM gem5 Developers                    break;
189010037SARM gem5 Developers                  case MISCREG_AT_S12E1R_Xt:
189110037SARM gem5 Developers                    flags    = TLB::MustBeOne;
189211577SDylan.Johnson@ARM.com                    tranType = TLB::S12E1Tran;
189310037SARM gem5 Developers                    mode     = BaseTLB::Read;
189410037SARM gem5 Developers                    break;
189510037SARM gem5 Developers                  case MISCREG_AT_S12E1W_Xt:
189610037SARM gem5 Developers                    flags    = TLB::MustBeOne;
189711577SDylan.Johnson@ARM.com                    tranType = TLB::S12E1Tran;
189810037SARM gem5 Developers                    mode     = BaseTLB::Write;
189910037SARM gem5 Developers                    break;
190010037SARM gem5 Developers                  case MISCREG_AT_S1E3R_Xt:
190110037SARM gem5 Developers                    flags    = TLB::MustBeOne;
190211577SDylan.Johnson@ARM.com                    tranType = TLB::S1E3Tran;
190310037SARM gem5 Developers                    mode     = BaseTLB::Read;
190410037SARM gem5 Developers                    break;
190510037SARM gem5 Developers                  case MISCREG_AT_S1E3W_Xt:
190610037SARM gem5 Developers                    flags    = TLB::MustBeOne;
190711577SDylan.Johnson@ARM.com                    tranType = TLB::S1E3Tran;
190810037SARM gem5 Developers                    mode     = BaseTLB::Write;
190910037SARM gem5 Developers                    break;
191010037SARM gem5 Developers                }
191110037SARM gem5 Developers                // If we're in timing mode then doing the translation in
191210037SARM gem5 Developers                // functional mode then we're slightly distorting performance
191310037SARM gem5 Developers                // results obtained from simulations. The translation should be
191410037SARM gem5 Developers                // done in the same mode the core is running in. NOTE: This
191510037SARM gem5 Developers                // can't be an atomic translation because that causes problems
191610037SARM gem5 Developers                // with unexpected atomic snoop requests.
191713417Sgiacomo.travaglini@arm.com                warn("Translating via %s in functional mode! Fix Me!\n",
191813417Sgiacomo.travaglini@arm.com                     miscRegName[misc_reg]);
191913417Sgiacomo.travaglini@arm.com
192011560Sandreas.sandberg@arm.com                req->setVirt(0, val, 0, flags,  Request::funcMasterId,
192110037SARM gem5 Developers                               tc->pcState().pc());
192211435Smitch.hayenga@arm.com                req->setContext(tc->contextId());
192312406Sgabeblack@google.com                fault = getDTBPtr(tc)->translateFunctional(req, tc, mode,
192412406Sgabeblack@google.com                                                           tranType);
192510037SARM gem5 Developers
192610037SARM gem5 Developers                MiscReg newVal;
192710037SARM gem5 Developers                if (fault == NoFault) {
192810037SARM gem5 Developers                    Addr paddr = req->getPaddr();
192912406Sgabeblack@google.com                    uint64_t attr = getDTBPtr(tc)->getAttr();
193010037SARM gem5 Developers                    uint64_t attr1 = attr >> 56;
193110037SARM gem5 Developers                    if (!attr1 || attr1 ==0x44) {
193210037SARM gem5 Developers                        attr |= 0x100;
193310037SARM gem5 Developers                        attr &= ~ uint64_t(0x80);
193410037SARM gem5 Developers                    }
193510037SARM gem5 Developers                    newVal = (paddr & mask(47, 12)) | attr;
193610037SARM gem5 Developers                    DPRINTF(MiscRegs,
193710037SARM gem5 Developers                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
193810037SARM gem5 Developers                          val, newVal);
193910037SARM gem5 Developers                } else {
194012524Sgiacomo.travaglini@arm.com                    ArmFault *armFault = static_cast<ArmFault *>(fault.get());
194112570Sgiacomo.travaglini@arm.com                    armFault->update(tc);
194210037SARM gem5 Developers                    // Set fault bit and FSR
194310037SARM gem5 Developers                    FSR fsr = armFault->getFsr(tc);
194410037SARM gem5 Developers
194511577SDylan.Johnson@ARM.com                    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
194611577SDylan.Johnson@ARM.com                    if (cpsr.width) { // AArch32
194711577SDylan.Johnson@ARM.com                        newVal = ((fsr >> 9) & 1) << 11;
194811577SDylan.Johnson@ARM.com                        // rearrange fault status
194911577SDylan.Johnson@ARM.com                        newVal |= ((fsr >>  0) & 0x3f) << 1;
195011577SDylan.Johnson@ARM.com                        newVal |= 0x1; // F bit
195111577SDylan.Johnson@ARM.com                        newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
195211577SDylan.Johnson@ARM.com                        newVal |= armFault->isStage2() ? 0x200 : 0;
195311577SDylan.Johnson@ARM.com                    } else { // AArch64
195411577SDylan.Johnson@ARM.com                        newVal = 1; // F bit
195511577SDylan.Johnson@ARM.com                        newVal |= fsr << 1; // FST
195611577SDylan.Johnson@ARM.com                        // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit.
195711577SDylan.Johnson@ARM.com                        newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW
195811577SDylan.Johnson@ARM.com                        newVal |= armFault->isStage2() ? 1 << 9 : 0; // S
195911577SDylan.Johnson@ARM.com                        newVal |= 1 << 11; // RES1
196011577SDylan.Johnson@ARM.com                    }
196110037SARM gem5 Developers                    DPRINTF(MiscRegs,
196210037SARM gem5 Developers                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
196310037SARM gem5 Developers                            val, fsr, newVal);
196410037SARM gem5 Developers                }
196510037SARM gem5 Developers                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
196610037SARM gem5 Developers                return;
196710037SARM gem5 Developers            }
196810037SARM gem5 Developers          case MISCREG_SPSR_EL3:
196910037SARM gem5 Developers          case MISCREG_SPSR_EL2:
197010037SARM gem5 Developers          case MISCREG_SPSR_EL1:
197110037SARM gem5 Developers            // Force bits 23:21 to 0
197210037SARM gem5 Developers            newVal = val & ~(0x7 << 21);
197310037SARM gem5 Developers            break;
19748549Sdaniel.johnson@arm.com          case MISCREG_L2CTLR:
19758549Sdaniel.johnson@arm.com            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
19768549Sdaniel.johnson@arm.com                 miscRegName[misc_reg], uint32_t(val));
197710037SARM gem5 Developers            break;
197810037SARM gem5 Developers
197910037SARM gem5 Developers          // Generic Timer registers
198012816Sgiacomo.travaglini@arm.com          case MISCREG_CNTHV_CTL_EL2:
198112816Sgiacomo.travaglini@arm.com          case MISCREG_CNTHV_CVAL_EL2:
198212816Sgiacomo.travaglini@arm.com          case MISCREG_CNTHV_TVAL_EL2:
198310844Sandreas.sandberg@arm.com          case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL:
198410844Sandreas.sandberg@arm.com          case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL:
198510844Sandreas.sandberg@arm.com          case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0:
198610844Sandreas.sandberg@arm.com          case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1:
198710844Sandreas.sandberg@arm.com            getGenericTimer(tc).setMiscReg(misc_reg, newVal);
198810037SARM gem5 Developers            break;
198913531Sjairo.balart@metempsy.com
199013531Sjairo.balart@metempsy.com          case MISCREG_ICC_PMR_EL1 ... MISCREG_ICC_IGRPEN1_EL3:
199113531Sjairo.balart@metempsy.com          case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_LR15_EL2:
199213531Sjairo.balart@metempsy.com            getGICv3CPUInterface(tc).setMiscReg(misc_reg, newVal);
199313531Sjairo.balart@metempsy.com            return;
19947405SAli.Saidi@ARM.com        }
19957405SAli.Saidi@ARM.com    }
19967405SAli.Saidi@ARM.com    setMiscRegNoEffect(misc_reg, newVal);
19977405SAli.Saidi@ARM.com}
19987405SAli.Saidi@ARM.com
199910844Sandreas.sandberg@arm.comBaseISADevice &
200010844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc)
200110037SARM gem5 Developers{
200210844Sandreas.sandberg@arm.com    // We only need to create an ISA interface the first time we try
200310844Sandreas.sandberg@arm.com    // to access the timer.
200410844Sandreas.sandberg@arm.com    if (timer)
200510844Sandreas.sandberg@arm.com        return *timer.get();
200610844Sandreas.sandberg@arm.com
200710844Sandreas.sandberg@arm.com    assert(system);
200810844Sandreas.sandberg@arm.com    GenericTimer *generic_timer(system->getGenericTimer());
200910844Sandreas.sandberg@arm.com    if (!generic_timer) {
201010844Sandreas.sandberg@arm.com        panic("Trying to get a generic timer from a system that hasn't "
201110844Sandreas.sandberg@arm.com              "been configured to use a generic timer.\n");
201210037SARM gem5 Developers    }
201310037SARM gem5 Developers
201411150Smitch.hayenga@arm.com    timer.reset(new GenericTimerISA(*generic_timer, tc->contextId()));
201512972Sandreas.sandberg@arm.com    timer->setThreadContext(tc);
201612972Sandreas.sandberg@arm.com
201710844Sandreas.sandberg@arm.com    return *timer.get();
201810037SARM gem5 Developers}
201910037SARM gem5 Developers
202013531Sjairo.balart@metempsy.comBaseISADevice &
202113531Sjairo.balart@metempsy.comISA::getGICv3CPUInterface(ThreadContext *tc)
202213531Sjairo.balart@metempsy.com{
202313531Sjairo.balart@metempsy.com    panic_if(!gicv3CpuInterface, "GICV3 cpu interface is not registered!");
202413531Sjairo.balart@metempsy.com    return *gicv3CpuInterface.get();
202513531Sjairo.balart@metempsy.com}
202613531Sjairo.balart@metempsy.com
20277405SAli.Saidi@ARM.com}
20289384SAndreas.Sandberg@arm.com
20299384SAndreas.Sandberg@arm.comArmISA::ISA *
20309384SAndreas.Sandberg@arm.comArmISAParams::create()
20319384SAndreas.Sandberg@arm.com{
20329384SAndreas.Sandberg@arm.com    return new ArmISA::ISA(this);
20339384SAndreas.Sandberg@arm.com}
2034