isa.cc revision 13396
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4611793Sbrandon.potter@amd.com#include "cpu/base.hh" 478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 488232Snate@binkert.org#include "debug/Arm.hh" 498232Snate@binkert.org#include "debug/MiscRegs.hh" 5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 5113531Sjairo.balart@metempsy.com#include "params/ArmISA.hh" 5213531Sjairo.balart@metempsy.com#include "sim/faults.hh" 539384SAndreas.Sandberg@arm.com#include "sim/stat_control.hh" 547678Sgblack@eecs.umich.edu#include "sim/system.hh" 558059SAli.Saidi@ARM.com 568284SAli.Saidi@ARM.comnamespace ArmISA 577405SAli.Saidi@ARM.com{ 587405SAli.Saidi@ARM.com 597405SAli.Saidi@ARM.comISA::ISA(Params *p) 607405SAli.Saidi@ARM.com : SimObject(p), 619384SAndreas.Sandberg@arm.com system(NULL), 6210461SAndreas.Sandberg@ARM.com _decoderFlavour(p->decoderFlavour), 6310461SAndreas.Sandberg@ARM.com _vecRegRenameMode(p->vecRegRenameMode), 6411165SRekai.GonzalezAlberquilla@arm.com pmu(p->pmu), 6512109SRekai.GonzalezAlberquilla@arm.com impdefAsNop(p->impdef_nop) 6612714Sgiacomo.travaglini@arm.com{ 6712714Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 689384SAndreas.Sandberg@arm.com 6911770SCurtis.Dunham@arm.com // Hook up a dummy device if we haven't been configured with a 7010037SARM gem5 Developers // real PMU. By using a dummy device, we don't need to check that 7110461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7210461SAndreas.Sandberg@ARM.com if (!pmu) 7310461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7410461SAndreas.Sandberg@ARM.com 7510461SAndreas.Sandberg@ARM.com // Give all ISA devices a pointer to this ISA 7610461SAndreas.Sandberg@ARM.com pmu->setISA(this); 7710609Sandreas.sandberg@arm.com 7810609Sandreas.sandberg@arm.com system = dynamic_cast<ArmSystem *>(p->system); 7910609Sandreas.sandberg@arm.com 8010037SARM gem5 Developers // Cache system-level properties 8110037SARM gem5 Developers if (FullSystem && system) { 8210037SARM gem5 Developers highestELIs64 = system->highestELIs64(); 8310037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8411771SCurtis.Dunham@arm.com haveLPAE = system->haveLPAE(); 8510037SARM gem5 Developers haveCrypto = system->haveCrypto(); 8610037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8713173Sgiacomo.travaglini@arm.com haveLargeAsid64 = system->haveLargeAsid64(); 8810037SARM gem5 Developers physAddrRange = system->physAddrRange(); 8910037SARM gem5 Developers } else { 9013114Sgiacomo.travaglini@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9110037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9211771SCurtis.Dunham@arm.com haveCrypto = false; 9310037SARM gem5 Developers haveLargeAsid64 = false; 9413499Sgiacomo.travaglini@arm.com physAddrRange = 32; // dummy value 9510037SARM gem5 Developers } 9613114Sgiacomo.travaglini@arm.com 9710037SARM gem5 Developers initializeMiscRegMetadata(); 9810037SARM gem5 Developers preUnflattenMiscReg(); 9913531Sjairo.balart@metempsy.com 10013531Sjairo.balart@metempsy.com clear(); 10113531Sjairo.balart@metempsy.com} 10213531Sjairo.balart@metempsy.com 10313531Sjairo.balart@metempsy.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 10413531Sjairo.balart@metempsy.com 10513531Sjairo.balart@metempsy.comconst ArmISAParams * 10612477SCurtis.Dunham@arm.comISA::params() const 10710037SARM gem5 Developers{ 10810037SARM gem5 Developers return dynamic_cast<const Params *>(_params); 1099384SAndreas.Sandberg@arm.com} 1109384SAndreas.Sandberg@arm.com 1119384SAndreas.Sandberg@arm.comvoid 11212479SCurtis.Dunham@arm.comISA::clear() 11312479SCurtis.Dunham@arm.com{ 1149384SAndreas.Sandberg@arm.com const Params *p(params()); 1159384SAndreas.Sandberg@arm.com 1169384SAndreas.Sandberg@arm.com SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1179384SAndreas.Sandberg@arm.com memset(miscRegs, 0, sizeof(miscRegs)); 1189384SAndreas.Sandberg@arm.com 1199384SAndreas.Sandberg@arm.com initID32(p); 1207427Sgblack@eecs.umich.edu 1217427Sgblack@eecs.umich.edu // We always initialize AArch64 ID registers even 1227427Sgblack@eecs.umich.edu // if we are in AArch32. This is done since if we 1239385SAndreas.Sandberg@arm.com // are in SE mode we don't know if our ArmProcess is 1249385SAndreas.Sandberg@arm.com // AArch32 or AArch64 1257427Sgblack@eecs.umich.edu initID64(p); 1267427Sgblack@eecs.umich.edu 12710037SARM gem5 Developers // Start with an event in the mailbox 12813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SEV_MAILBOX] = 1; 12910037SARM gem5 Developers 13013114Sgiacomo.travaglini@arm.com // Separate Instruction and Data TLBs 13113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_TLBTR] = 1; 13213114Sgiacomo.travaglini@arm.com 13313114Sgiacomo.travaglini@arm.com MVFR0 mvfr0 = 0; 13413114Sgiacomo.travaglini@arm.com mvfr0.advSimdRegisters = 2; 13512690Sgiacomo.travaglini@arm.com mvfr0.singlePrecision = 2; 13610037SARM gem5 Developers mvfr0.doublePrecision = 2; 1377427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1387427Sgblack@eecs.umich.edu mvfr0.divide = 1; 13910037SARM gem5 Developers mvfr0.squareRoot = 1; 1407427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1417427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1427427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1437427Sgblack@eecs.umich.edu 1447427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1457427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1467427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1477427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1487427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1497427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1507427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1517427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1527427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1537427Sgblack@eecs.umich.edu 1547427Sgblack@eecs.umich.edu // Reset values of PRRR and NMRR are implementation dependent 1557427Sgblack@eecs.umich.edu 1567427Sgblack@eecs.umich.edu // @todo: PRRR and NMRR in secure state? 1577427Sgblack@eecs.umich.edu miscRegs[MISCREG_PRRR_NS] = 1587427Sgblack@eecs.umich.edu (1 << 19) | // 19 1597427Sgblack@eecs.umich.edu (0 << 18) | // 18 1607427Sgblack@eecs.umich.edu (0 << 17) | // 17 1617427Sgblack@eecs.umich.edu (1 << 16) | // 16 1627427Sgblack@eecs.umich.edu (2 << 14) | // 15:14 1637436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1647436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 16510037SARM gem5 Developers (2 << 8) | // 9:8 16610037SARM gem5 Developers (2 << 6) | // 7:6 1677436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1687436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1697436Sdam.sunwoo@arm.com 0; // 1:0 1707436Sdam.sunwoo@arm.com 1717436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR_NS] = 1727436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1737436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1747436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1757436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1767436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1777436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1787436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 17913393Sgiacomo.travaglini@arm.com (1 << 14) | // 15:14 18010037SARM gem5 Developers (0 << 12) | // 13:12 1817436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1827436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1837436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1847436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1857436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1867436Sdam.sunwoo@arm.com 0; // 1:0 1877436Sdam.sunwoo@arm.com 1887436Sdam.sunwoo@arm.com if (FullSystem && system->highestELIs64()) { 1897436Sdam.sunwoo@arm.com // Initialize AArch64 state 1907436Sdam.sunwoo@arm.com clear64(p); 1917436Sdam.sunwoo@arm.com return; 1927436Sdam.sunwoo@arm.com } 1937436Sdam.sunwoo@arm.com 1947436Sdam.sunwoo@arm.com // Initialize AArch32 state... 1957436Sdam.sunwoo@arm.com clear32(p, sctlr_rst); 1967436Sdam.sunwoo@arm.com} 19713393Sgiacomo.travaglini@arm.com 19813393Sgiacomo.travaglini@arm.comvoid 19913393Sgiacomo.travaglini@arm.comISA::clear32(const ArmISAParams *p, const SCTLR &sctlr_rst) 20013393Sgiacomo.travaglini@arm.com{ 20113393Sgiacomo.travaglini@arm.com CPSR cpsr = 0; 20213393Sgiacomo.travaglini@arm.com cpsr.mode = MODE_USER; 20313393Sgiacomo.travaglini@arm.com 20413393Sgiacomo.travaglini@arm.com if (FullSystem) { 20513393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MVBAR] = system->resetAddr(); 20613393Sgiacomo.travaglini@arm.com } 20713393Sgiacomo.travaglini@arm.com 20813393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPSR] = cpsr; 20913393Sgiacomo.travaglini@arm.com updateRegMap(cpsr); 21013393Sgiacomo.travaglini@arm.com 21113393Sgiacomo.travaglini@arm.com SCTLR sctlr = 0; 21213393Sgiacomo.travaglini@arm.com sctlr.te = (bool) sctlr_rst.te; 21313396Sgiacomo.travaglini@arm.com sctlr.nmfi = (bool) sctlr_rst.nmfi; 21413396Sgiacomo.travaglini@arm.com sctlr.v = (bool) sctlr_rst.v; 21513396Sgiacomo.travaglini@arm.com sctlr.u = 1; 21613396Sgiacomo.travaglini@arm.com sctlr.xp = 1; 21713393Sgiacomo.travaglini@arm.com sctlr.rao2 = 1; 21813393Sgiacomo.travaglini@arm.com sctlr.rao3 = 1; 21913393Sgiacomo.travaglini@arm.com sctlr.rao4 = 0xf; // SCTLR[6:3] 22013393Sgiacomo.travaglini@arm.com sctlr.uci = 1; 22113393Sgiacomo.travaglini@arm.com sctlr.dze = 1; 22213393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_NS] = sctlr; 22313393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 22413393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_HCPTR] = 0; 22513393Sgiacomo.travaglini@arm.com 22613393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_CPACR] = 0; 22713393Sgiacomo.travaglini@arm.com 22813393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 22913393Sgiacomo.travaglini@arm.com 23013393Sgiacomo.travaglini@arm.com if (haveLPAE) { 23113393Sgiacomo.travaglini@arm.com TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 23213393Sgiacomo.travaglini@arm.com ttbcr.eae = 0; 23313393Sgiacomo.travaglini@arm.com miscRegs[MISCREG_TTBCR_NS] = ttbcr; 23413393Sgiacomo.travaglini@arm.com // Enforce consistency with system-level settings 2357644Sali.saidi@arm.com miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 2368147SAli.Saidi@ARM.com } 2379385SAndreas.Sandberg@arm.com 2389385SAndreas.Sandberg@arm.com if (haveSecurity) { 23910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 24010037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 24110037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 24210037SARM gem5 Developers } else { 24310037SARM gem5 Developers // we're always non-secure 24410037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 24510037SARM gem5 Developers } 24610037SARM gem5 Developers 24710037SARM gem5 Developers //XXX We need to initialize the rest of the state. 24810037SARM gem5 Developers} 24910037SARM gem5 Developers 25010037SARM gem5 Developersvoid 25110037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 25210037SARM gem5 Developers{ 25310037SARM gem5 Developers CPSR cpsr = 0; 25410037SARM gem5 Developers Addr rvbar = system->resetAddr(); 2558147SAli.Saidi@ARM.com switch (system->highestEL()) { 2567427Sgblack@eecs.umich.edu // Set initial EL to highest implemented EL using associated stack 2577427Sgblack@eecs.umich.edu // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 2587427Sgblack@eecs.umich.edu // value 25910037SARM gem5 Developers case EL3: 26010037SARM gem5 Developers cpsr.mode = MODE_EL3H; 26110037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 26210037SARM gem5 Developers break; 26313396Sgiacomo.travaglini@arm.com case EL2: 26410037SARM gem5 Developers cpsr.mode = MODE_EL2H; 26510037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 26610037SARM gem5 Developers break; 26710037SARM gem5 Developers case EL1: 26810037SARM gem5 Developers cpsr.mode = MODE_EL1H; 26910037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 27010037SARM gem5 Developers break; 27110037SARM gem5 Developers default: 27210037SARM gem5 Developers panic("Invalid highest implemented exception level"); 27310037SARM gem5 Developers break; 27410037SARM gem5 Developers } 27510037SARM gem5 Developers 27610037SARM gem5 Developers // Initialize rest of CPSR 27710037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 27810037SARM gem5 Developers cpsr.ss = 0; 27910037SARM gem5 Developers cpsr.il = 0; 28010037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 28110037SARM gem5 Developers updateRegMap(cpsr); 28210037SARM gem5 Developers 28310037SARM gem5 Developers // Initialize other control registers 28410037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 28510037SARM gem5 Developers if (haveSecurity) { 28610037SARM gem5 Developers miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 28710037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 28810037SARM gem5 Developers } else if (haveVirtualization) { 28910037SARM gem5 Developers // also MISCREG_SCTLR_EL2 (by mapping) 29010037SARM gem5 Developers miscRegs[MISCREG_HSCTLR] = 0x30c50830; 29110037SARM gem5 Developers } else { 29210037SARM gem5 Developers // also MISCREG_SCTLR_EL1 (by mapping) 29310037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 29410037SARM gem5 Developers // Always non-secure 29511770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCR_EL3] = 1; 29610037SARM gem5 Developers } 29711574SCurtis.Dunham@arm.com} 29811770SCurtis.Dunham@arm.com 29911770SCurtis.Dunham@arm.comvoid 30010037SARM gem5 DevelopersISA::initID32(const ArmISAParams *p) 30111770SCurtis.Dunham@arm.com{ 30211770SCurtis.Dunham@arm.com // Initialize configurable default values 30310037SARM gem5 Developers miscRegs[MISCREG_MIDR] = p->midr; 30410037SARM gem5 Developers miscRegs[MISCREG_MIDR_EL1] = p->midr; 30510037SARM gem5 Developers miscRegs[MISCREG_VPIDR] = p->midr; 30613114Sgiacomo.travaglini@arm.com 30710037SARM gem5 Developers miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 30813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 30913114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 31013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 31113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 31213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 31313114Sgiacomo.travaglini@arm.com 31413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 31513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 31613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 31713114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 31813114Sgiacomo.travaglini@arm.com} 31913114Sgiacomo.travaglini@arm.com 32013114Sgiacomo.travaglini@arm.comvoid 32113114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p) 32213114Sgiacomo.travaglini@arm.com{ 32313114Sgiacomo.travaglini@arm.com // Initialize configurable id registers 32413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 32513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 32613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 32713499Sgiacomo.travaglini@arm.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 32813499Sgiacomo.travaglini@arm.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 32913499Sgiacomo.travaglini@arm.com 33013499Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 33113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 33213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 33313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 33413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 33513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_AA64MMFR2_EL1] = p->id_aa64mmfr2_el1; 33610037SARM gem5 Developers 33710037SARM gem5 Developers miscRegs[MISCREG_ID_DFR0_EL1] = 33810037SARM gem5 Developers (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 33910461SAndreas.Sandberg@ARM.com 34010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 34110461SAndreas.Sandberg@ARM.com 34210461SAndreas.Sandberg@ARM.com // Enforce consistency with system-level settings... 34310037SARM gem5 Developers 34410037SARM gem5 Developers // EL3 34510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 34610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 34710037SARM gem5 Developers haveSecurity ? 0x2 : 0x0); 34813116Sgiacomo.travaglini@arm.com // EL2 34910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 35010461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 35110461SAndreas.Sandberg@ARM.com haveVirtualization ? 0x2 : 0x0); 35210461SAndreas.Sandberg@ARM.com // Large ASID support 35310461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 35410461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 35510037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 35610037SARM gem5 Developers // Physical address size 35710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 35810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 35910037SARM gem5 Developers encodePhysAddrRange64(physAddrRange)); 36011574SCurtis.Dunham@arm.com // Crypto 36110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = insertBits( 36210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1], 19, 4, 36310037SARM gem5 Developers haveCrypto ? 0x1112 : 0x0); 36411574SCurtis.Dunham@arm.com} 36510037SARM gem5 Developers 36610037SARM gem5 Developersvoid 36710037SARM gem5 DevelopersISA::startup(ThreadContext *tc) 36810037SARM gem5 Developers{ 36910037SARM gem5 Developers pmu->setThreadContext(tc); 37010037SARM gem5 Developers 37110037SARM gem5 Developers} 37213114Sgiacomo.travaglini@arm.com 37313173Sgiacomo.travaglini@arm.com 37413173Sgiacomo.travaglini@arm.comMiscReg 37513173Sgiacomo.travaglini@arm.comISA::readMiscRegNoEffect(int misc_reg) const 37613173Sgiacomo.travaglini@arm.com{ 37710037SARM gem5 Developers assert(misc_reg < NumMiscRegs); 37810037SARM gem5 Developers 37912972Sandreas.sandberg@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 38012972Sandreas.sandberg@arm.com const auto &map = getMiscIndices(misc_reg); 38112972Sandreas.sandberg@arm.com int lower = map.first, upper = map.second; 38212972Sandreas.sandberg@arm.com // NB!: apply architectural masks according to desired register, 38312972Sandreas.sandberg@arm.com // despite possibly getting value from different (mapped) register. 38413531Sjairo.balart@metempsy.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 38513531Sjairo.balart@metempsy.com |(miscRegs[upper] << 32)); 38613531Sjairo.balart@metempsy.com if (val & reg.res0()) { 38713531Sjairo.balart@metempsy.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 38813531Sjairo.balart@metempsy.com miscRegName[misc_reg], val & reg.res0()); 38913531Sjairo.balart@metempsy.com } 39013531Sjairo.balart@metempsy.com if ((val & reg.res1()) != reg.res1()) { 39112972Sandreas.sandberg@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 39212972Sandreas.sandberg@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 39312972Sandreas.sandberg@arm.com } 3947405SAli.Saidi@ARM.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 39510035Sandreas.hansson@arm.com} 3967405SAli.Saidi@ARM.com 3977405SAli.Saidi@ARM.com 3987614Sminkyu.jeong@arm.comMiscReg 39912478SCurtis.Dunham@arm.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 40012478SCurtis.Dunham@arm.com{ 40112478SCurtis.Dunham@arm.com CPSR cpsr = 0; 40212478SCurtis.Dunham@arm.com PCState pc = 0; 40312478SCurtis.Dunham@arm.com SCR scr = 0; 40412478SCurtis.Dunham@arm.com 40512478SCurtis.Dunham@arm.com if (misc_reg == MISCREG_CPSR) { 40612478SCurtis.Dunham@arm.com cpsr = miscRegs[misc_reg]; 40712478SCurtis.Dunham@arm.com pc = tc->pcState(); 40812478SCurtis.Dunham@arm.com cpsr.j = pc.jazelle() ? 1 : 0; 40912478SCurtis.Dunham@arm.com cpsr.t = pc.thumb() ? 1 : 0; 41012478SCurtis.Dunham@arm.com return cpsr; 41112478SCurtis.Dunham@arm.com } 41212478SCurtis.Dunham@arm.com 41312478SCurtis.Dunham@arm.com#ifndef NDEBUG 41412478SCurtis.Dunham@arm.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 4157405SAli.Saidi@ARM.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 4167405SAli.Saidi@ARM.com warn("Unimplemented system register %s read.\n", 4177405SAli.Saidi@ARM.com miscRegName[misc_reg]); 4187405SAli.Saidi@ARM.com else 4197405SAli.Saidi@ARM.com panic("Unimplemented system register %s read.\n", 4207405SAli.Saidi@ARM.com miscRegName[misc_reg]); 42110037SARM gem5 Developers } 42210037SARM gem5 Developers#endif 42310037SARM gem5 Developers 4249050Schander.sudanthi@arm.com switch (unflattenMiscReg(misc_reg)) { 4257405SAli.Saidi@ARM.com case MISCREG_HCR: 42610037SARM gem5 Developers { 42710037SARM gem5 Developers if (!haveVirtualization) 4287720Sgblack@eecs.umich.edu return 0; 4297720Sgblack@eecs.umich.edu else 4307405SAli.Saidi@ARM.com return readMiscRegNoEffect(MISCREG_HCR); 4317405SAli.Saidi@ARM.com } 4327757SAli.Saidi@ARM.com case MISCREG_CPACR: 43310037SARM gem5 Developers { 43410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 43510037SARM gem5 Developers CPACR cpacrMask = 0; 43610037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 43710037SARM gem5 Developers // be readable? (straight copy from the write code) 43810037SARM gem5 Developers cpacrMask.cp10 = ones; 43910037SARM gem5 Developers cpacrMask.cp11 = ones; 44010037SARM gem5 Developers cpacrMask.asedis = ones; 44110037SARM gem5 Developers 44210037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 44310037SARM gem5 Developers if (haveSecurity) { 44410037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 44510037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 44610037SARM gem5 Developers if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 44710037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 44810037SARM gem5 Developers // NB: Skipping the full loop, here 44910037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 45010037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 45110037SARM gem5 Developers } 45210037SARM gem5 Developers } 45310037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 45410037SARM gem5 Developers val &= cpacrMask; 45510037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 45610037SARM gem5 Developers miscRegName[misc_reg], val); 45710037SARM gem5 Developers return val; 45810037SARM gem5 Developers } 45910037SARM gem5 Developers case MISCREG_MPIDR: 46010037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 46110037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 46210037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 46310037SARM gem5 Developers return getMPIDR(system, tc); 46410037SARM gem5 Developers } else { 46510037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 46612667Schuan.zhu@arm.com } 46710037SARM gem5 Developers break; 46810037SARM gem5 Developers case MISCREG_MPIDR_EL1: 46910037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 47010037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 47110037SARM gem5 Developers case MISCREG_VMPIDR: 47210037SARM gem5 Developers // top bit defined as RES1 47310037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 47410037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 47510037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 47610037SARM gem5 Developers case MISCREG_MIDR: 47710037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 47810037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 4798284SAli.Saidi@ARM.com if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 48010037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 48113550Sgiacomo.travaglini@arm.com } else { 48210037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 48313550Sgiacomo.travaglini@arm.com } 48410037SARM gem5 Developers break; 48510037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 48610037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 48710037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 48810037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 48910037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 49010037SARM gem5 Developers return 0; 49110037SARM gem5 Developers 49210037SARM gem5 Developers case MISCREG_CLIDR: 49310037SARM gem5 Developers warn_once("The clidr register always reports 0 caches.\n"); 49410037SARM gem5 Developers warn_once("clidr LoUIS field of 0b001 to match current " 4959050Schander.sudanthi@arm.com "ARM implementations.\n"); 4968284SAli.Saidi@ARM.com return 0x00200000; 49710037SARM gem5 Developers case MISCREG_CCSIDR: 49810037SARM gem5 Developers warn_once("The ccsidr register isn't implemented and " 49910037SARM gem5 Developers "always reads as 0.\n"); 50010037SARM gem5 Developers break; 50110037SARM gem5 Developers case MISCREG_CTR: // AArch32, ARMv7, top bit set 50210037SARM gem5 Developers case MISCREG_CTR_EL0: // AArch64 50310037SARM gem5 Developers { 5047405SAli.Saidi@ARM.com //all caches have the same line size in gem5 5057731SAli.Saidi@ARM.com //4 byte words in ARM 5068468Swade.walker@arm.com unsigned lineSizeWords = 5078468Swade.walker@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 5088468Swade.walker@arm.com unsigned log2LineSizeWords = 0; 5097405SAli.Saidi@ARM.com 5107731SAli.Saidi@ARM.com while (lineSizeWords >>= 1) { 5117405SAli.Saidi@ARM.com ++log2LineSizeWords; 5127405SAli.Saidi@ARM.com } 51311809Sbaz21@cam.ac.uk 51411809Sbaz21@cam.ac.uk CTR ctr = 0; 5159130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 5169130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 5179130Satgutier@umich.edu //b11 - gem5 uses pipt 5189130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5199814Sandreas.hansson@arm.com //log2 of minimum d-cache line size (words) 5209130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5219130Satgutier@umich.edu //log2 of max reservation size (words) 5229130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5239130Satgutier@umich.edu //log2 of max writeback size (words) 5249130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5259130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5269130Satgutier@umich.edu ctr.format = 0x4; 5279130Satgutier@umich.edu 5289130Satgutier@umich.edu return ctr; 5299130Satgutier@umich.edu } 5309130Satgutier@umich.edu case MISCREG_ACTLR: 5319130Satgutier@umich.edu warn("Not doing anything for miscreg ACTLR\n"); 5329130Satgutier@umich.edu break; 5339130Satgutier@umich.edu 5349130Satgutier@umich.edu case MISCREG_PMXEVTYPER_PMCCFILTR: 5359130Satgutier@umich.edu case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 5369130Satgutier@umich.edu case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 5379130Satgutier@umich.edu case MISCREG_PMCR ... MISCREG_PMOVSSET: 5389130Satgutier@umich.edu return pmu->readMiscReg(misc_reg); 5399130Satgutier@umich.edu 5409130Satgutier@umich.edu case MISCREG_CPSR_Q: 5419130Satgutier@umich.edu panic("shouldn't be reading this register seperately\n"); 5427583SAli.Saidi@arm.com case MISCREG_FPSCR_QC: 5437583SAli.Saidi@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5447583SAli.Saidi@arm.com case MISCREG_FPSCR_EXC: 54510461SAndreas.Sandberg@ARM.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 54610461SAndreas.Sandberg@ARM.com case MISCREG_FPSR: 54710461SAndreas.Sandberg@ARM.com { 54810461SAndreas.Sandberg@ARM.com const uint32_t ones = (uint32_t)(-1); 54910461SAndreas.Sandberg@ARM.com FPSCR fpscrMask = 0; 55010461SAndreas.Sandberg@ARM.com fpscrMask.ioc = ones; 55110461SAndreas.Sandberg@ARM.com fpscrMask.dzc = ones; 5528302SAli.Saidi@ARM.com fpscrMask.ofc = ones; 5538302SAli.Saidi@ARM.com fpscrMask.ufc = ones; 5547783SGiacomo.Gabrielli@arm.com fpscrMask.ixc = ones; 5557783SGiacomo.Gabrielli@arm.com fpscrMask.idc = ones; 5567783SGiacomo.Gabrielli@arm.com fpscrMask.qc = ones; 5577783SGiacomo.Gabrielli@arm.com fpscrMask.v = ones; 55810037SARM gem5 Developers fpscrMask.c = ones; 55910037SARM gem5 Developers fpscrMask.z = ones; 56010037SARM gem5 Developers fpscrMask.n = ones; 56110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 56210037SARM gem5 Developers } 56310037SARM gem5 Developers case MISCREG_FPCR: 56410037SARM gem5 Developers { 56510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 56610037SARM gem5 Developers FPSCR fpscrMask = 0; 56710037SARM gem5 Developers fpscrMask.len = ones; 56810037SARM gem5 Developers fpscrMask.stride = ones; 56910037SARM gem5 Developers fpscrMask.rMode = ones; 57010037SARM gem5 Developers fpscrMask.fz = ones; 57110037SARM gem5 Developers fpscrMask.dn = ones; 57210037SARM gem5 Developers fpscrMask.ahp = ones; 57310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 57410037SARM gem5 Developers } 57510037SARM gem5 Developers case MISCREG_NZCV: 57610037SARM gem5 Developers { 57710037SARM gem5 Developers CPSR cpsr = 0; 57810037SARM gem5 Developers cpsr.nz = tc->readCCReg(CCREG_NZ); 57910037SARM gem5 Developers cpsr.c = tc->readCCReg(CCREG_C); 58010037SARM gem5 Developers cpsr.v = tc->readCCReg(CCREG_V); 58110037SARM gem5 Developers return cpsr; 58210037SARM gem5 Developers } 58310037SARM gem5 Developers case MISCREG_DAIF: 58410037SARM gem5 Developers { 58510037SARM gem5 Developers CPSR cpsr = 0; 58610037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 58710037SARM gem5 Developers return cpsr; 58810037SARM gem5 Developers } 58910037SARM gem5 Developers case MISCREG_SP_EL0: 59010338SCurtis.Dunham@arm.com { 59110338SCurtis.Dunham@arm.com return tc->readIntReg(INTREG_SP0); 59210338SCurtis.Dunham@arm.com } 59310037SARM gem5 Developers case MISCREG_SP_EL1: 59410037SARM gem5 Developers { 59510037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 59610037SARM gem5 Developers } 59710037SARM gem5 Developers case MISCREG_SP_EL2: 59810037SARM gem5 Developers { 59910037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 60010037SARM gem5 Developers } 60110037SARM gem5 Developers case MISCREG_SPSEL: 60210037SARM gem5 Developers { 60310037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 60410037SARM gem5 Developers } 60510037SARM gem5 Developers case MISCREG_CURRENTEL: 60610037SARM gem5 Developers { 60710037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 60810037SARM gem5 Developers } 60910037SARM gem5 Developers case MISCREG_L2CTLR: 61010037SARM gem5 Developers { 61110037SARM gem5 Developers // mostly unimplemented, just set NumCPUs field from sim and return 61210037SARM gem5 Developers L2CTLR l2ctlr = 0; 61310037SARM gem5 Developers // b00:1CPU to b11:4CPUs 61410037SARM gem5 Developers l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 61510037SARM gem5 Developers return l2ctlr; 61610037SARM gem5 Developers } 61710037SARM gem5 Developers case MISCREG_DBGDIDR: 61810037SARM gem5 Developers /* For now just implement the version number. 61910037SARM gem5 Developers * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 62010037SARM gem5 Developers */ 6218549Sdaniel.johnson@arm.com return 0x5 << 16; 6228868SMatt.Horsnell@arm.com case MISCREG_DBGDSCRint: 6238868SMatt.Horsnell@arm.com return 0; 6248868SMatt.Horsnell@arm.com case MISCREG_ISR: 6258868SMatt.Horsnell@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 6268868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_HCR), 6278868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_CPSR), 6288868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_SCR)); 6298868SMatt.Horsnell@arm.com case MISCREG_ISR_EL1: 6308868SMatt.Horsnell@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 63110461SAndreas.Sandberg@ARM.com readMiscRegNoEffect(MISCREG_HCR_EL2), 6328868SMatt.Horsnell@arm.com readMiscRegNoEffect(MISCREG_CPSR), 63310461SAndreas.Sandberg@ARM.com readMiscRegNoEffect(MISCREG_SCR_EL3)); 63410037SARM gem5 Developers case MISCREG_DCZID_EL0: 6358868SMatt.Horsnell@arm.com return 0x04; // DC ZVA clear 64-byte chunks 63610037SARM gem5 Developers case MISCREG_HCPTR: 63711150Smitch.hayenga@arm.com { 63810037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 63910037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 64010037SARM gem5 Developers val &= ~(1 << 14); 64110037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 64211150Smitch.hayenga@arm.com // HCPTR is RAO/WI 64310037SARM gem5 Developers bool secure_lookup = haveSecurity && 64410037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 64510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 64610037SARM gem5 Developers if (!secure_lookup) { 64710037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 64810037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 64910037SARM gem5 Developers } 65010037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 65110037SARM gem5 Developers val |= 0x33FF; 65210037SARM gem5 Developers return (val); 65310037SARM gem5 Developers } 65410037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 65510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 65610037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 65710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 65810037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 65910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 66010037SARM gem5 Developers case MISCREG_SCTLR: 66110037SARM gem5 Developers return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 66210037SARM gem5 Developers case MISCREG_SCTLR_EL1: 66310037SARM gem5 Developers return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 66410037SARM gem5 Developers case MISCREG_SCTLR_EL2: 66510037SARM gem5 Developers case MISCREG_SCTLR_EL3: 66610037SARM gem5 Developers case MISCREG_HSCTLR: 66710037SARM gem5 Developers return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 66810037SARM gem5 Developers 66910037SARM gem5 Developers case MISCREG_ID_PFR0: 67010844Sandreas.sandberg@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 67111772SCurtis.Dunham@arm.com return 0x00000031; 67211772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 67311772SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 67411772SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 67511774SCurtis.Dunham@arm.com return 0x00000001 67611774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 67711774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 67811774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 67911774SCurtis.Dunham@arm.com } 68011774SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 68111774SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 68211773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 68313531Sjairo.balart@metempsy.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 68413531Sjairo.balart@metempsy.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 68513531Sjairo.balart@metempsy.com case MISCREG_ID_AA64PFR1_EL1: 68613531Sjairo.balart@metempsy.com return 0; // bits [63:0] RES0 (reserved for future use) 68713531Sjairo.balart@metempsy.com 68811773SCurtis.Dunham@arm.com // Generic Timer registers 68911773SCurtis.Dunham@arm.com case MISCREG_CNTHV_CTL_EL2: 69011772SCurtis.Dunham@arm.com case MISCREG_CNTHV_CVAL_EL2: 69110037SARM gem5 Developers case MISCREG_CNTHV_TVAL_EL2: 69212816Sgiacomo.travaglini@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 69312816Sgiacomo.travaglini@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 69412816Sgiacomo.travaglini@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 69510844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 69610844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 69710844Sandreas.sandberg@arm.com 69810844Sandreas.sandberg@arm.com default: 69910844Sandreas.sandberg@arm.com break; 70010844Sandreas.sandberg@arm.com 70113531Sjairo.balart@metempsy.com } 70213531Sjairo.balart@metempsy.com return readMiscRegNoEffect(misc_reg); 70313531Sjairo.balart@metempsy.com} 70413531Sjairo.balart@metempsy.com 70510188Sgeoffrey.blake@arm.comvoid 70610037SARM gem5 DevelopersISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 70710037SARM gem5 Developers{ 7087405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 7097405SAli.Saidi@ARM.com 7107405SAli.Saidi@ARM.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 7117405SAli.Saidi@ARM.com const auto &map = getMiscIndices(misc_reg); 7127405SAli.Saidi@ARM.com int lower = map.first, upper = map.second; 7137405SAli.Saidi@ARM.com 7147405SAli.Saidi@ARM.com auto v = (val & ~reg.wi()) | reg.rao(); 7157405SAli.Saidi@ARM.com if (upper > 0) { 7167614Sminkyu.jeong@arm.com miscRegs[lower] = bits(v, 31, 0); 71712478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 71812478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 71912478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 72012478SCurtis.Dunham@arm.com } else { 72112478SCurtis.Dunham@arm.com miscRegs[lower] = v; 72211771SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 72312478SCurtis.Dunham@arm.com misc_reg, lower, v); 72412478SCurtis.Dunham@arm.com } 72510037SARM gem5 Developers} 72612478SCurtis.Dunham@arm.com 72710037SARM gem5 Developersvoid 72812478SCurtis.Dunham@arm.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 72910037SARM gem5 Developers{ 73012478SCurtis.Dunham@arm.com 73110037SARM gem5 Developers MiscReg newVal = val; 7327405SAli.Saidi@ARM.com bool secure_lookup; 7337405SAli.Saidi@ARM.com SCR scr; 7347405SAli.Saidi@ARM.com 7357405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7367405SAli.Saidi@ARM.com updateRegMap(val); 7377749SAli.Saidi@ARM.com 7387405SAli.Saidi@ARM.com 73910037SARM gem5 Developers CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 74010037SARM gem5 Developers int old_mode = old_cpsr.mode; 7418284SAli.Saidi@ARM.com CPSR cpsr = val; 7427405SAli.Saidi@ARM.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 7437405SAli.Saidi@ARM.com getITBPtr(tc)->invalidateMiscReg(); 7447749SAli.Saidi@ARM.com getDTBPtr(tc)->invalidateMiscReg(); 7457749SAli.Saidi@ARM.com } 7467749SAli.Saidi@ARM.com 7477749SAli.Saidi@ARM.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7487405SAli.Saidi@ARM.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 74912510Sgiacomo.travaglini@arm.com PCState pc = tc->pcState(); 75012406Sgabeblack@google.com pc.nextThumb(cpsr.t); 75112406Sgabeblack@google.com pc.nextJazelle(cpsr.j); 7527749SAli.Saidi@ARM.com pc.illegalExec(cpsr.il == 1); 7537749SAli.Saidi@ARM.com 7547614Sminkyu.jeong@arm.com // Follow slightly different semantics if a CheckerCPU object 7557614Sminkyu.jeong@arm.com // is connected 7567720Sgblack@eecs.umich.edu CheckerCPU *checker = tc->getCheckerCpuPtr(); 7577720Sgblack@eecs.umich.edu if (checker) { 7587720Sgblack@eecs.umich.edu tc->pcStateNoRecord(pc); 75912763Sgiacomo.travaglini@arm.com } else { 7608887Sgeoffrey.blake@arm.com tc->pcState(pc); 7618887Sgeoffrey.blake@arm.com } 7628887Sgeoffrey.blake@arm.com } else { 7638887Sgeoffrey.blake@arm.com#ifndef NDEBUG 7648887Sgeoffrey.blake@arm.com if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 7658887Sgeoffrey.blake@arm.com if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 7668887Sgeoffrey.blake@arm.com warn("Unimplemented system register %s write with %#x.\n", 7678887Sgeoffrey.blake@arm.com miscRegName[misc_reg], val); 7688887Sgeoffrey.blake@arm.com else 7697408Sgblack@eecs.umich.edu panic("Unimplemented system register %s write with %#x.\n", 77010037SARM gem5 Developers miscRegName[misc_reg], val); 77110037SARM gem5 Developers } 77210037SARM gem5 Developers#endif 77310037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 77410037SARM gem5 Developers case MISCREG_CPACR: 77510037SARM gem5 Developers { 77610037SARM gem5 Developers 77710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 77810037SARM gem5 Developers CPACR cpacrMask = 0; 77910037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 78010037SARM gem5 Developers // be writable 7817408Sgblack@eecs.umich.edu cpacrMask.cp10 = ones; 7827408Sgblack@eecs.umich.edu cpacrMask.cp11 = ones; 7838206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 7848206SWilliam.Wang@arm.com 7858206SWilliam.Wang@arm.com // Security Extensions may limit the writability of CPACR 7868206SWilliam.Wang@arm.com if (haveSecurity) { 7878206SWilliam.Wang@arm.com scr = readMiscRegNoEffect(MISCREG_SCR); 7888206SWilliam.Wang@arm.com CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 7898206SWilliam.Wang@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 7908206SWilliam.Wang@arm.com NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 79110037SARM gem5 Developers // NB: Skipping the full loop, here 79210037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 79310037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 79410037SARM gem5 Developers } 79510037SARM gem5 Developers } 79612667Schuan.zhu@arm.com 79710037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 79810037SARM gem5 Developers newVal &= cpacrMask; 79910037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 80010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 80110037SARM gem5 Developers miscRegName[misc_reg], newVal); 80210037SARM gem5 Developers } 80310037SARM gem5 Developers break; 80410037SARM gem5 Developers case MISCREG_CPTR_EL2: 8058206SWilliam.Wang@arm.com { 80610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 80710037SARM gem5 Developers CPTR cptrMask = 0; 80810037SARM gem5 Developers cptrMask.tcpac = ones; 80910037SARM gem5 Developers cptrMask.tta = ones; 81010037SARM gem5 Developers cptrMask.tfp = ones; 81110037SARM gem5 Developers newVal &= cptrMask; 81210037SARM gem5 Developers cptrMask = 0; 81310037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 81410037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 81510037SARM gem5 Developers newVal |= cptrMask; 81610037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 81710037SARM gem5 Developers miscRegName[misc_reg], newVal); 81810037SARM gem5 Developers } 81910037SARM gem5 Developers break; 82010037SARM gem5 Developers case MISCREG_CPTR_EL3: 82110037SARM gem5 Developers { 82210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 82310037SARM gem5 Developers CPTR cptrMask = 0; 82410037SARM gem5 Developers cptrMask.tcpac = ones; 82510037SARM gem5 Developers cptrMask.tta = ones; 82610037SARM gem5 Developers cptrMask.tfp = ones; 82710037SARM gem5 Developers newVal &= cptrMask; 82810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 82910037SARM gem5 Developers miscRegName[misc_reg], newVal); 83010037SARM gem5 Developers } 83110037SARM gem5 Developers break; 83210037SARM gem5 Developers case MISCREG_CSSELR: 83310037SARM gem5 Developers warn_once("The csselr register isn't implemented.\n"); 83410037SARM gem5 Developers return; 8358206SWilliam.Wang@arm.com 8368206SWilliam.Wang@arm.com case MISCREG_DC_ZVA_Xt: 8377408Sgblack@eecs.umich.edu warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 8387408Sgblack@eecs.umich.edu return; 8397408Sgblack@eecs.umich.edu 8407731SAli.Saidi@ARM.com case MISCREG_FPSCR: 8418206SWilliam.Wang@arm.com { 84210037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 84310037SARM gem5 Developers FPSCR fpscrMask = 0; 84410037SARM gem5 Developers fpscrMask.ioc = ones; 84510037SARM gem5 Developers fpscrMask.dzc = ones; 84610037SARM gem5 Developers fpscrMask.ofc = ones; 8477408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8487408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8497408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 8507408Sgblack@eecs.umich.edu fpscrMask.ioe = ones; 8517408Sgblack@eecs.umich.edu fpscrMask.dze = ones; 8527408Sgblack@eecs.umich.edu fpscrMask.ofe = ones; 8537408Sgblack@eecs.umich.edu fpscrMask.ufe = ones; 8547408Sgblack@eecs.umich.edu fpscrMask.ixe = ones; 8557408Sgblack@eecs.umich.edu fpscrMask.ide = ones; 8567408Sgblack@eecs.umich.edu fpscrMask.len = ones; 85710037SARM gem5 Developers fpscrMask.stride = ones; 85810037SARM gem5 Developers fpscrMask.rMode = ones; 85910037SARM gem5 Developers fpscrMask.fz = ones; 86010037SARM gem5 Developers fpscrMask.dn = ones; 86110037SARM gem5 Developers fpscrMask.ahp = ones; 86210037SARM gem5 Developers fpscrMask.qc = ones; 8637408Sgblack@eecs.umich.edu fpscrMask.v = ones; 8647408Sgblack@eecs.umich.edu fpscrMask.c = ones; 8657408Sgblack@eecs.umich.edu fpscrMask.z = ones; 8667408Sgblack@eecs.umich.edu fpscrMask.n = ones; 8677408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 8687408Sgblack@eecs.umich.edu (readMiscRegNoEffect(MISCREG_FPSCR) & 8697408Sgblack@eecs.umich.edu ~(uint32_t)fpscrMask); 8707408Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 8717408Sgblack@eecs.umich.edu } 8727408Sgblack@eecs.umich.edu break; 8737408Sgblack@eecs.umich.edu case MISCREG_FPSR: 8747408Sgblack@eecs.umich.edu { 87510037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87610037SARM gem5 Developers FPSCR fpscrMask = 0; 8779377Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8787408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8797408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 88010037SARM gem5 Developers fpscrMask.ufc = ones; 88110037SARM gem5 Developers fpscrMask.ixc = ones; 88210037SARM gem5 Developers fpscrMask.idc = ones; 88310037SARM gem5 Developers fpscrMask.qc = ones; 88410037SARM gem5 Developers fpscrMask.v = ones; 88510037SARM gem5 Developers fpscrMask.c = ones; 88610037SARM gem5 Developers fpscrMask.z = ones; 88710037SARM gem5 Developers fpscrMask.n = ones; 88810037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 88910037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 89010037SARM gem5 Developers ~(uint32_t)fpscrMask); 89110037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 89210037SARM gem5 Developers } 89310037SARM gem5 Developers break; 89410037SARM gem5 Developers case MISCREG_FPCR: 89510037SARM gem5 Developers { 89610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 89710037SARM gem5 Developers FPSCR fpscrMask = 0; 89810037SARM gem5 Developers fpscrMask.len = ones; 89910037SARM gem5 Developers fpscrMask.stride = ones; 90010037SARM gem5 Developers fpscrMask.rMode = ones; 90110037SARM gem5 Developers fpscrMask.fz = ones; 90210037SARM gem5 Developers fpscrMask.dn = ones; 90310037SARM gem5 Developers fpscrMask.ahp = ones; 90410037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 90510037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 90610037SARM gem5 Developers ~(uint32_t)fpscrMask); 90710037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 90810037SARM gem5 Developers } 90910037SARM gem5 Developers break; 91010037SARM gem5 Developers case MISCREG_CPSR_Q: 91110037SARM gem5 Developers { 91210037SARM gem5 Developers assert(!(newVal & ~CpsrMaskQ)); 91310037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 91410037SARM gem5 Developers misc_reg = MISCREG_CPSR; 91510037SARM gem5 Developers } 91610037SARM gem5 Developers break; 9178302SAli.Saidi@ARM.com case MISCREG_FPSCR_QC: 9188302SAli.Saidi@ARM.com { 9198302SAli.Saidi@ARM.com newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 92010037SARM gem5 Developers (newVal & FpscrQcMask); 9218302SAli.Saidi@ARM.com misc_reg = MISCREG_FPSCR; 9228302SAli.Saidi@ARM.com } 9238302SAli.Saidi@ARM.com break; 9247783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 9257783SGiacomo.Gabrielli@arm.com { 92610037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 92710037SARM gem5 Developers (newVal & FpscrExcMask); 9287783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9297783SGiacomo.Gabrielli@arm.com } 9307783SGiacomo.Gabrielli@arm.com break; 9317783SGiacomo.Gabrielli@arm.com case MISCREG_FPEXC: 9327783SGiacomo.Gabrielli@arm.com { 93310037SARM gem5 Developers // vfpv3 architecture, section B.6.1 of DDI04068 93410037SARM gem5 Developers // bit 29 - valid only if fpexc[31] is 0 9357783SGiacomo.Gabrielli@arm.com const uint32_t fpexcMask = 0x60000000; 9367783SGiacomo.Gabrielli@arm.com newVal = (newVal & fpexcMask) | 9377783SGiacomo.Gabrielli@arm.com (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 9387408Sgblack@eecs.umich.edu } 9397408Sgblack@eecs.umich.edu break; 9408206SWilliam.Wang@arm.com case MISCREG_HCR: 9418206SWilliam.Wang@arm.com { 9427408Sgblack@eecs.umich.edu if (!haveVirtualization) 9437408Sgblack@eecs.umich.edu return; 94410037SARM gem5 Developers } 9457408Sgblack@eecs.umich.edu break; 9467408Sgblack@eecs.umich.edu case MISCREG_IFSR: 94710037SARM gem5 Developers { 94810037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 94910037SARM gem5 Developers const uint32_t ifsrMask = 95010037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 95110037SARM gem5 Developers newVal = newVal & ~ifsrMask; 95210037SARM gem5 Developers } 95310037SARM gem5 Developers break; 95410037SARM gem5 Developers case MISCREG_DFSR: 95510037SARM gem5 Developers { 95610037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 95710037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 95810037SARM gem5 Developers newVal = newVal & ~dfsrMask; 95910037SARM gem5 Developers } 96010037SARM gem5 Developers break; 96110037SARM gem5 Developers case MISCREG_AMAIR0: 96210037SARM gem5 Developers case MISCREG_AMAIR1: 96310037SARM gem5 Developers { 96410037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 96510037SARM gem5 Developers // Valid only with LPAE 96610037SARM gem5 Developers if (!haveLPAE) 96710037SARM gem5 Developers return; 96810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 96910037SARM gem5 Developers } 97010037SARM gem5 Developers break; 97110037SARM gem5 Developers case MISCREG_SCR: 97210037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 97310037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 97410037SARM gem5 Developers break; 97510037SARM gem5 Developers case MISCREG_SCTLR: 97610037SARM gem5 Developers { 97710037SARM gem5 Developers DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 97810037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 97912406Sgabeblack@google.com 98012406Sgabeblack@google.com MiscRegIndex sctlr_idx; 98110037SARM gem5 Developers if (haveSecurity && !highestELIs64 && !scr.ns) { 9827408Sgblack@eecs.umich.edu sctlr_idx = MISCREG_SCTLR_S; 9837408Sgblack@eecs.umich.edu } else { 9847408Sgblack@eecs.umich.edu sctlr_idx = MISCREG_SCTLR_NS; 98510037SARM gem5 Developers } 98612639Sgiacomo.travaglini@arm.com 98712639Sgiacomo.travaglini@arm.com SCTLR sctlr = miscRegs[sctlr_idx]; 98812639Sgiacomo.travaglini@arm.com SCTLR new_sctlr = newVal; 98912639Sgiacomo.travaglini@arm.com new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 99012639Sgiacomo.travaglini@arm.com miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 99112639Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 99212639Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 99312639Sgiacomo.travaglini@arm.com } 99410037SARM gem5 Developers case MISCREG_MIDR: 9957408Sgblack@eecs.umich.edu case MISCREG_ID_PFR0: 99610037SARM gem5 Developers case MISCREG_ID_PFR1: 99710037SARM gem5 Developers case MISCREG_ID_DFR0: 99812406Sgabeblack@google.com case MISCREG_ID_MMFR0: 99912406Sgabeblack@google.com case MISCREG_ID_MMFR1: 10007408Sgblack@eecs.umich.edu case MISCREG_ID_MMFR2: 10019385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 10029385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 10039385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 100410461SAndreas.Sandberg@ARM.com case MISCREG_ID_ISAR2: 10059385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 10069385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 10079385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 10089385SAndreas.Sandberg@arm.com 10099385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 10109385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 10119385SAndreas.Sandberg@arm.com case MISCREG_TLBTR: 10129385SAndreas.Sandberg@arm.com case MISCREG_MVFR0: 10139385SAndreas.Sandberg@arm.com case MISCREG_MVFR1: 10149385SAndreas.Sandberg@arm.com 10159385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64AFR0_EL1: 10169385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64AFR1_EL1: 10179385SAndreas.Sandberg@arm.com case MISCREG_ID_AA64DFR0_EL1: 10187408Sgblack@eecs.umich.edu case MISCREG_ID_AA64DFR1_EL1: 10197408Sgblack@eecs.umich.edu case MISCREG_ID_AA64ISAR0_EL1: 10207408Sgblack@eecs.umich.edu case MISCREG_ID_AA64ISAR1_EL1: 102110037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 102210037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 102310037SARM gem5 Developers case MISCREG_ID_AA64MMFR2_EL1: 102410037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 102510037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 102610037SARM gem5 Developers // ID registers are constants. 102710037SARM gem5 Developers return; 102810037SARM gem5 Developers 102910037SARM gem5 Developers // TLB Invalidate All 103013116Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 103110037SARM gem5 Developers { 103210037SARM gem5 Developers assert32(tc); 10339385SAndreas.Sandberg@arm.com scr = readMiscReg(MISCREG_SCR, tc); 10347408Sgblack@eecs.umich.edu 10359385SAndreas.Sandberg@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 103612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 103712605Sgiacomo.travaglini@arm.com return; 103812605Sgiacomo.travaglini@arm.com } 103912605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 104012605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLIS: 104112605Sgiacomo.travaglini@arm.com { 104212605Sgiacomo.travaglini@arm.com assert32(tc); 104312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 104412605Sgiacomo.travaglini@arm.com 104512605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 104612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 10477408Sgblack@eecs.umich.edu return; 104812605Sgiacomo.travaglini@arm.com } 104912605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 105012605Sgiacomo.travaglini@arm.com case MISCREG_ITLBIALL: 105112605Sgiacomo.travaglini@arm.com { 105212605Sgiacomo.travaglini@arm.com assert32(tc); 105312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 105412605Sgiacomo.travaglini@arm.com 105512605Sgiacomo.travaglini@arm.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 105612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 10577408Sgblack@eecs.umich.edu return; 105812605Sgiacomo.travaglini@arm.com } 105912605Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 106012605Sgiacomo.travaglini@arm.com case MISCREG_DTLBIALL: 106112605Sgiacomo.travaglini@arm.com { 106212605Sgiacomo.travaglini@arm.com assert32(tc); 106312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 106412605Sgiacomo.travaglini@arm.com 106512605Sgiacomo.travaglini@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 106612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 10677408Sgblack@eecs.umich.edu return; 106812605Sgiacomo.travaglini@arm.com } 106912605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA 107012605Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 107112605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 107212605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 107312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 107412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 107512605Sgiacomo.travaglini@arm.com { 107612605Sgiacomo.travaglini@arm.com assert32(tc); 107712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 107812605Sgiacomo.travaglini@arm.com 107912605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 108012605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 108112576Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 108212605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 108312605Sgiacomo.travaglini@arm.com 108412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 108512605Sgiacomo.travaglini@arm.com return; 108612605Sgiacomo.travaglini@arm.com } 108712605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Inner Shareable 108812605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAIS: 108912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 109012605Sgiacomo.travaglini@arm.com { 109112605Sgiacomo.travaglini@arm.com assert32(tc); 109212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 109312605Sgiacomo.travaglini@arm.com 109412605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 109512605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 109612576Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 109712605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 109812605Sgiacomo.travaglini@arm.com 109912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 110012605Sgiacomo.travaglini@arm.com return; 110112605Sgiacomo.travaglini@arm.com } 110212605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match 110312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASID: 110412605Sgiacomo.travaglini@arm.com { 110512605Sgiacomo.travaglini@arm.com assert32(tc); 110612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 110712605Sgiacomo.travaglini@arm.com 110812605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 110912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 111012605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 111112605Sgiacomo.travaglini@arm.com 111212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 111312605Sgiacomo.travaglini@arm.com return; 111412605Sgiacomo.travaglini@arm.com } 111512605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match, Inner Shareable 111612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASIDIS: 111712605Sgiacomo.travaglini@arm.com { 111812605Sgiacomo.travaglini@arm.com assert32(tc); 111912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 112012605Sgiacomo.travaglini@arm.com 112112605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 112212605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 11237408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 112412605Sgiacomo.travaglini@arm.com 112512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 112612605Sgiacomo.travaglini@arm.com return; 112712605Sgiacomo.travaglini@arm.com } 112812605Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 112912605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 113012605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 113112605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID 113212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 113312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 113412605Sgiacomo.travaglini@arm.com { 113512605Sgiacomo.travaglini@arm.com assert32(tc); 113612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 113712605Sgiacomo.travaglini@arm.com 113812605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 113912605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 114012576Sgiacomo.travaglini@arm.com 114112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 114212605Sgiacomo.travaglini@arm.com return; 114312605Sgiacomo.travaglini@arm.com } 114412605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 114512605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAIS: 114612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 114712605Sgiacomo.travaglini@arm.com { 114812605Sgiacomo.travaglini@arm.com assert32(tc); 114912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 115012605Sgiacomo.travaglini@arm.com 115112605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 115212605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 115312576Sgiacomo.travaglini@arm.com 115412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 115512605Sgiacomo.travaglini@arm.com return; 115612605Sgiacomo.travaglini@arm.com } 115712605Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 115812605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 115912605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 116012605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode 116112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAH: 116212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 116312605Sgiacomo.travaglini@arm.com { 116412605Sgiacomo.travaglini@arm.com assert32(tc); 116512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 116612605Sgiacomo.travaglini@arm.com 116712605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 116812605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 116912576Sgiacomo.travaglini@arm.com 117012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 117112605Sgiacomo.travaglini@arm.com return; 117212605Sgiacomo.travaglini@arm.com } 117312605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode, Inner Shareable 117412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAHIS: 117512605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 117612605Sgiacomo.travaglini@arm.com { 117712605Sgiacomo.travaglini@arm.com assert32(tc); 117812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 117912605Sgiacomo.travaglini@arm.com 118012605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 118112605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 118212576Sgiacomo.travaglini@arm.com 118312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 118412605Sgiacomo.travaglini@arm.com return; 118512605Sgiacomo.travaglini@arm.com } 118612605Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 118712605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 118812605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 118912605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2 119012605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 119112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 119212605Sgiacomo.travaglini@arm.com { 119312605Sgiacomo.travaglini@arm.com assert32(tc); 119412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 119512605Sgiacomo.travaglini@arm.com 119612605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 119712605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 119812577Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 119912605Sgiacomo.travaglini@arm.com 120012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 120112605Sgiacomo.travaglini@arm.com return; 120212605Sgiacomo.travaglini@arm.com } 120312605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2, 120412605Sgiacomo.travaglini@arm.com // Inner Shareable 120512605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 120612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 120712605Sgiacomo.travaglini@arm.com { 120812605Sgiacomo.travaglini@arm.com assert32(tc); 120912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 121012605Sgiacomo.travaglini@arm.com 121112605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 121212605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 121312577Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 121412605Sgiacomo.travaglini@arm.com 121512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 121612605Sgiacomo.travaglini@arm.com return; 121712605Sgiacomo.travaglini@arm.com } 121812605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by VA 121912605Sgiacomo.travaglini@arm.com case MISCREG_ITLBIMVA: 122012605Sgiacomo.travaglini@arm.com { 122112605Sgiacomo.travaglini@arm.com assert32(tc); 122212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 122312605Sgiacomo.travaglini@arm.com 122412605Sgiacomo.travaglini@arm.com ITLBIMVA tlbiOp(EL1, 122512605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 122610037SARM gem5 Developers mbits(newVal, 31, 12), 122712605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 122812605Sgiacomo.travaglini@arm.com 122912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 123012605Sgiacomo.travaglini@arm.com return; 123112605Sgiacomo.travaglini@arm.com } 123212605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by VA 123312605Sgiacomo.travaglini@arm.com case MISCREG_DTLBIMVA: 123412605Sgiacomo.travaglini@arm.com { 123512605Sgiacomo.travaglini@arm.com assert32(tc); 123612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 123712605Sgiacomo.travaglini@arm.com 123812605Sgiacomo.travaglini@arm.com DTLBIMVA tlbiOp(EL1, 123912605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 124010037SARM gem5 Developers mbits(newVal, 31, 12), 124112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 124212605Sgiacomo.travaglini@arm.com 124312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 124412605Sgiacomo.travaglini@arm.com return; 124512605Sgiacomo.travaglini@arm.com } 124612605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by ASID match 124712605Sgiacomo.travaglini@arm.com case MISCREG_ITLBIASID: 124812605Sgiacomo.travaglini@arm.com { 124912605Sgiacomo.travaglini@arm.com assert32(tc); 125012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 125112605Sgiacomo.travaglini@arm.com 125212605Sgiacomo.travaglini@arm.com ITLBIASID tlbiOp(EL1, 125312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 125410037SARM gem5 Developers bits(newVal, 7,0)); 125512605Sgiacomo.travaglini@arm.com 125612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 125712605Sgiacomo.travaglini@arm.com return; 125812605Sgiacomo.travaglini@arm.com } 125912605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by ASID match 126012605Sgiacomo.travaglini@arm.com case MISCREG_DTLBIASID: 126112605Sgiacomo.travaglini@arm.com { 126212605Sgiacomo.travaglini@arm.com assert32(tc); 126312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 126412605Sgiacomo.travaglini@arm.com 126512605Sgiacomo.travaglini@arm.com DTLBIASID tlbiOp(EL1, 126612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 126710037SARM gem5 Developers bits(newVal, 7,0)); 126812605Sgiacomo.travaglini@arm.com 126912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 127012605Sgiacomo.travaglini@arm.com return; 127112605Sgiacomo.travaglini@arm.com } 127212605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp 127312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLNSNH: 127412605Sgiacomo.travaglini@arm.com { 127512605Sgiacomo.travaglini@arm.com assert32(tc); 127612605Sgiacomo.travaglini@arm.com 127712605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 127812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 127912605Sgiacomo.travaglini@arm.com return; 128010037SARM gem5 Developers } 128112605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 128212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLNSNHIS: 128312605Sgiacomo.travaglini@arm.com { 128412605Sgiacomo.travaglini@arm.com assert32(tc); 128512605Sgiacomo.travaglini@arm.com 128612605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 128712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 128812605Sgiacomo.travaglini@arm.com return; 128910037SARM gem5 Developers } 129012605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode 129112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLH: 129212605Sgiacomo.travaglini@arm.com { 129312605Sgiacomo.travaglini@arm.com assert32(tc); 129412605Sgiacomo.travaglini@arm.com 129512605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 129612605Sgiacomo.travaglini@arm.com tlbiOp(tc); 129712605Sgiacomo.travaglini@arm.com return; 129810037SARM gem5 Developers } 129912605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode, Inner Shareable 130012605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALLHIS: 130112605Sgiacomo.travaglini@arm.com { 130212605Sgiacomo.travaglini@arm.com assert32(tc); 130312605Sgiacomo.travaglini@arm.com 130412605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 130512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 130612605Sgiacomo.travaglini@arm.com return; 130710037SARM gem5 Developers } 130812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3 130912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3: 131012605Sgiacomo.travaglini@arm.com { 131112605Sgiacomo.travaglini@arm.com assert64(tc); 131212605Sgiacomo.travaglini@arm.com 131312605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 131412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 131512605Sgiacomo.travaglini@arm.com return; 131612605Sgiacomo.travaglini@arm.com } 131712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3, Inner Shareable 131812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3IS: 131912605Sgiacomo.travaglini@arm.com { 132012605Sgiacomo.travaglini@arm.com assert64(tc); 132112605Sgiacomo.travaglini@arm.com 132212605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 132312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 132412605Sgiacomo.travaglini@arm.com return; 132510037SARM gem5 Developers } 132612605Sgiacomo.travaglini@arm.com // @todo: uncomment this to enable Virtualization 132712605Sgiacomo.travaglini@arm.com // case MISCREG_TLBI_ALLE2IS: 132812605Sgiacomo.travaglini@arm.com // case MISCREG_TLBI_ALLE2: 132912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1 133012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE1: 133112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1: 133212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLS12E1: 133313549Sanouk.vanlaer@arm.com // @todo: handle VMID and stage 2 to enable Virtualization 133413549Sanouk.vanlaer@arm.com { 133513549Sanouk.vanlaer@arm.com assert64(tc); 133613549Sanouk.vanlaer@arm.com scr = readMiscReg(MISCREG_SCR, tc); 133713549Sanouk.vanlaer@arm.com 133813549Sanouk.vanlaer@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 133913549Sanouk.vanlaer@arm.com tlbiOp(tc); 134013549Sanouk.vanlaer@arm.com return; 134113549Sanouk.vanlaer@arm.com } 134213549Sanouk.vanlaer@arm.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 134313549Sanouk.vanlaer@arm.com case MISCREG_TLBI_ALLE1IS: 134412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 134510037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1IS: 134610037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 134710037SARM gem5 Developers { 134810037SARM gem5 Developers assert64(tc); 134912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 135012605Sgiacomo.travaglini@arm.com 135112605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 135212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 135312605Sgiacomo.travaglini@arm.com return; 135412605Sgiacomo.travaglini@arm.com } 135512605Sgiacomo.travaglini@arm.com // VAEx(IS) and VALEx(IS) are the same because TLBs 135612605Sgiacomo.travaglini@arm.com // only store entries 135712605Sgiacomo.travaglini@arm.com // from the last level of translation table walks 135812605Sgiacomo.travaglini@arm.com // @todo: handle VMID to enable Virtualization 135912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3 136012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE3_Xt: 136112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE3_Xt: 136212605Sgiacomo.travaglini@arm.com { 136312605Sgiacomo.travaglini@arm.com assert64(tc); 136412605Sgiacomo.travaglini@arm.com 136512605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 136612605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 136712605Sgiacomo.travaglini@arm.com 0xbeef); 136812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 136912605Sgiacomo.travaglini@arm.com return; 137012605Sgiacomo.travaglini@arm.com } 137112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 137210037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 137310037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 137412605Sgiacomo.travaglini@arm.com { 137512605Sgiacomo.travaglini@arm.com assert64(tc); 137612605Sgiacomo.travaglini@arm.com 137712605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 137812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 137912605Sgiacomo.travaglini@arm.com 0xbeef); 138012605Sgiacomo.travaglini@arm.com 138112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 138212605Sgiacomo.travaglini@arm.com return; 138312605Sgiacomo.travaglini@arm.com } 138412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2 138512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2_Xt: 138612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2_Xt: 138710037SARM gem5 Developers { 138810037SARM gem5 Developers assert64(tc); 138912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 139012605Sgiacomo.travaglini@arm.com 139112605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 139212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 139312605Sgiacomo.travaglini@arm.com 0xbeef); 139412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 139512605Sgiacomo.travaglini@arm.com return; 139612605Sgiacomo.travaglini@arm.com } 139712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 139812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2IS_Xt: 139912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2IS_Xt: 140012605Sgiacomo.travaglini@arm.com { 140112605Sgiacomo.travaglini@arm.com assert64(tc); 140212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 140312605Sgiacomo.travaglini@arm.com 140412605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 140512605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 140612605Sgiacomo.travaglini@arm.com 0xbeef); 140712605Sgiacomo.travaglini@arm.com 140812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 140912605Sgiacomo.travaglini@arm.com return; 141012605Sgiacomo.travaglini@arm.com } 141112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1 141212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 141310037SARM gem5 Developers case MISCREG_TLBI_VALE1_Xt: 141410037SARM gem5 Developers { 141512605Sgiacomo.travaglini@arm.com assert64(tc); 141612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 141712605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 141812605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 141912605Sgiacomo.travaglini@arm.com 142012605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 142112605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 142212605Sgiacomo.travaglini@arm.com asid); 142312605Sgiacomo.travaglini@arm.com 142412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 142512605Sgiacomo.travaglini@arm.com return; 142612605Sgiacomo.travaglini@arm.com } 142712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 142812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1IS_Xt: 142912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1IS_Xt: 143012605Sgiacomo.travaglini@arm.com { 143112605Sgiacomo.travaglini@arm.com assert64(tc); 143212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 143312605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 143412605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 143512605Sgiacomo.travaglini@arm.com 143612605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 143712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 143812605Sgiacomo.travaglini@arm.com asid); 143912605Sgiacomo.travaglini@arm.com 144012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 144112605Sgiacomo.travaglini@arm.com return; 144212605Sgiacomo.travaglini@arm.com } 144310037SARM gem5 Developers // AArch64 TLB Invalidate by ASID, EL1 144410037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 144512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 144612605Sgiacomo.travaglini@arm.com { 144712605Sgiacomo.travaglini@arm.com assert64(tc); 144812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 144912605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 145012605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 145112605Sgiacomo.travaglini@arm.com 145212605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 145312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 145412605Sgiacomo.travaglini@arm.com return; 145512605Sgiacomo.travaglini@arm.com } 145612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 145712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1IS_Xt: 145812605Sgiacomo.travaglini@arm.com { 145910037SARM gem5 Developers assert64(tc); 146012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 146112605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 146212605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 146312605Sgiacomo.travaglini@arm.com 146412605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 146512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 146612605Sgiacomo.travaglini@arm.com return; 146712605Sgiacomo.travaglini@arm.com } 146812605Sgiacomo.travaglini@arm.com // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 146912605Sgiacomo.travaglini@arm.com // entries from the last level of translation table walks 147012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 147112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 147210037SARM gem5 Developers case MISCREG_TLBI_VAALE1_Xt: 147312605Sgiacomo.travaglini@arm.com { 147412605Sgiacomo.travaglini@arm.com assert64(tc); 147512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147612605Sgiacomo.travaglini@arm.com 147712605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 147812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 147912605Sgiacomo.travaglini@arm.com 148012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 148112605Sgiacomo.travaglini@arm.com return; 148212605Sgiacomo.travaglini@arm.com } 148310037SARM gem5 Developers // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 148410037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 148512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1IS_Xt: 148612605Sgiacomo.travaglini@arm.com { 148712605Sgiacomo.travaglini@arm.com assert64(tc); 148812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 148912605Sgiacomo.travaglini@arm.com 149012605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 149112605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 149212605Sgiacomo.travaglini@arm.com 149312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 149412605Sgiacomo.travaglini@arm.com return; 149512605Sgiacomo.travaglini@arm.com } 149612605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 149712605Sgiacomo.travaglini@arm.com // Stage 2, EL1 149812605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1_Xt: 149910037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1_Xt: 150010037SARM gem5 Developers { 150112605Sgiacomo.travaglini@arm.com assert64(tc); 150212605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 150312605Sgiacomo.travaglini@arm.com 150412605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 150512605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 150612605Sgiacomo.travaglini@arm.com 150712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 150812605Sgiacomo.travaglini@arm.com return; 150912605Sgiacomo.travaglini@arm.com } 151012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 151112605Sgiacomo.travaglini@arm.com // Stage 2, EL1, Inner Shareable 151212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1IS_Xt: 151312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2LE1IS_Xt: 151412605Sgiacomo.travaglini@arm.com { 151512605Sgiacomo.travaglini@arm.com assert64(tc); 151612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 151712605Sgiacomo.travaglini@arm.com 151812605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 151912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 152012605Sgiacomo.travaglini@arm.com 152112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 152212605Sgiacomo.travaglini@arm.com return; 152312605Sgiacomo.travaglini@arm.com } 152412605Sgiacomo.travaglini@arm.com case MISCREG_ACTLR: 152512605Sgiacomo.travaglini@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 152612605Sgiacomo.travaglini@arm.com break; 152712605Sgiacomo.travaglini@arm.com 152810037SARM gem5 Developers case MISCREG_PMXEVTYPER_PMCCFILTR: 152912605Sgiacomo.travaglini@arm.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 153012605Sgiacomo.travaglini@arm.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 153112605Sgiacomo.travaglini@arm.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 153212605Sgiacomo.travaglini@arm.com pmu->setMiscReg(misc_reg, newVal); 153312605Sgiacomo.travaglini@arm.com break; 153412605Sgiacomo.travaglini@arm.com 153512605Sgiacomo.travaglini@arm.com 153612605Sgiacomo.travaglini@arm.com case MISCREG_HSTR: // TJDBX, now redifined to be RES0 153712605Sgiacomo.travaglini@arm.com { 153812605Sgiacomo.travaglini@arm.com HSTR hstrMask = 0; 15397583SAli.Saidi@arm.com hstrMask.tjdbx = 1; 15407583SAli.Saidi@arm.com newVal &= ~((uint32_t) hstrMask); 15417583SAli.Saidi@arm.com break; 154210461SAndreas.Sandberg@ARM.com } 154310461SAndreas.Sandberg@ARM.com case MISCREG_HCPTR: 154410461SAndreas.Sandberg@ARM.com { 154510461SAndreas.Sandberg@ARM.com // If a CP bit in NSACR is 0 then the corresponding bit in 154610461SAndreas.Sandberg@ARM.com // HCPTR is RAO/WI. Same applies to NSASEDIS 154710461SAndreas.Sandberg@ARM.com secure_lookup = haveSecurity && 15487583SAli.Saidi@arm.com inSecureState(readMiscRegNoEffect(MISCREG_SCR), 154910461SAndreas.Sandberg@ARM.com readMiscRegNoEffect(MISCREG_CPSR)); 155010461SAndreas.Sandberg@ARM.com if (!secure_lookup) { 155110037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 155210037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 155310037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 155410037SARM gem5 Developers } 155510037SARM gem5 Developers break; 155610037SARM gem5 Developers } 155710037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 155810037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 155910037SARM gem5 Developers break; 156010037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 156110037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 156210037SARM gem5 Developers break; 156310037SARM gem5 Developers case MISCREG_ATS1CPR: 156410037SARM gem5 Developers case MISCREG_ATS1CPW: 156510037SARM gem5 Developers case MISCREG_ATS1CUR: 156610037SARM gem5 Developers case MISCREG_ATS1CUW: 156710037SARM gem5 Developers case MISCREG_ATS12NSOPR: 156810037SARM gem5 Developers case MISCREG_ATS12NSOPW: 156910037SARM gem5 Developers case MISCREG_ATS12NSOUR: 157010037SARM gem5 Developers case MISCREG_ATS12NSOUW: 157110037SARM gem5 Developers case MISCREG_ATS1HR: 157210037SARM gem5 Developers case MISCREG_ATS1HW: 157310037SARM gem5 Developers { 157410037SARM gem5 Developers Request::Flags flags = 0; 157510037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 157610037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 157710037SARM gem5 Developers Fault fault; 157810037SARM gem5 Developers switch(misc_reg) { 157910037SARM gem5 Developers case MISCREG_ATS1CPR: 158010037SARM gem5 Developers flags = TLB::MustBeOne; 158110037SARM gem5 Developers tranType = TLB::S1CTran; 158210037SARM gem5 Developers mode = BaseTLB::Read; 158310037SARM gem5 Developers break; 158410037SARM gem5 Developers case MISCREG_ATS1CPW: 158510037SARM gem5 Developers flags = TLB::MustBeOne; 158610037SARM gem5 Developers tranType = TLB::S1CTran; 158710037SARM gem5 Developers mode = BaseTLB::Write; 15887436Sdam.sunwoo@arm.com break; 158911608Snikos.nikoleris@arm.com case MISCREG_ATS1CUR: 159010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159110037SARM gem5 Developers tranType = TLB::S1CTran; 15927436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 15937436Sdam.sunwoo@arm.com break; 159410037SARM gem5 Developers case MISCREG_ATS1CUW: 159510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159610037SARM gem5 Developers tranType = TLB::S1CTran; 159710037SARM gem5 Developers mode = BaseTLB::Write; 159810037SARM gem5 Developers break; 159910037SARM gem5 Developers case MISCREG_ATS12NSOPR: 160010037SARM gem5 Developers if (!haveSecurity) 160110037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 160210037SARM gem5 Developers flags = TLB::MustBeOne; 160310037SARM gem5 Developers tranType = TLB::S1S2NsTran; 160410037SARM gem5 Developers mode = BaseTLB::Read; 160510037SARM gem5 Developers break; 160610037SARM gem5 Developers case MISCREG_ATS12NSOPW: 160710037SARM gem5 Developers if (!haveSecurity) 160810037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 160910037SARM gem5 Developers flags = TLB::MustBeOne; 161010037SARM gem5 Developers tranType = TLB::S1S2NsTran; 161110037SARM gem5 Developers mode = BaseTLB::Write; 161210037SARM gem5 Developers break; 161310037SARM gem5 Developers case MISCREG_ATS12NSOUR: 161410037SARM gem5 Developers if (!haveSecurity) 161510037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 161610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 161710037SARM gem5 Developers tranType = TLB::S1S2NsTran; 161810037SARM gem5 Developers mode = BaseTLB::Read; 161910037SARM gem5 Developers break; 162010037SARM gem5 Developers case MISCREG_ATS12NSOUW: 162110037SARM gem5 Developers if (!haveSecurity) 162210037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 162310037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 162410037SARM gem5 Developers tranType = TLB::S1S2NsTran; 162510037SARM gem5 Developers mode = BaseTLB::Write; 162610037SARM gem5 Developers break; 162710037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 162810037SARM gem5 Developers flags = TLB::MustBeOne; 162910037SARM gem5 Developers tranType = TLB::HypMode; 163010037SARM gem5 Developers mode = BaseTLB::Read; 163110037SARM gem5 Developers break; 163210037SARM gem5 Developers case MISCREG_ATS1HW: 163310037SARM gem5 Developers flags = TLB::MustBeOne; 163410037SARM gem5 Developers tranType = TLB::HypMode; 163510037SARM gem5 Developers mode = BaseTLB::Write; 163610037SARM gem5 Developers break; 163710037SARM gem5 Developers } 163810037SARM gem5 Developers // If we're in timing mode then doing the translation in 163910037SARM gem5 Developers // functional mode then we're slightly distorting performance 164010037SARM gem5 Developers // results obtained from simulations. The translation should be 164110037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 164210037SARM gem5 Developers // can't be an atomic translation because that causes problems 164310037SARM gem5 Developers // with unexpected atomic snoop requests. 164410037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 164510037SARM gem5 Developers 164610037SARM gem5 Developers auto req = std::make_shared<Request>( 164710037SARM gem5 Developers 0, val, 0, flags, Request::funcMasterId, 164810037SARM gem5 Developers tc->pcState().pc(), tc->contextId()); 164910037SARM gem5 Developers 165010037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional( 165110037SARM gem5 Developers req, tc, mode, tranType); 16527436Sdam.sunwoo@arm.com 165310037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 165410037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 165510037SARM gem5 Developers 165610037SARM gem5 Developers MiscReg newVal; 165710037SARM gem5 Developers if (fault == NoFault) { 165810037SARM gem5 Developers Addr paddr = req->getPaddr(); 165913417Sgiacomo.travaglini@arm.com if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 166013417Sgiacomo.travaglini@arm.com ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 166112749Sgiacomo.travaglini@arm.com newVal = (paddr & mask(39, 12)) | 166212749Sgiacomo.travaglini@arm.com (getDTBPtr(tc)->getAttr()); 166312749Sgiacomo.travaglini@arm.com } else { 166412749Sgiacomo.travaglini@arm.com newVal = (paddr & 0xfffff000) | 166512749Sgiacomo.travaglini@arm.com (getDTBPtr(tc)->getAttr()); 166612406Sgabeblack@google.com } 166712749Sgiacomo.travaglini@arm.com DPRINTF(MiscRegs, 166812749Sgiacomo.travaglini@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 166910037SARM gem5 Developers val, newVal); 167010037SARM gem5 Developers } else { 167110037SARM gem5 Developers ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 167210037SARM gem5 Developers armFault->update(tc); 16737436Sdam.sunwoo@arm.com // Set fault bit and FSR 167412749Sgiacomo.travaglini@arm.com FSR fsr = armFault->getFsr(tc); 167510037SARM gem5 Developers 167610037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 167710037SARM gem5 Developers if (newVal) { 167812406Sgabeblack@google.com // LPAE - rearange fault status 167910037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 168010037SARM gem5 Developers } else { 168112406Sgabeblack@google.com // VMSA - rearange fault status 168210037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 16837436Sdam.sunwoo@arm.com newVal |= ((fsr >> 10) & 0x1) << 5; 16847436Sdam.sunwoo@arm.com newVal |= ((fsr >> 12) & 0x1) << 6; 168510037SARM gem5 Developers } 168610037SARM gem5 Developers newVal |= 0x1; // F bit 168712524Sgiacomo.travaglini@arm.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 168812570Sgiacomo.travaglini@arm.com newVal |= armFault->isStage2() ? 0x200 : 0; 168910037SARM gem5 Developers DPRINTF(MiscRegs, 169010037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 169110037SARM gem5 Developers val, fsr, newVal); 169210037SARM gem5 Developers } 169310037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 169410037SARM gem5 Developers return; 169510037SARM gem5 Developers } 169610037SARM gem5 Developers case MISCREG_TTBCR: 169710037SARM gem5 Developers { 169810037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 169910037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 170010037SARM gem5 Developers TTBCR ttbcrMask = 0; 170110037SARM gem5 Developers TTBCR ttbcrNew = newVal; 170210037SARM gem5 Developers 170310037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 170410037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 170510037SARM gem5 Developers if (haveSecurity) { 170610037SARM gem5 Developers ttbcrMask.pd0 = ones; 170710037SARM gem5 Developers ttbcrMask.pd1 = ones; 17087436Sdam.sunwoo@arm.com } 170910037SARM gem5 Developers ttbcrMask.epd0 = ones; 17107436Sdam.sunwoo@arm.com ttbcrMask.irgn0 = ones; 17117436Sdam.sunwoo@arm.com ttbcrMask.orgn0 = ones; 171210037SARM gem5 Developers ttbcrMask.sh0 = ones; 171310037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 171410037SARM gem5 Developers ttbcrMask.a1 = ones; 171510037SARM gem5 Developers ttbcrMask.epd1 = ones; 171610037SARM gem5 Developers ttbcrMask.irgn1 = ones; 171710037SARM gem5 Developers ttbcrMask.orgn1 = ones; 171810037SARM gem5 Developers ttbcrMask.sh1 = ones; 171910037SARM gem5 Developers if (haveLPAE) 172010037SARM gem5 Developers ttbcrMask.eae = ones; 172110037SARM gem5 Developers 172210037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 172310037SARM gem5 Developers newVal = newVal & ttbcrMask; 172410037SARM gem5 Developers } else { 172510037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 172610037SARM gem5 Developers } 172710037SARM gem5 Developers // Invalidate TLB MiscReg 172810037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 172910037SARM gem5 Developers getDTBPtr(tc)->invalidateMiscReg(); 173010037SARM gem5 Developers break; 173110037SARM gem5 Developers } 173210037SARM gem5 Developers case MISCREG_TTBR0: 173310037SARM gem5 Developers case MISCREG_TTBR1: 173410037SARM gem5 Developers { 173510037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 173610037SARM gem5 Developers if (haveLPAE) { 173710037SARM gem5 Developers if (ttbcr.eae) { 173810037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 173910037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 174010037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 174110037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 174210037SARM gem5 Developers } 174312666Sgiacomo.travaglini@arm.com } 174412666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 174512666Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 174612666Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 174710037SARM gem5 Developers break; 174810037SARM gem5 Developers } 174910037SARM gem5 Developers case MISCREG_SCTLR_EL1: 175010037SARM gem5 Developers case MISCREG_CONTEXTIDR: 175110037SARM gem5 Developers case MISCREG_PRRR: 175210037SARM gem5 Developers case MISCREG_NMRR: 175310037SARM gem5 Developers case MISCREG_MAIR0: 175410037SARM gem5 Developers case MISCREG_MAIR1: 175510037SARM gem5 Developers case MISCREG_DACR: 175610037SARM gem5 Developers case MISCREG_VTTBR: 175710037SARM gem5 Developers case MISCREG_SCR_EL3: 175810037SARM gem5 Developers case MISCREG_HCR_EL2: 175910037SARM gem5 Developers case MISCREG_TCR_EL1: 176012666Sgiacomo.travaglini@arm.com case MISCREG_TCR_EL2: 176112406Sgabeblack@google.com case MISCREG_TCR_EL3: 176212406Sgabeblack@google.com case MISCREG_SCTLR_EL2: 176312666Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL3: 176410508SAli.Saidi@ARM.com case MISCREG_HSCTLR: 176512666Sgiacomo.travaglini@arm.com case MISCREG_TTBR0_EL1: 17667749SAli.Saidi@ARM.com case MISCREG_TTBR1_EL1: 17677749SAli.Saidi@ARM.com case MISCREG_TTBR0_EL2: 17687749SAli.Saidi@ARM.com case MISCREG_TTBR1_EL2: 176910037SARM gem5 Developers case MISCREG_TTBR0_EL3: 177010037SARM gem5 Developers getITBPtr(tc)->invalidateMiscReg(); 17717749SAli.Saidi@ARM.com getDTBPtr(tc)->invalidateMiscReg(); 177210037SARM gem5 Developers break; 177310037SARM gem5 Developers case MISCREG_NZCV: 177411575SDylan.Johnson@ARM.com { 177510037SARM gem5 Developers CPSR cpsr = val; 177610037SARM gem5 Developers 177710037SARM gem5 Developers tc->setCCReg(CCREG_NZ, cpsr.nz); 177810508SAli.Saidi@ARM.com tc->setCCReg(CCREG_C, cpsr.c); 177910508SAli.Saidi@ARM.com tc->setCCReg(CCREG_V, cpsr.v); 178011573SDylan.Johnson@ARM.com } 178110037SARM gem5 Developers break; 178210037SARM gem5 Developers case MISCREG_DAIF: 178310037SARM gem5 Developers { 178412675Sgiacomo.travaglini@arm.com CPSR cpsr = miscRegs[MISCREG_CPSR]; 178510037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 178612406Sgabeblack@google.com newVal = cpsr; 178712406Sgabeblack@google.com misc_reg = MISCREG_CPSR; 17887749SAli.Saidi@ARM.com } 178910037SARM gem5 Developers break; 179010037SARM gem5 Developers case MISCREG_SP_EL0: 179110037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 179210037SARM gem5 Developers break; 179310338SCurtis.Dunham@arm.com case MISCREG_SP_EL1: 179410338SCurtis.Dunham@arm.com tc->setIntReg(INTREG_SP1, newVal); 179510338SCurtis.Dunham@arm.com break; 179610037SARM gem5 Developers case MISCREG_SP_EL2: 179710037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 179810037SARM gem5 Developers break; 179910037SARM gem5 Developers case MISCREG_SPSEL: 180010037SARM gem5 Developers { 180110037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 180210037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 180310037SARM gem5 Developers newVal = cpsr; 180410037SARM gem5 Developers misc_reg = MISCREG_CPSR; 180510037SARM gem5 Developers } 180610037SARM gem5 Developers break; 180710037SARM gem5 Developers case MISCREG_CURRENTEL: 180810037SARM gem5 Developers { 180910037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 181010037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 181110037SARM gem5 Developers newVal = cpsr; 181210037SARM gem5 Developers misc_reg = MISCREG_CPSR; 181310037SARM gem5 Developers } 181410037SARM gem5 Developers break; 181510037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 181610037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 181710037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 181810037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 181910037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 182010037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 182110037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 182210037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 182310037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 182410037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 182510037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 182610037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 182710037SARM gem5 Developers { 182810037SARM gem5 Developers RequestPtr req = std::make_shared<Request>(); 182910037SARM gem5 Developers Request::Flags flags = 0; 183010037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 183110037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 183210037SARM gem5 Developers Fault fault; 183310037SARM gem5 Developers switch(misc_reg) { 183410037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 183510037SARM gem5 Developers flags = TLB::MustBeOne; 183610037SARM gem5 Developers tranType = TLB::S1E1Tran; 183710037SARM gem5 Developers mode = BaseTLB::Read; 183810037SARM gem5 Developers break; 183910037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 184010037SARM gem5 Developers flags = TLB::MustBeOne; 184110037SARM gem5 Developers tranType = TLB::S1E1Tran; 184210037SARM gem5 Developers mode = BaseTLB::Write; 184310037SARM gem5 Developers break; 184412749Sgiacomo.travaglini@arm.com case MISCREG_AT_S1E0R_Xt: 184511608Snikos.nikoleris@arm.com flags = TLB::MustBeOne | TLB::UserMode; 184610037SARM gem5 Developers tranType = TLB::S1E0Tran; 184710037SARM gem5 Developers mode = BaseTLB::Read; 184810037SARM gem5 Developers break; 184910037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 185010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 185110037SARM gem5 Developers tranType = TLB::S1E0Tran; 185211577SDylan.Johnson@ARM.com mode = BaseTLB::Write; 185310037SARM gem5 Developers break; 185410037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 185510037SARM gem5 Developers flags = TLB::MustBeOne; 185610037SARM gem5 Developers tranType = TLB::S1E2Tran; 185711577SDylan.Johnson@ARM.com mode = BaseTLB::Read; 185810037SARM gem5 Developers break; 185910037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 186010037SARM gem5 Developers flags = TLB::MustBeOne; 186110037SARM gem5 Developers tranType = TLB::S1E2Tran; 186211577SDylan.Johnson@ARM.com mode = BaseTLB::Write; 186310037SARM gem5 Developers break; 186410037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 186510037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 186610037SARM gem5 Developers tranType = TLB::S12E0Tran; 186711577SDylan.Johnson@ARM.com mode = BaseTLB::Read; 186810037SARM gem5 Developers break; 186910037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 187010037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 187110037SARM gem5 Developers tranType = TLB::S12E0Tran; 187211577SDylan.Johnson@ARM.com mode = BaseTLB::Write; 187310037SARM gem5 Developers break; 187410037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 187510037SARM gem5 Developers flags = TLB::MustBeOne; 187610037SARM gem5 Developers tranType = TLB::S12E1Tran; 187711577SDylan.Johnson@ARM.com mode = BaseTLB::Read; 187810037SARM gem5 Developers break; 187910037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 188010037SARM gem5 Developers flags = TLB::MustBeOne; 188110037SARM gem5 Developers tranType = TLB::S12E1Tran; 188211577SDylan.Johnson@ARM.com mode = BaseTLB::Write; 188310037SARM gem5 Developers break; 188410037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 188510037SARM gem5 Developers flags = TLB::MustBeOne; 188610037SARM gem5 Developers tranType = TLB::S1E3Tran; 188711577SDylan.Johnson@ARM.com mode = BaseTLB::Read; 188810037SARM gem5 Developers break; 188910037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 189010037SARM gem5 Developers flags = TLB::MustBeOne; 189110037SARM gem5 Developers tranType = TLB::S1E3Tran; 189211577SDylan.Johnson@ARM.com mode = BaseTLB::Write; 189310037SARM gem5 Developers break; 189410037SARM gem5 Developers } 189510037SARM gem5 Developers // If we're in timing mode then doing the translation in 189610037SARM gem5 Developers // functional mode then we're slightly distorting performance 189711577SDylan.Johnson@ARM.com // results obtained from simulations. The translation should be 189810037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 189910037SARM gem5 Developers // can't be an atomic translation because that causes problems 190010037SARM gem5 Developers // with unexpected atomic snoop requests. 190110037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 190211577SDylan.Johnson@ARM.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 190310037SARM gem5 Developers tc->pcState().pc()); 190410037SARM gem5 Developers req->setContext(tc->contextId()); 190510037SARM gem5 Developers fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 190610037SARM gem5 Developers tranType); 190711577SDylan.Johnson@ARM.com 190810037SARM gem5 Developers MiscReg newVal; 190910037SARM gem5 Developers if (fault == NoFault) { 191010037SARM gem5 Developers Addr paddr = req->getPaddr(); 191110037SARM gem5 Developers uint64_t attr = getDTBPtr(tc)->getAttr(); 191210037SARM gem5 Developers uint64_t attr1 = attr >> 56; 191310037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 191410037SARM gem5 Developers attr |= 0x100; 191510037SARM gem5 Developers attr &= ~ uint64_t(0x80); 191610037SARM gem5 Developers } 191713417Sgiacomo.travaglini@arm.com newVal = (paddr & mask(47, 12)) | attr; 191813417Sgiacomo.travaglini@arm.com DPRINTF(MiscRegs, 191913417Sgiacomo.travaglini@arm.com "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 192011560Sandreas.sandberg@arm.com val, newVal); 192110037SARM gem5 Developers } else { 192211435Smitch.hayenga@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 192312406Sgabeblack@google.com armFault->update(tc); 192412406Sgabeblack@google.com // Set fault bit and FSR 192510037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 192610037SARM gem5 Developers 192710037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 192810037SARM gem5 Developers if (cpsr.width) { // AArch32 192912406Sgabeblack@google.com newVal = ((fsr >> 9) & 1) << 11; 193010037SARM gem5 Developers // rearrange fault status 193110037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 193210037SARM gem5 Developers newVal |= 0x1; // F bit 193310037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 193410037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 193510037SARM gem5 Developers } else { // AArch64 193610037SARM gem5 Developers newVal = 1; // F bit 193710037SARM gem5 Developers newVal |= fsr << 1; // FST 193810037SARM gem5 Developers // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 193910037SARM gem5 Developers newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 194012524Sgiacomo.travaglini@arm.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 194112570Sgiacomo.travaglini@arm.com newVal |= 1 << 11; // RES1 194210037SARM gem5 Developers } 194310037SARM gem5 Developers DPRINTF(MiscRegs, 194410037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 194511577SDylan.Johnson@ARM.com val, fsr, newVal); 194611577SDylan.Johnson@ARM.com } 194711577SDylan.Johnson@ARM.com setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 194811577SDylan.Johnson@ARM.com return; 194911577SDylan.Johnson@ARM.com } 195011577SDylan.Johnson@ARM.com case MISCREG_SPSR_EL3: 195111577SDylan.Johnson@ARM.com case MISCREG_SPSR_EL2: 195211577SDylan.Johnson@ARM.com case MISCREG_SPSR_EL1: 195311577SDylan.Johnson@ARM.com // Force bits 23:21 to 0 195411577SDylan.Johnson@ARM.com newVal = val & ~(0x7 << 21); 195511577SDylan.Johnson@ARM.com break; 195611577SDylan.Johnson@ARM.com case MISCREG_L2CTLR: 195711577SDylan.Johnson@ARM.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 195811577SDylan.Johnson@ARM.com miscRegName[misc_reg], uint32_t(val)); 195911577SDylan.Johnson@ARM.com break; 196011577SDylan.Johnson@ARM.com 196110037SARM gem5 Developers // Generic Timer registers 196210037SARM gem5 Developers case MISCREG_CNTHV_CTL_EL2: 196310037SARM gem5 Developers case MISCREG_CNTHV_CVAL_EL2: 196410037SARM gem5 Developers case MISCREG_CNTHV_TVAL_EL2: 196510037SARM gem5 Developers case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 196610037SARM gem5 Developers case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 196710037SARM gem5 Developers case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 196810037SARM gem5 Developers case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 196910037SARM gem5 Developers getGenericTimer(tc).setMiscReg(misc_reg, newVal); 197010037SARM gem5 Developers break; 197110037SARM gem5 Developers } 197210037SARM gem5 Developers } 197310037SARM gem5 Developers setMiscRegNoEffect(misc_reg, newVal); 19748549Sdaniel.johnson@arm.com} 19758549Sdaniel.johnson@arm.com 19768549Sdaniel.johnson@arm.comBaseISADevice & 197710037SARM gem5 DevelopersISA::getGenericTimer(ThreadContext *tc) 197810037SARM gem5 Developers{ 197910037SARM gem5 Developers // We only need to create an ISA interface the first time we try 198012816Sgiacomo.travaglini@arm.com // to access the timer. 198112816Sgiacomo.travaglini@arm.com if (timer) 198212816Sgiacomo.travaglini@arm.com return *timer.get(); 198310844Sandreas.sandberg@arm.com 198410844Sandreas.sandberg@arm.com assert(system); 198510844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 198610844Sandreas.sandberg@arm.com if (!generic_timer) { 198710844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 198810037SARM gem5 Developers "been configured to use a generic timer.\n"); 198913531Sjairo.balart@metempsy.com } 199013531Sjairo.balart@metempsy.com 199113531Sjairo.balart@metempsy.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 199213531Sjairo.balart@metempsy.com timer->setThreadContext(tc); 199313531Sjairo.balart@metempsy.com 19947405SAli.Saidi@ARM.com return *timer.get(); 19957405SAli.Saidi@ARM.com} 19967405SAli.Saidi@ARM.com 19977405SAli.Saidi@ARM.com} 19987405SAli.Saidi@ARM.com 199910844Sandreas.sandberg@arm.comArmISA::ISA * 200010844Sandreas.sandberg@arm.comArmISAParams::create() 200110037SARM gem5 Developers{ 200210844Sandreas.sandberg@arm.com return new ArmISA::ISA(this); 200310844Sandreas.sandberg@arm.com} 200410844Sandreas.sandberg@arm.com