isa.cc revision 13114
17405SAli.Saidi@ARM.com/* 212667Schuan.zhu@arm.com * Copyright (c) 2010-2018 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh" 439050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 4412406Sgabeblack@google.com#include "arch/arm/tlb.hh" 4512605Sgiacomo.travaglini@arm.com#include "arch/arm/tlbi_op.hh" 4611793Sbrandon.potter@amd.com#include "cpu/base.hh" 478887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 488232Snate@binkert.org#include "debug/Arm.hh" 498232Snate@binkert.org#include "debug/MiscRegs.hh" 5010844Sandreas.sandberg@arm.com#include "dev/arm/generic_timer.hh" 519384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 527678Sgblack@eecs.umich.edu#include "sim/faults.hh" 538059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 548284SAli.Saidi@ARM.com#include "sim/system.hh" 557405SAli.Saidi@ARM.com 567405SAli.Saidi@ARM.comnamespace ArmISA 577405SAli.Saidi@ARM.com{ 587405SAli.Saidi@ARM.com 599384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 6010461SAndreas.Sandberg@ARM.com : SimObject(p), 6110461SAndreas.Sandberg@ARM.com system(NULL), 6211165SRekai.GonzalezAlberquilla@arm.com _decoderFlavour(p->decoderFlavour), 6312109SRekai.GonzalezAlberquilla@arm.com _vecRegRenameMode(p->vecRegRenameMode), 6412714Sgiacomo.travaglini@arm.com pmu(p->pmu), 6512714Sgiacomo.travaglini@arm.com impdefAsNop(p->impdef_nop) 669384SAndreas.Sandberg@arm.com{ 6711770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_RST] = 0; 6810037SARM gem5 Developers 6910461SAndreas.Sandberg@ARM.com // Hook up a dummy device if we haven't been configured with a 7010461SAndreas.Sandberg@ARM.com // real PMU. By using a dummy device, we don't need to check that 7110461SAndreas.Sandberg@ARM.com // the PMU exist every time we try to access a PMU register. 7210461SAndreas.Sandberg@ARM.com if (!pmu) 7310461SAndreas.Sandberg@ARM.com pmu = &dummyDevice; 7410461SAndreas.Sandberg@ARM.com 7510609Sandreas.sandberg@arm.com // Give all ISA devices a pointer to this ISA 7610609Sandreas.sandberg@arm.com pmu->setISA(this); 7710609Sandreas.sandberg@arm.com 7810037SARM gem5 Developers system = dynamic_cast<ArmSystem *>(p->system); 7910037SARM gem5 Developers 8010037SARM gem5 Developers // Cache system-level properties 8110037SARM gem5 Developers if (FullSystem && system) { 8211771SCurtis.Dunham@arm.com highestELIs64 = system->highestELIs64(); 8310037SARM gem5 Developers haveSecurity = system->haveSecurity(); 8410037SARM gem5 Developers haveLPAE = system->haveLPAE(); 8510037SARM gem5 Developers haveVirtualization = system->haveVirtualization(); 8610037SARM gem5 Developers haveLargeAsid64 = system->haveLargeAsid64(); 8713114Sgiacomo.travaglini@arm.com physAddrRange = system->physAddrRange(); 8810037SARM gem5 Developers } else { 8911771SCurtis.Dunham@arm.com highestELIs64 = true; // ArmSystem::highestELIs64 does the same 9010037SARM gem5 Developers haveSecurity = haveLPAE = haveVirtualization = false; 9110037SARM gem5 Developers haveLargeAsid64 = false; 9213114Sgiacomo.travaglini@arm.com physAddrRange = 32; // dummy value 9310037SARM gem5 Developers } 9410037SARM gem5 Developers 9512477SCurtis.Dunham@arm.com initializeMiscRegMetadata(); 9610037SARM gem5 Developers preUnflattenMiscReg(); 9710037SARM gem5 Developers 989384SAndreas.Sandberg@arm.com clear(); 999384SAndreas.Sandberg@arm.com} 1009384SAndreas.Sandberg@arm.com 10112479SCurtis.Dunham@arm.comstd::vector<struct ISA::MiscRegLUTEntry> ISA::lookUpMiscReg(NUM_MISCREGS); 10212479SCurtis.Dunham@arm.com 1039384SAndreas.Sandberg@arm.comconst ArmISAParams * 1049384SAndreas.Sandberg@arm.comISA::params() const 1059384SAndreas.Sandberg@arm.com{ 1069384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 1079384SAndreas.Sandberg@arm.com} 1089384SAndreas.Sandberg@arm.com 1097427Sgblack@eecs.umich.eduvoid 1107427Sgblack@eecs.umich.eduISA::clear() 1117427Sgblack@eecs.umich.edu{ 1129385SAndreas.Sandberg@arm.com const Params *p(params()); 1139385SAndreas.Sandberg@arm.com 1147427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 1157427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 11610037SARM gem5 Developers 11713114Sgiacomo.travaglini@arm.com initID32(p); 11810037SARM gem5 Developers 11913114Sgiacomo.travaglini@arm.com // We always initialize AArch64 ID registers even 12013114Sgiacomo.travaglini@arm.com // if we are in AArch32. This is done since if we 12113114Sgiacomo.travaglini@arm.com // are in SE mode we don't know if our ArmProcess is 12213114Sgiacomo.travaglini@arm.com // AArch32 or AArch64 12313114Sgiacomo.travaglini@arm.com initID64(p); 12412690Sgiacomo.travaglini@arm.com 12510037SARM gem5 Developers if (FullSystem && system->highestELIs64()) { 12610037SARM gem5 Developers // Initialize AArch64 state 12710037SARM gem5 Developers clear64(p); 12810037SARM gem5 Developers return; 12910037SARM gem5 Developers } 13010037SARM gem5 Developers 13110037SARM gem5 Developers // Initialize AArch32 state... 13210037SARM gem5 Developers 1337427Sgblack@eecs.umich.edu CPSR cpsr = 0; 1347427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 1357427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 1367427Sgblack@eecs.umich.edu updateRegMap(cpsr); 1377427Sgblack@eecs.umich.edu 1387427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 13910037SARM gem5 Developers sctlr.te = (bool) sctlr_rst.te; 14010037SARM gem5 Developers sctlr.nmfi = (bool) sctlr_rst.nmfi; 14110037SARM gem5 Developers sctlr.v = (bool) sctlr_rst.v; 14210037SARM gem5 Developers sctlr.u = 1; 1437427Sgblack@eecs.umich.edu sctlr.xp = 1; 1447427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 1457427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 14610037SARM gem5 Developers sctlr.rao4 = 0xf; // SCTLR[6:3] 14710204SAli.Saidi@ARM.com sctlr.uci = 1; 14810204SAli.Saidi@ARM.com sctlr.dze = 1; 14910037SARM gem5 Developers miscRegs[MISCREG_SCTLR_NS] = sctlr; 1507427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 15110037SARM gem5 Developers miscRegs[MISCREG_HCPTR] = 0; 1527427Sgblack@eecs.umich.edu 15310037SARM gem5 Developers // Start with an event in the mailbox 1547427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 1557427Sgblack@eecs.umich.edu 15610037SARM gem5 Developers // Separate Instruction and Data TLBs 1577427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 1587427Sgblack@eecs.umich.edu 1597427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1607427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1617427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1627427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1637427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1647427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1657427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1667427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1677427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1687427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1697427Sgblack@eecs.umich.edu 1707427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1717427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1727427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1737427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1747427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1757427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1767427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1777427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1787427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1797427Sgblack@eecs.umich.edu 1807436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1817436Sdam.sunwoo@arm.com 18210037SARM gem5 Developers // @todo: PRRR and NMRR in secure state? 18310037SARM gem5 Developers miscRegs[MISCREG_PRRR_NS] = 1847436Sdam.sunwoo@arm.com (1 << 19) | // 19 1857436Sdam.sunwoo@arm.com (0 << 18) | // 18 1867436Sdam.sunwoo@arm.com (0 << 17) | // 17 1877436Sdam.sunwoo@arm.com (1 << 16) | // 16 1887436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1897436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1907436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1917436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1927436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1937436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1947436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1957436Sdam.sunwoo@arm.com 0; // 1:0 19610037SARM gem5 Developers miscRegs[MISCREG_NMRR_NS] = 1977436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1987436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1997436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 2007436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 2017436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 2027436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 2037436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 2047436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 2057436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 2067436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 2077436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 2087436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 2097436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 2107436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 2117436Sdam.sunwoo@arm.com 0; // 1:0 2127436Sdam.sunwoo@arm.com 2137644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 2148147SAli.Saidi@ARM.com 2159385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 2169385SAndreas.Sandberg@arm.com 21710037SARM gem5 Developers if (haveLPAE) { 21810037SARM gem5 Developers TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS]; 21910037SARM gem5 Developers ttbcr.eae = 0; 22010037SARM gem5 Developers miscRegs[MISCREG_TTBCR_NS] = ttbcr; 22110037SARM gem5 Developers // Enforce consistency with system-level settings 22210037SARM gem5 Developers miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5; 22310037SARM gem5 Developers } 22410037SARM gem5 Developers 22510037SARM gem5 Developers if (haveSecurity) { 22610037SARM gem5 Developers miscRegs[MISCREG_SCTLR_S] = sctlr; 22710037SARM gem5 Developers miscRegs[MISCREG_SCR] = 0; 22810037SARM gem5 Developers miscRegs[MISCREG_VBAR_S] = 0; 22910037SARM gem5 Developers } else { 23010037SARM gem5 Developers // we're always non-secure 23110037SARM gem5 Developers miscRegs[MISCREG_SCR] = 1; 23210037SARM gem5 Developers } 2338147SAli.Saidi@ARM.com 2347427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 2357427Sgblack@eecs.umich.edu} 2367427Sgblack@eecs.umich.edu 23710037SARM gem5 Developersvoid 23810037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p) 23910037SARM gem5 Developers{ 24010037SARM gem5 Developers CPSR cpsr = 0; 24110037SARM gem5 Developers Addr rvbar = system->resetAddr64(); 24210037SARM gem5 Developers switch (system->highestEL()) { 24310037SARM gem5 Developers // Set initial EL to highest implemented EL using associated stack 24410037SARM gem5 Developers // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset 24510037SARM gem5 Developers // value 24610037SARM gem5 Developers case EL3: 24710037SARM gem5 Developers cpsr.mode = MODE_EL3H; 24810037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL3] = rvbar; 24910037SARM gem5 Developers break; 25010037SARM gem5 Developers case EL2: 25110037SARM gem5 Developers cpsr.mode = MODE_EL2H; 25210037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL2] = rvbar; 25310037SARM gem5 Developers break; 25410037SARM gem5 Developers case EL1: 25510037SARM gem5 Developers cpsr.mode = MODE_EL1H; 25610037SARM gem5 Developers miscRegs[MISCREG_RVBAR_EL1] = rvbar; 25710037SARM gem5 Developers break; 25810037SARM gem5 Developers default: 25910037SARM gem5 Developers panic("Invalid highest implemented exception level"); 26010037SARM gem5 Developers break; 26110037SARM gem5 Developers } 26210037SARM gem5 Developers 26310037SARM gem5 Developers // Initialize rest of CPSR 26410037SARM gem5 Developers cpsr.daif = 0xf; // Mask all interrupts 26510037SARM gem5 Developers cpsr.ss = 0; 26610037SARM gem5 Developers cpsr.il = 0; 26710037SARM gem5 Developers miscRegs[MISCREG_CPSR] = cpsr; 26810037SARM gem5 Developers updateRegMap(cpsr); 26910037SARM gem5 Developers 27010037SARM gem5 Developers // Initialize other control registers 27110037SARM gem5 Developers miscRegs[MISCREG_MPIDR_EL1] = 0x80000000; 27210037SARM gem5 Developers if (haveSecurity) { 27311770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_EL3] = 0x30c50830; 27410037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 0x00000030; // RES1 fields 27511574SCurtis.Dunham@arm.com } else if (haveVirtualization) { 27611770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL2 (by mapping) 27711770SCurtis.Dunham@arm.com miscRegs[MISCREG_HSCTLR] = 0x30c50830; 27810037SARM gem5 Developers } else { 27911770SCurtis.Dunham@arm.com // also MISCREG_SCTLR_EL1 (by mapping) 28011770SCurtis.Dunham@arm.com miscRegs[MISCREG_SCTLR_NS] = 0x30d00800 | 0x00050030; // RES1 | init 28110037SARM gem5 Developers // Always non-secure 28210037SARM gem5 Developers miscRegs[MISCREG_SCR_EL3] = 1; 28310037SARM gem5 Developers } 28413114Sgiacomo.travaglini@arm.com} 28510037SARM gem5 Developers 28613114Sgiacomo.travaglini@arm.comvoid 28713114Sgiacomo.travaglini@arm.comISA::initID32(const ArmISAParams *p) 28813114Sgiacomo.travaglini@arm.com{ 28913114Sgiacomo.travaglini@arm.com // Initialize configurable default values 29013114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR] = p->midr; 29113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_MIDR_EL1] = p->midr; 29213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_VPIDR] = p->midr; 29313114Sgiacomo.travaglini@arm.com 29413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 29513114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 29613114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 29713114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 29813114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 29913114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 30013114Sgiacomo.travaglini@arm.com 30113114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 30213114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 30313114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 30413114Sgiacomo.travaglini@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 30513114Sgiacomo.travaglini@arm.com} 30613114Sgiacomo.travaglini@arm.com 30713114Sgiacomo.travaglini@arm.comvoid 30813114Sgiacomo.travaglini@arm.comISA::initID64(const ArmISAParams *p) 30913114Sgiacomo.travaglini@arm.com{ 31010037SARM gem5 Developers // Initialize configurable id registers 31110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1; 31210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1; 31310461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_AA64DFR0_EL1] = 31410461SAndreas.Sandberg@ARM.com (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) | 31510461SAndreas.Sandberg@ARM.com (p->pmu ? 0x0000000000000100ULL : 0); // Enable PMUv3 31610461SAndreas.Sandberg@ARM.com 31710037SARM gem5 Developers miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1; 31810037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1; 31910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1; 32010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1; 32110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1; 32210037SARM gem5 Developers 32310461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0_EL1] = 32410461SAndreas.Sandberg@ARM.com (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3 32510461SAndreas.Sandberg@ARM.com 32610461SAndreas.Sandberg@ARM.com miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1]; 32710461SAndreas.Sandberg@ARM.com 32810037SARM gem5 Developers // Enforce consistency with system-level settings... 32910037SARM gem5 Developers 33010037SARM gem5 Developers // EL3 33110037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 33210037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12, 33311574SCurtis.Dunham@arm.com haveSecurity ? 0x2 : 0x0); 33410037SARM gem5 Developers // EL2 33510037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits( 33610037SARM gem5 Developers miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8, 33711574SCurtis.Dunham@arm.com haveVirtualization ? 0x2 : 0x0); 33810037SARM gem5 Developers // Large ASID support 33910037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 34010037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4, 34110037SARM gem5 Developers haveLargeAsid64 ? 0x2 : 0x0); 34210037SARM gem5 Developers // Physical address size 34310037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits( 34410037SARM gem5 Developers miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0, 34513114Sgiacomo.travaglini@arm.com encodePhysAddrRange64(physAddrRange)); 34610037SARM gem5 Developers} 34710037SARM gem5 Developers 34812972Sandreas.sandberg@arm.comvoid 34912972Sandreas.sandberg@arm.comISA::startup(ThreadContext *tc) 35012972Sandreas.sandberg@arm.com{ 35112972Sandreas.sandberg@arm.com pmu->setThreadContext(tc); 35212972Sandreas.sandberg@arm.com 35312972Sandreas.sandberg@arm.com} 35412972Sandreas.sandberg@arm.com 35512972Sandreas.sandberg@arm.com 3567405SAli.Saidi@ARM.comMiscReg 35710035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 3587405SAli.Saidi@ARM.com{ 3597405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 3607614Sminkyu.jeong@arm.com 36112478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 36212478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 36312478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 36412478SCurtis.Dunham@arm.com // NB!: apply architectural masks according to desired register, 36512478SCurtis.Dunham@arm.com // despite possibly getting value from different (mapped) register. 36612478SCurtis.Dunham@arm.com auto val = !upper ? miscRegs[lower] : ((miscRegs[lower] & mask(32)) 36712478SCurtis.Dunham@arm.com |(miscRegs[upper] << 32)); 36812478SCurtis.Dunham@arm.com if (val & reg.res0()) { 36912478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with set res0 bits: %#x\n", 37012478SCurtis.Dunham@arm.com miscRegName[misc_reg], val & reg.res0()); 37112478SCurtis.Dunham@arm.com } 37212478SCurtis.Dunham@arm.com if ((val & reg.res1()) != reg.res1()) { 37312478SCurtis.Dunham@arm.com DPRINTF(MiscRegs, "Reading MiscReg %s with clear res1 bits: %#x\n", 37412478SCurtis.Dunham@arm.com miscRegName[misc_reg], (val & reg.res1()) ^ reg.res1()); 37512478SCurtis.Dunham@arm.com } 37612478SCurtis.Dunham@arm.com return (val & ~reg.raz()) | reg.rao(); // enforce raz/rao 3777405SAli.Saidi@ARM.com} 3787405SAli.Saidi@ARM.com 3797405SAli.Saidi@ARM.com 3807405SAli.Saidi@ARM.comMiscReg 3817405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 3827405SAli.Saidi@ARM.com{ 38310037SARM gem5 Developers CPSR cpsr = 0; 38410037SARM gem5 Developers PCState pc = 0; 38510037SARM gem5 Developers SCR scr = 0; 3869050Schander.sudanthi@arm.com 3877405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 38810037SARM gem5 Developers cpsr = miscRegs[misc_reg]; 38910037SARM gem5 Developers pc = tc->pcState(); 3907720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 3917720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 3927405SAli.Saidi@ARM.com return cpsr; 3937405SAli.Saidi@ARM.com } 3947757SAli.Saidi@ARM.com 39510037SARM gem5 Developers#ifndef NDEBUG 39610037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 39710037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 39810037SARM gem5 Developers warn("Unimplemented system register %s read.\n", 39910037SARM gem5 Developers miscRegName[misc_reg]); 40010037SARM gem5 Developers else 40110037SARM gem5 Developers panic("Unimplemented system register %s read.\n", 40210037SARM gem5 Developers miscRegName[misc_reg]); 40310037SARM gem5 Developers } 40410037SARM gem5 Developers#endif 40510037SARM gem5 Developers 40610037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 40710037SARM gem5 Developers case MISCREG_HCR: 40810037SARM gem5 Developers { 40910037SARM gem5 Developers if (!haveVirtualization) 41010037SARM gem5 Developers return 0; 41110037SARM gem5 Developers else 41210037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HCR); 41310037SARM gem5 Developers } 41410037SARM gem5 Developers case MISCREG_CPACR: 41510037SARM gem5 Developers { 41610037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 41710037SARM gem5 Developers CPACR cpacrMask = 0; 41810037SARM gem5 Developers // Only cp10, cp11, and ase are implemented, nothing else should 41910037SARM gem5 Developers // be readable? (straight copy from the write code) 42010037SARM gem5 Developers cpacrMask.cp10 = ones; 42110037SARM gem5 Developers cpacrMask.cp11 = ones; 42210037SARM gem5 Developers cpacrMask.asedis = ones; 42310037SARM gem5 Developers 42410037SARM gem5 Developers // Security Extensions may limit the readability of CPACR 42510037SARM gem5 Developers if (haveSecurity) { 42610037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 42710037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 42812667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 42910037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 43010037SARM gem5 Developers // NB: Skipping the full loop, here 43110037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 43210037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 43310037SARM gem5 Developers } 43410037SARM gem5 Developers } 43510037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(MISCREG_CPACR); 43610037SARM gem5 Developers val &= cpacrMask; 43710037SARM gem5 Developers DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n", 43810037SARM gem5 Developers miscRegName[misc_reg], val); 43910037SARM gem5 Developers return val; 44010037SARM gem5 Developers } 4418284SAli.Saidi@ARM.com case MISCREG_MPIDR: 44210037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 44310037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 44410037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 44510037SARM gem5 Developers return getMPIDR(system, tc); 4469050Schander.sudanthi@arm.com } else { 44710037SARM gem5 Developers return readMiscReg(MISCREG_VMPIDR, tc); 44810037SARM gem5 Developers } 44910037SARM gem5 Developers break; 45010037SARM gem5 Developers case MISCREG_MPIDR_EL1: 45110037SARM gem5 Developers // @todo in the absence of v8 virtualization support just return MPIDR_EL1 45210037SARM gem5 Developers return getMPIDR(system, tc) & 0xffffffff; 45310037SARM gem5 Developers case MISCREG_VMPIDR: 45410037SARM gem5 Developers // top bit defined as RES1 45510037SARM gem5 Developers return readMiscRegNoEffect(misc_reg) | 0x80000000; 45610037SARM gem5 Developers case MISCREG_ID_AFR0: // not implemented, so alias MIDR 45710037SARM gem5 Developers case MISCREG_REVIDR: // not implemented, so alias MIDR 45810037SARM gem5 Developers case MISCREG_MIDR: 45910037SARM gem5 Developers cpsr = readMiscRegNoEffect(MISCREG_CPSR); 46010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 46110037SARM gem5 Developers if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) { 46210037SARM gem5 Developers return readMiscRegNoEffect(misc_reg); 46310037SARM gem5 Developers } else { 46410037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_VPIDR); 4659050Schander.sudanthi@arm.com } 4668284SAli.Saidi@ARM.com break; 46710037SARM gem5 Developers case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI 46810037SARM gem5 Developers case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI 46910037SARM gem5 Developers case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI 47010037SARM gem5 Developers case MISCREG_AIDR: // AUX ID set to 0 47110037SARM gem5 Developers case MISCREG_TCMTR: // No TCM's 47210037SARM gem5 Developers return 0; 47310037SARM gem5 Developers 4747405SAli.Saidi@ARM.com case MISCREG_CLIDR: 4757731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 4768468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 4778468Swade.walker@arm.com "ARM implementations.\n"); 4788468Swade.walker@arm.com return 0x00200000; 4797405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 4807731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 4817405SAli.Saidi@ARM.com "always reads as 0.\n"); 4827405SAli.Saidi@ARM.com break; 48311809Sbaz21@cam.ac.uk case MISCREG_CTR: // AArch32, ARMv7, top bit set 48411809Sbaz21@cam.ac.uk case MISCREG_CTR_EL0: // AArch64 4859130Satgutier@umich.edu { 4869130Satgutier@umich.edu //all caches have the same line size in gem5 4879130Satgutier@umich.edu //4 byte words in ARM 4889130Satgutier@umich.edu unsigned lineSizeWords = 4899814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 4909130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 4919130Satgutier@umich.edu 4929130Satgutier@umich.edu while (lineSizeWords >>= 1) { 4939130Satgutier@umich.edu ++log2LineSizeWords; 4949130Satgutier@umich.edu } 4959130Satgutier@umich.edu 4969130Satgutier@umich.edu CTR ctr = 0; 4979130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 4989130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 4999130Satgutier@umich.edu //b11 - gem5 uses pipt 5009130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 5019130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 5029130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 5039130Satgutier@umich.edu //log2 of max reservation size (words) 5049130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 5059130Satgutier@umich.edu //log2 of max writeback size (words) 5069130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 5079130Satgutier@umich.edu //b100 - gem5 format is ARMv7 5089130Satgutier@umich.edu ctr.format = 0x4; 5099130Satgutier@umich.edu 5109130Satgutier@umich.edu return ctr; 5119130Satgutier@umich.edu } 5127583SAli.Saidi@arm.com case MISCREG_ACTLR: 5137583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 5147583SAli.Saidi@arm.com break; 51510461SAndreas.Sandberg@ARM.com 51610461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 51710461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 51810461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 51910461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 52010461SAndreas.Sandberg@ARM.com return pmu->readMiscReg(misc_reg); 52110461SAndreas.Sandberg@ARM.com 5228302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 5238302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 5247783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 5257783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 5267783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 5277783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 52810037SARM gem5 Developers case MISCREG_FPSR: 52910037SARM gem5 Developers { 53010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 53110037SARM gem5 Developers FPSCR fpscrMask = 0; 53210037SARM gem5 Developers fpscrMask.ioc = ones; 53310037SARM gem5 Developers fpscrMask.dzc = ones; 53410037SARM gem5 Developers fpscrMask.ofc = ones; 53510037SARM gem5 Developers fpscrMask.ufc = ones; 53610037SARM gem5 Developers fpscrMask.ixc = ones; 53710037SARM gem5 Developers fpscrMask.idc = ones; 53810037SARM gem5 Developers fpscrMask.qc = ones; 53910037SARM gem5 Developers fpscrMask.v = ones; 54010037SARM gem5 Developers fpscrMask.c = ones; 54110037SARM gem5 Developers fpscrMask.z = ones; 54210037SARM gem5 Developers fpscrMask.n = ones; 54310037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 54410037SARM gem5 Developers } 54510037SARM gem5 Developers case MISCREG_FPCR: 54610037SARM gem5 Developers { 54710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 54810037SARM gem5 Developers FPSCR fpscrMask = 0; 54910037SARM gem5 Developers fpscrMask.len = ones; 55010037SARM gem5 Developers fpscrMask.stride = ones; 55110037SARM gem5 Developers fpscrMask.rMode = ones; 55210037SARM gem5 Developers fpscrMask.fz = ones; 55310037SARM gem5 Developers fpscrMask.dn = ones; 55410037SARM gem5 Developers fpscrMask.ahp = ones; 55510037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask; 55610037SARM gem5 Developers } 55710037SARM gem5 Developers case MISCREG_NZCV: 55810037SARM gem5 Developers { 55910037SARM gem5 Developers CPSR cpsr = 0; 56010338SCurtis.Dunham@arm.com cpsr.nz = tc->readCCReg(CCREG_NZ); 56110338SCurtis.Dunham@arm.com cpsr.c = tc->readCCReg(CCREG_C); 56210338SCurtis.Dunham@arm.com cpsr.v = tc->readCCReg(CCREG_V); 56310037SARM gem5 Developers return cpsr; 56410037SARM gem5 Developers } 56510037SARM gem5 Developers case MISCREG_DAIF: 56610037SARM gem5 Developers { 56710037SARM gem5 Developers CPSR cpsr = 0; 56810037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif; 56910037SARM gem5 Developers return cpsr; 57010037SARM gem5 Developers } 57110037SARM gem5 Developers case MISCREG_SP_EL0: 57210037SARM gem5 Developers { 57310037SARM gem5 Developers return tc->readIntReg(INTREG_SP0); 57410037SARM gem5 Developers } 57510037SARM gem5 Developers case MISCREG_SP_EL1: 57610037SARM gem5 Developers { 57710037SARM gem5 Developers return tc->readIntReg(INTREG_SP1); 57810037SARM gem5 Developers } 57910037SARM gem5 Developers case MISCREG_SP_EL2: 58010037SARM gem5 Developers { 58110037SARM gem5 Developers return tc->readIntReg(INTREG_SP2); 58210037SARM gem5 Developers } 58310037SARM gem5 Developers case MISCREG_SPSEL: 58410037SARM gem5 Developers { 58510037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0x1; 58610037SARM gem5 Developers } 58710037SARM gem5 Developers case MISCREG_CURRENTEL: 58810037SARM gem5 Developers { 58910037SARM gem5 Developers return miscRegs[MISCREG_CPSR] & 0xc; 59010037SARM gem5 Developers } 5918549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 5928868SMatt.Horsnell@arm.com { 5938868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 5948868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 5958868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 5968868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 5978868SMatt.Horsnell@arm.com return l2ctlr; 5988868SMatt.Horsnell@arm.com } 5998868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 6008868SMatt.Horsnell@arm.com /* For now just implement the version number. 60110461SAndreas.Sandberg@ARM.com * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5) 6028868SMatt.Horsnell@arm.com */ 60310461SAndreas.Sandberg@ARM.com return 0x5 << 16; 60410037SARM gem5 Developers case MISCREG_DBGDSCRint: 6058868SMatt.Horsnell@arm.com return 0; 60610037SARM gem5 Developers case MISCREG_ISR: 60711150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 60810037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR), 60910037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 61010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR)); 61110037SARM gem5 Developers case MISCREG_ISR_EL1: 61211150Smitch.hayenga@arm.com return tc->getCpuPtr()->getInterruptController(tc->threadId())->getISR( 61310037SARM gem5 Developers readMiscRegNoEffect(MISCREG_HCR_EL2), 61410037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR), 61510037SARM gem5 Developers readMiscRegNoEffect(MISCREG_SCR_EL3)); 61610037SARM gem5 Developers case MISCREG_DCZID_EL0: 61710037SARM gem5 Developers return 0x04; // DC ZVA clear 64-byte chunks 61810037SARM gem5 Developers case MISCREG_HCPTR: 61910037SARM gem5 Developers { 62010037SARM gem5 Developers MiscReg val = readMiscRegNoEffect(misc_reg); 62110037SARM gem5 Developers // The trap bit associated with CP14 is defined as RAZ 62210037SARM gem5 Developers val &= ~(1 << 14); 62310037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 62410037SARM gem5 Developers // HCPTR is RAO/WI 62510037SARM gem5 Developers bool secure_lookup = haveSecurity && 62610037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 62710037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 62810037SARM gem5 Developers if (!secure_lookup) { 62910037SARM gem5 Developers MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR); 63010037SARM gem5 Developers val |= (mask ^ 0x7FFF) & 0xBFFF; 63110037SARM gem5 Developers } 63210037SARM gem5 Developers // Set the bits for unimplemented coprocessors to RAO/WI 63310037SARM gem5 Developers val |= 0x33FF; 63410037SARM gem5 Developers return (val); 63510037SARM gem5 Developers } 63610037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 63710037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_DFAR_S); 63810037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 63910037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_IFAR_S); 64010037SARM gem5 Developers case MISCREG_HVBAR: // bottom bits reserved 64110037SARM gem5 Developers return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0; 64211769SCurtis.Dunham@arm.com case MISCREG_SCTLR: 64311769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x72DD39FF) | 0x00C00818; 64410037SARM gem5 Developers case MISCREG_SCTLR_EL1: 64511770SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x37DDDBBF) | 0x30D00800; 64611770SCurtis.Dunham@arm.com case MISCREG_SCTLR_EL2: 64710037SARM gem5 Developers case MISCREG_SCTLR_EL3: 64811770SCurtis.Dunham@arm.com case MISCREG_HSCTLR: 64911769SCurtis.Dunham@arm.com return (readMiscRegNoEffect(misc_reg) & 0x32CD183F) | 0x30C50830; 65010844Sandreas.sandberg@arm.com 65111772SCurtis.Dunham@arm.com case MISCREG_ID_PFR0: 65211772SCurtis.Dunham@arm.com // !ThumbEE | !Jazelle | Thumb | ARM 65311772SCurtis.Dunham@arm.com return 0x00000031; 65411772SCurtis.Dunham@arm.com case MISCREG_ID_PFR1: 65511774SCurtis.Dunham@arm.com { // Timer | Virti | !M Profile | TrustZone | ARMv4 65611774SCurtis.Dunham@arm.com bool haveTimer = (system->getGenericTimer() != NULL); 65711774SCurtis.Dunham@arm.com return 0x00000001 65811774SCurtis.Dunham@arm.com | (haveSecurity ? 0x00000010 : 0x0) 65911774SCurtis.Dunham@arm.com | (haveVirtualization ? 0x00001000 : 0x0) 66011774SCurtis.Dunham@arm.com | (haveTimer ? 0x00010000 : 0x0); 66111774SCurtis.Dunham@arm.com } 66211773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR0_EL1: 66311773SCurtis.Dunham@arm.com return 0x0000000000000002 // AArch{64,32} supported at EL0 66411773SCurtis.Dunham@arm.com | 0x0000000000000020 // EL1 66511773SCurtis.Dunham@arm.com | (haveVirtualization ? 0x0000000000000200 : 0) // EL2 66611773SCurtis.Dunham@arm.com | (haveSecurity ? 0x0000000000002000 : 0); // EL3 66711773SCurtis.Dunham@arm.com case MISCREG_ID_AA64PFR1_EL1: 66811773SCurtis.Dunham@arm.com return 0; // bits [63:0] RES0 (reserved for future use) 66911772SCurtis.Dunham@arm.com 67010037SARM gem5 Developers // Generic Timer registers 67112816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 67212816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 67312816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 67410844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 67510844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 67610844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 67710844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 67810844Sandreas.sandberg@arm.com return getGenericTimer(tc).readMiscReg(misc_reg); 67910844Sandreas.sandberg@arm.com 68010188Sgeoffrey.blake@arm.com default: 68110037SARM gem5 Developers break; 68210037SARM gem5 Developers 6837405SAli.Saidi@ARM.com } 6847405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 6857405SAli.Saidi@ARM.com} 6867405SAli.Saidi@ARM.com 6877405SAli.Saidi@ARM.comvoid 6887405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 6897405SAli.Saidi@ARM.com{ 6907405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 6917614Sminkyu.jeong@arm.com 69212478SCurtis.Dunham@arm.com const auto ® = lookUpMiscReg[misc_reg]; // bit masks 69312478SCurtis.Dunham@arm.com const auto &map = getMiscIndices(misc_reg); 69412478SCurtis.Dunham@arm.com int lower = map.first, upper = map.second; 69512478SCurtis.Dunham@arm.com 69612478SCurtis.Dunham@arm.com auto v = (val & ~reg.wi()) | reg.rao(); 69711771SCurtis.Dunham@arm.com if (upper > 0) { 69812478SCurtis.Dunham@arm.com miscRegs[lower] = bits(v, 31, 0); 69912478SCurtis.Dunham@arm.com miscRegs[upper] = bits(v, 63, 32); 70010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n", 70112478SCurtis.Dunham@arm.com misc_reg, lower, upper, v); 70210037SARM gem5 Developers } else { 70312478SCurtis.Dunham@arm.com miscRegs[lower] = v; 70410037SARM gem5 Developers DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", 70512478SCurtis.Dunham@arm.com misc_reg, lower, v); 70610037SARM gem5 Developers } 7077405SAli.Saidi@ARM.com} 7087405SAli.Saidi@ARM.com 7097405SAli.Saidi@ARM.comvoid 7107405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 7117405SAli.Saidi@ARM.com{ 7127749SAli.Saidi@ARM.com 7137405SAli.Saidi@ARM.com MiscReg newVal = val; 71410037SARM gem5 Developers bool secure_lookup; 71510037SARM gem5 Developers SCR scr; 7168284SAli.Saidi@ARM.com 7177405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 7187405SAli.Saidi@ARM.com updateRegMap(val); 7197749SAli.Saidi@ARM.com 7207749SAli.Saidi@ARM.com 7217749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 7227749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 7237405SAli.Saidi@ARM.com CPSR cpsr = val; 72412510Sgiacomo.travaglini@arm.com if (old_mode != cpsr.mode || cpsr.il != old_cpsr.il) { 72512406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 72612406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 7277749SAli.Saidi@ARM.com } 7287749SAli.Saidi@ARM.com 7297614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 7307614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 7317720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 7327720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 7337720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 73412763Sgiacomo.travaglini@arm.com pc.illegalExec(cpsr.il == 1); 7358887Sgeoffrey.blake@arm.com 7368887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 7378887Sgeoffrey.blake@arm.com // is connected 7388887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 7398887Sgeoffrey.blake@arm.com if (checker) { 7408887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 7418887Sgeoffrey.blake@arm.com } else { 7428887Sgeoffrey.blake@arm.com tc->pcState(pc); 7438887Sgeoffrey.blake@arm.com } 7447408Sgblack@eecs.umich.edu } else { 74510037SARM gem5 Developers#ifndef NDEBUG 74610037SARM gem5 Developers if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) { 74710037SARM gem5 Developers if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL]) 74810037SARM gem5 Developers warn("Unimplemented system register %s write with %#x.\n", 74910037SARM gem5 Developers miscRegName[misc_reg], val); 75010037SARM gem5 Developers else 75110037SARM gem5 Developers panic("Unimplemented system register %s write with %#x.\n", 75210037SARM gem5 Developers miscRegName[misc_reg], val); 75310037SARM gem5 Developers } 75410037SARM gem5 Developers#endif 75510037SARM gem5 Developers switch (unflattenMiscReg(misc_reg)) { 7567408Sgblack@eecs.umich.edu case MISCREG_CPACR: 7577408Sgblack@eecs.umich.edu { 7588206SWilliam.Wang@arm.com 7598206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 7608206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 7618206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 7628206SWilliam.Wang@arm.com // be writable 7638206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 7648206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 7658206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 76610037SARM gem5 Developers 76710037SARM gem5 Developers // Security Extensions may limit the writability of CPACR 76810037SARM gem5 Developers if (haveSecurity) { 76910037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 77010037SARM gem5 Developers CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR); 77112667Schuan.zhu@arm.com if (scr.ns && (cpsr.mode != MODE_MON) && ELIs32(tc, EL3)) { 77210037SARM gem5 Developers NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR); 77310037SARM gem5 Developers // NB: Skipping the full loop, here 77410037SARM gem5 Developers if (!nsacr.cp10) cpacrMask.cp10 = 0; 77510037SARM gem5 Developers if (!nsacr.cp11) cpacrMask.cp11 = 0; 77610037SARM gem5 Developers } 77710037SARM gem5 Developers } 77810037SARM gem5 Developers 77910037SARM gem5 Developers MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR); 7808206SWilliam.Wang@arm.com newVal &= cpacrMask; 78110037SARM gem5 Developers newVal |= old_val & ~cpacrMask; 78210037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 78310037SARM gem5 Developers miscRegName[misc_reg], newVal); 78410037SARM gem5 Developers } 78510037SARM gem5 Developers break; 78610037SARM gem5 Developers case MISCREG_CPTR_EL2: 78710037SARM gem5 Developers { 78810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 78910037SARM gem5 Developers CPTR cptrMask = 0; 79010037SARM gem5 Developers cptrMask.tcpac = ones; 79110037SARM gem5 Developers cptrMask.tta = ones; 79210037SARM gem5 Developers cptrMask.tfp = ones; 79310037SARM gem5 Developers newVal &= cptrMask; 79410037SARM gem5 Developers cptrMask = 0; 79510037SARM gem5 Developers cptrMask.res1_13_12_el2 = ones; 79610037SARM gem5 Developers cptrMask.res1_9_0_el2 = ones; 79710037SARM gem5 Developers newVal |= cptrMask; 79810037SARM gem5 Developers DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 79910037SARM gem5 Developers miscRegName[misc_reg], newVal); 80010037SARM gem5 Developers } 80110037SARM gem5 Developers break; 80210037SARM gem5 Developers case MISCREG_CPTR_EL3: 80310037SARM gem5 Developers { 80410037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 80510037SARM gem5 Developers CPTR cptrMask = 0; 80610037SARM gem5 Developers cptrMask.tcpac = ones; 80710037SARM gem5 Developers cptrMask.tta = ones; 80810037SARM gem5 Developers cptrMask.tfp = ones; 80910037SARM gem5 Developers newVal &= cptrMask; 8108206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 8118206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 8127408Sgblack@eecs.umich.edu } 8137408Sgblack@eecs.umich.edu break; 8147408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 8157731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 8168206SWilliam.Wang@arm.com return; 81710037SARM gem5 Developers 81810037SARM gem5 Developers case MISCREG_DC_ZVA_Xt: 81910037SARM gem5 Developers warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n"); 82010037SARM gem5 Developers return; 82110037SARM gem5 Developers 8227408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 8237408Sgblack@eecs.umich.edu { 8247408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 8257408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 8267408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 8277408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 8287408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 8297408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 8307408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 8317408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 83210037SARM gem5 Developers fpscrMask.ioe = ones; 83310037SARM gem5 Developers fpscrMask.dze = ones; 83410037SARM gem5 Developers fpscrMask.ofe = ones; 83510037SARM gem5 Developers fpscrMask.ufe = ones; 83610037SARM gem5 Developers fpscrMask.ixe = ones; 83710037SARM gem5 Developers fpscrMask.ide = ones; 8387408Sgblack@eecs.umich.edu fpscrMask.len = ones; 8397408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 8407408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 8417408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 8427408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 8437408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 8447408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 8457408Sgblack@eecs.umich.edu fpscrMask.v = ones; 8467408Sgblack@eecs.umich.edu fpscrMask.c = ones; 8477408Sgblack@eecs.umich.edu fpscrMask.z = ones; 8487408Sgblack@eecs.umich.edu fpscrMask.n = ones; 8497408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 85010037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 85110037SARM gem5 Developers ~(uint32_t)fpscrMask); 8529377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 8537408Sgblack@eecs.umich.edu } 8547408Sgblack@eecs.umich.edu break; 85510037SARM gem5 Developers case MISCREG_FPSR: 85610037SARM gem5 Developers { 85710037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 85810037SARM gem5 Developers FPSCR fpscrMask = 0; 85910037SARM gem5 Developers fpscrMask.ioc = ones; 86010037SARM gem5 Developers fpscrMask.dzc = ones; 86110037SARM gem5 Developers fpscrMask.ofc = ones; 86210037SARM gem5 Developers fpscrMask.ufc = ones; 86310037SARM gem5 Developers fpscrMask.ixc = ones; 86410037SARM gem5 Developers fpscrMask.idc = ones; 86510037SARM gem5 Developers fpscrMask.qc = ones; 86610037SARM gem5 Developers fpscrMask.v = ones; 86710037SARM gem5 Developers fpscrMask.c = ones; 86810037SARM gem5 Developers fpscrMask.z = ones; 86910037SARM gem5 Developers fpscrMask.n = ones; 87010037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 87110037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 87210037SARM gem5 Developers ~(uint32_t)fpscrMask); 87310037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 87410037SARM gem5 Developers } 87510037SARM gem5 Developers break; 87610037SARM gem5 Developers case MISCREG_FPCR: 87710037SARM gem5 Developers { 87810037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 87910037SARM gem5 Developers FPSCR fpscrMask = 0; 88010037SARM gem5 Developers fpscrMask.len = ones; 88110037SARM gem5 Developers fpscrMask.stride = ones; 88210037SARM gem5 Developers fpscrMask.rMode = ones; 88310037SARM gem5 Developers fpscrMask.fz = ones; 88410037SARM gem5 Developers fpscrMask.dn = ones; 88510037SARM gem5 Developers fpscrMask.ahp = ones; 88610037SARM gem5 Developers newVal = (newVal & (uint32_t)fpscrMask) | 88710037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPSCR) & 88810037SARM gem5 Developers ~(uint32_t)fpscrMask); 88910037SARM gem5 Developers misc_reg = MISCREG_FPSCR; 89010037SARM gem5 Developers } 89110037SARM gem5 Developers break; 8928302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 8938302SAli.Saidi@ARM.com { 8948302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 89510037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal; 8968302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 8978302SAli.Saidi@ARM.com } 8988302SAli.Saidi@ARM.com break; 8997783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 9007783SGiacomo.Gabrielli@arm.com { 90110037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 90210037SARM gem5 Developers (newVal & FpscrQcMask); 9037783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9047783SGiacomo.Gabrielli@arm.com } 9057783SGiacomo.Gabrielli@arm.com break; 9067783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 9077783SGiacomo.Gabrielli@arm.com { 90810037SARM gem5 Developers newVal = readMiscRegNoEffect(MISCREG_FPSCR) | 90910037SARM gem5 Developers (newVal & FpscrExcMask); 9107783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 9117783SGiacomo.Gabrielli@arm.com } 9127783SGiacomo.Gabrielli@arm.com break; 9137408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 9147408Sgblack@eecs.umich.edu { 9158206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 9168206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 9177408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 9187408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 91910037SARM gem5 Developers (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask); 9207408Sgblack@eecs.umich.edu } 9217408Sgblack@eecs.umich.edu break; 92210037SARM gem5 Developers case MISCREG_HCR: 92310037SARM gem5 Developers { 92410037SARM gem5 Developers if (!haveVirtualization) 92510037SARM gem5 Developers return; 92610037SARM gem5 Developers } 92710037SARM gem5 Developers break; 92810037SARM gem5 Developers case MISCREG_IFSR: 92910037SARM gem5 Developers { 93010037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.96 93110037SARM gem5 Developers const uint32_t ifsrMask = 93210037SARM gem5 Developers mask(31, 13) | mask(11, 11) | mask(8, 6); 93310037SARM gem5 Developers newVal = newVal & ~ifsrMask; 93410037SARM gem5 Developers } 93510037SARM gem5 Developers break; 93610037SARM gem5 Developers case MISCREG_DFSR: 93710037SARM gem5 Developers { 93810037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.52 93910037SARM gem5 Developers const uint32_t dfsrMask = mask(31, 14) | mask(8, 8); 94010037SARM gem5 Developers newVal = newVal & ~dfsrMask; 94110037SARM gem5 Developers } 94210037SARM gem5 Developers break; 94310037SARM gem5 Developers case MISCREG_AMAIR0: 94410037SARM gem5 Developers case MISCREG_AMAIR1: 94510037SARM gem5 Developers { 94610037SARM gem5 Developers // ARM ARM (ARM DDI 0406C.b) B4.1.5 94710037SARM gem5 Developers // Valid only with LPAE 94810037SARM gem5 Developers if (!haveLPAE) 94910037SARM gem5 Developers return; 95010037SARM gem5 Developers DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal); 95110037SARM gem5 Developers } 95210037SARM gem5 Developers break; 95310037SARM gem5 Developers case MISCREG_SCR: 95412406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 95512406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 95610037SARM gem5 Developers break; 9577408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 9587408Sgblack@eecs.umich.edu { 9597408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 96010037SARM gem5 Developers scr = readMiscRegNoEffect(MISCREG_SCR); 96112639Sgiacomo.travaglini@arm.com 96212639Sgiacomo.travaglini@arm.com MiscRegIndex sctlr_idx; 96312639Sgiacomo.travaglini@arm.com if (haveSecurity && !highestELIs64 && !scr.ns) { 96412639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_S; 96512639Sgiacomo.travaglini@arm.com } else { 96612639Sgiacomo.travaglini@arm.com sctlr_idx = MISCREG_SCTLR_NS; 96712639Sgiacomo.travaglini@arm.com } 96812639Sgiacomo.travaglini@arm.com 96910037SARM gem5 Developers SCTLR sctlr = miscRegs[sctlr_idx]; 9707408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 97110037SARM gem5 Developers new_sctlr.nmfi = ((bool)sctlr.nmfi) && !haveVirtualization; 97210037SARM gem5 Developers miscRegs[sctlr_idx] = (MiscReg)new_sctlr; 97312406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 97412406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 9757408Sgblack@eecs.umich.edu } 9769385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 9779385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 9789385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 97910461SAndreas.Sandberg@ARM.com case MISCREG_ID_DFR0: 9809385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 9819385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 9829385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 9839385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 9849385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 9859385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 9869385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 9879385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 9889385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 9899385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 9909385SAndreas.Sandberg@arm.com 9919385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 9929385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 9937408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 9947408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 9957408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 99610037SARM gem5 Developers 99710037SARM gem5 Developers case MISCREG_ID_AA64AFR0_EL1: 99810037SARM gem5 Developers case MISCREG_ID_AA64AFR1_EL1: 99910037SARM gem5 Developers case MISCREG_ID_AA64DFR0_EL1: 100010037SARM gem5 Developers case MISCREG_ID_AA64DFR1_EL1: 100110037SARM gem5 Developers case MISCREG_ID_AA64ISAR0_EL1: 100210037SARM gem5 Developers case MISCREG_ID_AA64ISAR1_EL1: 100310037SARM gem5 Developers case MISCREG_ID_AA64MMFR0_EL1: 100410037SARM gem5 Developers case MISCREG_ID_AA64MMFR1_EL1: 100510037SARM gem5 Developers case MISCREG_ID_AA64PFR0_EL1: 100610037SARM gem5 Developers case MISCREG_ID_AA64PFR1_EL1: 10079385SAndreas.Sandberg@arm.com // ID registers are constants. 10087408Sgblack@eecs.umich.edu return; 10099385SAndreas.Sandberg@arm.com 101012605Sgiacomo.travaglini@arm.com // TLB Invalidate All 101112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIALL: // TLBI all entries, EL0&1, 101212605Sgiacomo.travaglini@arm.com { 101312605Sgiacomo.travaglini@arm.com assert32(tc); 101412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 101512605Sgiacomo.travaglini@arm.com 101612605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 101712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 101812605Sgiacomo.travaglini@arm.com return; 101912605Sgiacomo.travaglini@arm.com } 102012605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Inner Shareable 10217408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 102212605Sgiacomo.travaglini@arm.com { 102312605Sgiacomo.travaglini@arm.com assert32(tc); 102412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 102512605Sgiacomo.travaglini@arm.com 102612605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 102712605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 102812605Sgiacomo.travaglini@arm.com return; 102912605Sgiacomo.travaglini@arm.com } 103012605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate All 10317408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 103212605Sgiacomo.travaglini@arm.com { 103312605Sgiacomo.travaglini@arm.com assert32(tc); 103412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 103512605Sgiacomo.travaglini@arm.com 103612605Sgiacomo.travaglini@arm.com ITLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 103712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 103812605Sgiacomo.travaglini@arm.com return; 103912605Sgiacomo.travaglini@arm.com } 104012605Sgiacomo.travaglini@arm.com // Data TLB Invalidate All 10417408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 104212605Sgiacomo.travaglini@arm.com { 104312605Sgiacomo.travaglini@arm.com assert32(tc); 104412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 104512605Sgiacomo.travaglini@arm.com 104612605Sgiacomo.travaglini@arm.com DTLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 104712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 104812605Sgiacomo.travaglini@arm.com return; 104912605Sgiacomo.travaglini@arm.com } 105012605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA 105112605Sgiacomo.travaglini@arm.com // mcr tlbimval(is) is invalidating all matching entries 105212605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 105312605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 105412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVA: 105512576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAL: 105612605Sgiacomo.travaglini@arm.com { 105712605Sgiacomo.travaglini@arm.com assert32(tc); 105812605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 105912605Sgiacomo.travaglini@arm.com 106012605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 106112605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 106212605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 106312605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 106412605Sgiacomo.travaglini@arm.com 106512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 106612605Sgiacomo.travaglini@arm.com return; 106712605Sgiacomo.travaglini@arm.com } 106812605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Inner Shareable 106912605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAIS: 107012576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALIS: 107112605Sgiacomo.travaglini@arm.com { 107212605Sgiacomo.travaglini@arm.com assert32(tc); 107312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 107412605Sgiacomo.travaglini@arm.com 107512605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, 107612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 107712605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 107812605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 107912605Sgiacomo.travaglini@arm.com 108012605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 108112605Sgiacomo.travaglini@arm.com return; 108212605Sgiacomo.travaglini@arm.com } 108312605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match 108412605Sgiacomo.travaglini@arm.com case MISCREG_TLBIASID: 108512605Sgiacomo.travaglini@arm.com { 108612605Sgiacomo.travaglini@arm.com assert32(tc); 108712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 108812605Sgiacomo.travaglini@arm.com 108912605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 109012605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 109112605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 109212605Sgiacomo.travaglini@arm.com 109312605Sgiacomo.travaglini@arm.com tlbiOp(tc); 109412605Sgiacomo.travaglini@arm.com return; 109512605Sgiacomo.travaglini@arm.com } 109612605Sgiacomo.travaglini@arm.com // TLB Invalidate by ASID match, Inner Shareable 10977408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 109812605Sgiacomo.travaglini@arm.com { 109912605Sgiacomo.travaglini@arm.com assert32(tc); 110012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 110112605Sgiacomo.travaglini@arm.com 110212605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, 110312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 110412605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 110512605Sgiacomo.travaglini@arm.com 110612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 110712605Sgiacomo.travaglini@arm.com return; 110812605Sgiacomo.travaglini@arm.com } 110912605Sgiacomo.travaglini@arm.com // mcr tlbimvaal(is) is invalidating all matching entries 111012605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 111112605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 111212605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID 111312605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAA: 111412576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAL: 111512605Sgiacomo.travaglini@arm.com { 111612605Sgiacomo.travaglini@arm.com assert32(tc); 111712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 111812605Sgiacomo.travaglini@arm.com 111912605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 112012605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 112112605Sgiacomo.travaglini@arm.com 112212605Sgiacomo.travaglini@arm.com tlbiOp(tc); 112312605Sgiacomo.travaglini@arm.com return; 112412605Sgiacomo.travaglini@arm.com } 112512605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, All ASID, Inner Shareable 112612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAAIS: 112712576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAALIS: 112812605Sgiacomo.travaglini@arm.com { 112912605Sgiacomo.travaglini@arm.com assert32(tc); 113012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 113112605Sgiacomo.travaglini@arm.com 113212605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 113312605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), false); 113412605Sgiacomo.travaglini@arm.com 113512605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 113612605Sgiacomo.travaglini@arm.com return; 113712605Sgiacomo.travaglini@arm.com } 113812605Sgiacomo.travaglini@arm.com // mcr tlbimvalh(is) is invalidating all matching entries 113912605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 114012605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 114112605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode 114212605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAH: 114312576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALH: 114412605Sgiacomo.travaglini@arm.com { 114512605Sgiacomo.travaglini@arm.com assert32(tc); 114612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 114712605Sgiacomo.travaglini@arm.com 114812605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 114912605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 115012605Sgiacomo.travaglini@arm.com 115112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 115212605Sgiacomo.travaglini@arm.com return; 115312605Sgiacomo.travaglini@arm.com } 115412605Sgiacomo.travaglini@arm.com // TLB Invalidate by VA, Hyp mode, Inner Shareable 115512605Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVAHIS: 115612576Sgiacomo.travaglini@arm.com case MISCREG_TLBIMVALHIS: 115712605Sgiacomo.travaglini@arm.com { 115812605Sgiacomo.travaglini@arm.com assert32(tc); 115912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 116012605Sgiacomo.travaglini@arm.com 116112605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 116212605Sgiacomo.travaglini@arm.com mbits(newVal, 31,12), true); 116312605Sgiacomo.travaglini@arm.com 116412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 116512605Sgiacomo.travaglini@arm.com return; 116612605Sgiacomo.travaglini@arm.com } 116712605Sgiacomo.travaglini@arm.com // mcr tlbiipas2l(is) is invalidating all matching entries 116812605Sgiacomo.travaglini@arm.com // regardless of the level of lookup, since in gem5 we cache 116912605Sgiacomo.travaglini@arm.com // in the tlb the last level of lookup only. 117012605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2 117112605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2: 117212577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2L: 117312605Sgiacomo.travaglini@arm.com { 117412605Sgiacomo.travaglini@arm.com assert32(tc); 117512605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 117612605Sgiacomo.travaglini@arm.com 117712605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 117812605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 117912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 118012605Sgiacomo.travaglini@arm.com 118112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 118212605Sgiacomo.travaglini@arm.com return; 118312605Sgiacomo.travaglini@arm.com } 118412605Sgiacomo.travaglini@arm.com // TLB Invalidate by Intermediate Physical Address, Stage 2, 118512605Sgiacomo.travaglini@arm.com // Inner Shareable 118612605Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2IS: 118712577Sgiacomo.travaglini@arm.com case MISCREG_TLBIIPAS2LIS: 118812605Sgiacomo.travaglini@arm.com { 118912605Sgiacomo.travaglini@arm.com assert32(tc); 119012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 119112605Sgiacomo.travaglini@arm.com 119212605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, 119312605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 119412605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 119512605Sgiacomo.travaglini@arm.com 119612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 119712605Sgiacomo.travaglini@arm.com return; 119812605Sgiacomo.travaglini@arm.com } 119912605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by VA 120010037SARM gem5 Developers case MISCREG_ITLBIMVA: 120112605Sgiacomo.travaglini@arm.com { 120212605Sgiacomo.travaglini@arm.com assert32(tc); 120312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 120412605Sgiacomo.travaglini@arm.com 120512605Sgiacomo.travaglini@arm.com ITLBIMVA tlbiOp(EL1, 120612605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 120712605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 120812605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 120912605Sgiacomo.travaglini@arm.com 121012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 121112605Sgiacomo.travaglini@arm.com return; 121212605Sgiacomo.travaglini@arm.com } 121312605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by VA 121410037SARM gem5 Developers case MISCREG_DTLBIMVA: 121512605Sgiacomo.travaglini@arm.com { 121612605Sgiacomo.travaglini@arm.com assert32(tc); 121712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 121812605Sgiacomo.travaglini@arm.com 121912605Sgiacomo.travaglini@arm.com DTLBIMVA tlbiOp(EL1, 122012605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 122112605Sgiacomo.travaglini@arm.com mbits(newVal, 31, 12), 122212605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 122312605Sgiacomo.travaglini@arm.com 122412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 122512605Sgiacomo.travaglini@arm.com return; 122612605Sgiacomo.travaglini@arm.com } 122712605Sgiacomo.travaglini@arm.com // Instruction TLB Invalidate by ASID match 122810037SARM gem5 Developers case MISCREG_ITLBIASID: 122912605Sgiacomo.travaglini@arm.com { 123012605Sgiacomo.travaglini@arm.com assert32(tc); 123112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 123212605Sgiacomo.travaglini@arm.com 123312605Sgiacomo.travaglini@arm.com ITLBIASID tlbiOp(EL1, 123412605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 123512605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 123612605Sgiacomo.travaglini@arm.com 123712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 123812605Sgiacomo.travaglini@arm.com return; 123912605Sgiacomo.travaglini@arm.com } 124012605Sgiacomo.travaglini@arm.com // Data TLB Invalidate by ASID match 124110037SARM gem5 Developers case MISCREG_DTLBIASID: 124212605Sgiacomo.travaglini@arm.com { 124312605Sgiacomo.travaglini@arm.com assert32(tc); 124412605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 124512605Sgiacomo.travaglini@arm.com 124612605Sgiacomo.travaglini@arm.com DTLBIASID tlbiOp(EL1, 124712605Sgiacomo.travaglini@arm.com haveSecurity && !scr.ns, 124812605Sgiacomo.travaglini@arm.com bits(newVal, 7,0)); 124912605Sgiacomo.travaglini@arm.com 125012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 125112605Sgiacomo.travaglini@arm.com return; 125212605Sgiacomo.travaglini@arm.com } 125312605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp 125410037SARM gem5 Developers case MISCREG_TLBIALLNSNH: 125512605Sgiacomo.travaglini@arm.com { 125612605Sgiacomo.travaglini@arm.com assert32(tc); 125712605Sgiacomo.travaglini@arm.com 125812605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 125912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 126012605Sgiacomo.travaglini@arm.com return; 126112605Sgiacomo.travaglini@arm.com } 126212605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Non-Secure Non-Hyp, Inner Shareable 126310037SARM gem5 Developers case MISCREG_TLBIALLNSNHIS: 126412605Sgiacomo.travaglini@arm.com { 126512605Sgiacomo.travaglini@arm.com assert32(tc); 126612605Sgiacomo.travaglini@arm.com 126712605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, false); 126812605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 126912605Sgiacomo.travaglini@arm.com return; 127012605Sgiacomo.travaglini@arm.com } 127112605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode 127210037SARM gem5 Developers case MISCREG_TLBIALLH: 127312605Sgiacomo.travaglini@arm.com { 127412605Sgiacomo.travaglini@arm.com assert32(tc); 127512605Sgiacomo.travaglini@arm.com 127612605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 127712605Sgiacomo.travaglini@arm.com tlbiOp(tc); 127812605Sgiacomo.travaglini@arm.com return; 127912605Sgiacomo.travaglini@arm.com } 128012605Sgiacomo.travaglini@arm.com // TLB Invalidate All, Hyp mode, Inner Shareable 128110037SARM gem5 Developers case MISCREG_TLBIALLHIS: 128212605Sgiacomo.travaglini@arm.com { 128312605Sgiacomo.travaglini@arm.com assert32(tc); 128412605Sgiacomo.travaglini@arm.com 128512605Sgiacomo.travaglini@arm.com TLBIALLN tlbiOp(EL1, true); 128612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 128712605Sgiacomo.travaglini@arm.com return; 128812605Sgiacomo.travaglini@arm.com } 128912605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3 129012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE3: 129112605Sgiacomo.travaglini@arm.com { 129212605Sgiacomo.travaglini@arm.com assert64(tc); 129312605Sgiacomo.travaglini@arm.com 129412605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 129512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 129612605Sgiacomo.travaglini@arm.com return; 129712605Sgiacomo.travaglini@arm.com } 129812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL3, Inner Shareable 129910037SARM gem5 Developers case MISCREG_TLBI_ALLE3IS: 130012605Sgiacomo.travaglini@arm.com { 130112605Sgiacomo.travaglini@arm.com assert64(tc); 130212605Sgiacomo.travaglini@arm.com 130312605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL3, true); 130412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 130512605Sgiacomo.travaglini@arm.com return; 130612605Sgiacomo.travaglini@arm.com } 130710037SARM gem5 Developers // @todo: uncomment this to enable Virtualization 130810037SARM gem5 Developers // case MISCREG_TLBI_ALLE2IS: 130910037SARM gem5 Developers // case MISCREG_TLBI_ALLE2: 131012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1 131110037SARM gem5 Developers case MISCREG_TLBI_ALLE1: 131210037SARM gem5 Developers case MISCREG_TLBI_VMALLE1: 131310037SARM gem5 Developers case MISCREG_TLBI_VMALLS12E1: 131410037SARM gem5 Developers // @todo: handle VMID and stage 2 to enable Virtualization 131512605Sgiacomo.travaglini@arm.com { 131612605Sgiacomo.travaglini@arm.com assert64(tc); 131712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 131812605Sgiacomo.travaglini@arm.com 131912605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 132012605Sgiacomo.travaglini@arm.com tlbiOp(tc); 132112605Sgiacomo.travaglini@arm.com return; 132212605Sgiacomo.travaglini@arm.com } 132312605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate All, EL1, Inner Shareable 132412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ALLE1IS: 132512605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLE1IS: 132612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VMALLS12E1IS: 132712605Sgiacomo.travaglini@arm.com // @todo: handle VMID and stage 2 to enable Virtualization 132812605Sgiacomo.travaglini@arm.com { 132912605Sgiacomo.travaglini@arm.com assert64(tc); 133012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 133112605Sgiacomo.travaglini@arm.com 133212605Sgiacomo.travaglini@arm.com TLBIALL tlbiOp(EL1, haveSecurity && !scr.ns); 133312605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 133412605Sgiacomo.travaglini@arm.com return; 133512605Sgiacomo.travaglini@arm.com } 133612605Sgiacomo.travaglini@arm.com // VAEx(IS) and VALEx(IS) are the same because TLBs 133712605Sgiacomo.travaglini@arm.com // only store entries 133810037SARM gem5 Developers // from the last level of translation table walks 133910037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 134012605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3 134112605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE3_Xt: 134212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE3_Xt: 134312605Sgiacomo.travaglini@arm.com { 134412605Sgiacomo.travaglini@arm.com assert64(tc); 134512605Sgiacomo.travaglini@arm.com 134612605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 134712605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 134812605Sgiacomo.travaglini@arm.com 0xbeef); 134912605Sgiacomo.travaglini@arm.com tlbiOp(tc); 135012605Sgiacomo.travaglini@arm.com return; 135112605Sgiacomo.travaglini@arm.com } 135212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL3, Inner Shareable 135310037SARM gem5 Developers case MISCREG_TLBI_VAE3IS_Xt: 135410037SARM gem5 Developers case MISCREG_TLBI_VALE3IS_Xt: 135512605Sgiacomo.travaglini@arm.com { 135612605Sgiacomo.travaglini@arm.com assert64(tc); 135712605Sgiacomo.travaglini@arm.com 135812605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL3, true, 135912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 136012605Sgiacomo.travaglini@arm.com 0xbeef); 136112605Sgiacomo.travaglini@arm.com 136212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 136312605Sgiacomo.travaglini@arm.com return; 136412605Sgiacomo.travaglini@arm.com } 136512605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2 136612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE2_Xt: 136712605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE2_Xt: 136812605Sgiacomo.travaglini@arm.com { 136912605Sgiacomo.travaglini@arm.com assert64(tc); 137012605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 137112605Sgiacomo.travaglini@arm.com 137212605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 137312605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 137412605Sgiacomo.travaglini@arm.com 0xbeef); 137512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 137612605Sgiacomo.travaglini@arm.com return; 137712605Sgiacomo.travaglini@arm.com } 137812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL2, Inner Shareable 137910037SARM gem5 Developers case MISCREG_TLBI_VAE2IS_Xt: 138010037SARM gem5 Developers case MISCREG_TLBI_VALE2IS_Xt: 138112605Sgiacomo.travaglini@arm.com { 138212605Sgiacomo.travaglini@arm.com assert64(tc); 138312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 138412605Sgiacomo.travaglini@arm.com 138512605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL2, haveSecurity && !scr.ns, 138612605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 138712605Sgiacomo.travaglini@arm.com 0xbeef); 138812605Sgiacomo.travaglini@arm.com 138912605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 139012605Sgiacomo.travaglini@arm.com return; 139112605Sgiacomo.travaglini@arm.com } 139212605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1 139312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAE1_Xt: 139412605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VALE1_Xt: 139512605Sgiacomo.travaglini@arm.com { 139612605Sgiacomo.travaglini@arm.com assert64(tc); 139712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 139812605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 139912605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 140012605Sgiacomo.travaglini@arm.com 140112605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 140212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 140312605Sgiacomo.travaglini@arm.com asid); 140412605Sgiacomo.travaglini@arm.com 140512605Sgiacomo.travaglini@arm.com tlbiOp(tc); 140612605Sgiacomo.travaglini@arm.com return; 140712605Sgiacomo.travaglini@arm.com } 140812605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, EL1, Inner Shareable 140910037SARM gem5 Developers case MISCREG_TLBI_VAE1IS_Xt: 141010037SARM gem5 Developers case MISCREG_TLBI_VALE1IS_Xt: 141112605Sgiacomo.travaglini@arm.com { 141212605Sgiacomo.travaglini@arm.com assert64(tc); 141312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 141412605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 141512605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 141612605Sgiacomo.travaglini@arm.com 141712605Sgiacomo.travaglini@arm.com TLBIMVA tlbiOp(EL1, haveSecurity && !scr.ns, 141812605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, 141912605Sgiacomo.travaglini@arm.com asid); 142012605Sgiacomo.travaglini@arm.com 142112605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 142212605Sgiacomo.travaglini@arm.com return; 142312605Sgiacomo.travaglini@arm.com } 142412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1 142510037SARM gem5 Developers // @todo: handle VMID to enable Virtualization 142612605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_ASIDE1_Xt: 142712605Sgiacomo.travaglini@arm.com { 142812605Sgiacomo.travaglini@arm.com assert64(tc); 142912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 143012605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 143112605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 143212605Sgiacomo.travaglini@arm.com 143312605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 143412605Sgiacomo.travaglini@arm.com tlbiOp(tc); 143512605Sgiacomo.travaglini@arm.com return; 143612605Sgiacomo.travaglini@arm.com } 143712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by ASID, EL1, Inner Shareable 143810037SARM gem5 Developers case MISCREG_TLBI_ASIDE1IS_Xt: 143912605Sgiacomo.travaglini@arm.com { 144012605Sgiacomo.travaglini@arm.com assert64(tc); 144112605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 144212605Sgiacomo.travaglini@arm.com auto asid = haveLargeAsid64 ? bits(newVal, 63, 48) : 144312605Sgiacomo.travaglini@arm.com bits(newVal, 55, 48); 144412605Sgiacomo.travaglini@arm.com 144512605Sgiacomo.travaglini@arm.com TLBIASID tlbiOp(EL1, haveSecurity && !scr.ns, asid); 144612605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 144712605Sgiacomo.travaglini@arm.com return; 144812605Sgiacomo.travaglini@arm.com } 144910037SARM gem5 Developers // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store 145010037SARM gem5 Developers // entries from the last level of translation table walks 145112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1 145212605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAAE1_Xt: 145312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_VAALE1_Xt: 145412605Sgiacomo.travaglini@arm.com { 145512605Sgiacomo.travaglini@arm.com assert64(tc); 145612605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 145712605Sgiacomo.travaglini@arm.com 145812605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 145912605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 146012605Sgiacomo.travaglini@arm.com 146112605Sgiacomo.travaglini@arm.com tlbiOp(tc); 146212605Sgiacomo.travaglini@arm.com return; 146312605Sgiacomo.travaglini@arm.com } 146412605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by VA, All ASID, EL1, Inner Shareable 146510037SARM gem5 Developers case MISCREG_TLBI_VAAE1IS_Xt: 146610037SARM gem5 Developers case MISCREG_TLBI_VAALE1IS_Xt: 146712605Sgiacomo.travaglini@arm.com { 146812605Sgiacomo.travaglini@arm.com assert64(tc); 146912605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 147012605Sgiacomo.travaglini@arm.com 147112605Sgiacomo.travaglini@arm.com TLBIMVAA tlbiOp(EL1, haveSecurity && !scr.ns, 147212605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 43, 0)) << 12, false); 147312605Sgiacomo.travaglini@arm.com 147412605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 147512605Sgiacomo.travaglini@arm.com return; 147612605Sgiacomo.travaglini@arm.com } 147712605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 147812605Sgiacomo.travaglini@arm.com // Stage 2, EL1 147912605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1_Xt: 148012605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2LE1_Xt: 148112605Sgiacomo.travaglini@arm.com { 148212605Sgiacomo.travaglini@arm.com assert64(tc); 148312605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 148412605Sgiacomo.travaglini@arm.com 148512605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 148612605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 148712605Sgiacomo.travaglini@arm.com 148812605Sgiacomo.travaglini@arm.com tlbiOp(tc); 148912605Sgiacomo.travaglini@arm.com return; 149012605Sgiacomo.travaglini@arm.com } 149112605Sgiacomo.travaglini@arm.com // AArch64 TLB Invalidate by Intermediate Physical Address, 149212605Sgiacomo.travaglini@arm.com // Stage 2, EL1, Inner Shareable 149312605Sgiacomo.travaglini@arm.com case MISCREG_TLBI_IPAS2E1IS_Xt: 149410037SARM gem5 Developers case MISCREG_TLBI_IPAS2LE1IS_Xt: 149512605Sgiacomo.travaglini@arm.com { 149612605Sgiacomo.travaglini@arm.com assert64(tc); 149712605Sgiacomo.travaglini@arm.com scr = readMiscReg(MISCREG_SCR, tc); 149812605Sgiacomo.travaglini@arm.com 149912605Sgiacomo.travaglini@arm.com TLBIIPA tlbiOp(EL1, haveSecurity && !scr.ns, 150012605Sgiacomo.travaglini@arm.com static_cast<Addr>(bits(newVal, 35, 0)) << 12); 150112605Sgiacomo.travaglini@arm.com 150212605Sgiacomo.travaglini@arm.com tlbiOp.broadcast(tc); 150312605Sgiacomo.travaglini@arm.com return; 150412605Sgiacomo.travaglini@arm.com } 15057583SAli.Saidi@arm.com case MISCREG_ACTLR: 15067583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 15077583SAli.Saidi@arm.com break; 150810461SAndreas.Sandberg@ARM.com 150910461SAndreas.Sandberg@ARM.com case MISCREG_PMXEVTYPER_PMCCFILTR: 151010461SAndreas.Sandberg@ARM.com case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0: 151110461SAndreas.Sandberg@ARM.com case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0: 151210461SAndreas.Sandberg@ARM.com case MISCREG_PMCR ... MISCREG_PMOVSSET: 151310461SAndreas.Sandberg@ARM.com pmu->setMiscReg(misc_reg, newVal); 15147583SAli.Saidi@arm.com break; 151510461SAndreas.Sandberg@ARM.com 151610461SAndreas.Sandberg@ARM.com 151710037SARM gem5 Developers case MISCREG_HSTR: // TJDBX, now redifined to be RES0 151810037SARM gem5 Developers { 151910037SARM gem5 Developers HSTR hstrMask = 0; 152010037SARM gem5 Developers hstrMask.tjdbx = 1; 152110037SARM gem5 Developers newVal &= ~((uint32_t) hstrMask); 152210037SARM gem5 Developers break; 152310037SARM gem5 Developers } 152410037SARM gem5 Developers case MISCREG_HCPTR: 152510037SARM gem5 Developers { 152610037SARM gem5 Developers // If a CP bit in NSACR is 0 then the corresponding bit in 152710037SARM gem5 Developers // HCPTR is RAO/WI. Same applies to NSASEDIS 152810037SARM gem5 Developers secure_lookup = haveSecurity && 152910037SARM gem5 Developers inSecureState(readMiscRegNoEffect(MISCREG_SCR), 153010037SARM gem5 Developers readMiscRegNoEffect(MISCREG_CPSR)); 153110037SARM gem5 Developers if (!secure_lookup) { 153210037SARM gem5 Developers MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR); 153310037SARM gem5 Developers MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF; 153410037SARM gem5 Developers newVal = (newVal & ~mask) | (oldValue & mask); 153510037SARM gem5 Developers } 153610037SARM gem5 Developers break; 153710037SARM gem5 Developers } 153810037SARM gem5 Developers case MISCREG_HDFAR: // alias for secure DFAR 153910037SARM gem5 Developers misc_reg = MISCREG_DFAR_S; 154010037SARM gem5 Developers break; 154110037SARM gem5 Developers case MISCREG_HIFAR: // alias for secure IFAR 154210037SARM gem5 Developers misc_reg = MISCREG_IFAR_S; 154310037SARM gem5 Developers break; 154410037SARM gem5 Developers case MISCREG_ATS1CPR: 154510037SARM gem5 Developers case MISCREG_ATS1CPW: 154610037SARM gem5 Developers case MISCREG_ATS1CUR: 154710037SARM gem5 Developers case MISCREG_ATS1CUW: 154810037SARM gem5 Developers case MISCREG_ATS12NSOPR: 154910037SARM gem5 Developers case MISCREG_ATS12NSOPW: 155010037SARM gem5 Developers case MISCREG_ATS12NSOUR: 155110037SARM gem5 Developers case MISCREG_ATS12NSOUW: 155210037SARM gem5 Developers case MISCREG_ATS1HR: 155310037SARM gem5 Developers case MISCREG_ATS1HW: 15547436Sdam.sunwoo@arm.com { 155511608Snikos.nikoleris@arm.com Request::Flags flags = 0; 155610037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 155710037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 15587436Sdam.sunwoo@arm.com Fault fault; 15597436Sdam.sunwoo@arm.com switch(misc_reg) { 156010037SARM gem5 Developers case MISCREG_ATS1CPR: 156110037SARM gem5 Developers flags = TLB::MustBeOne; 156210037SARM gem5 Developers tranType = TLB::S1CTran; 156310037SARM gem5 Developers mode = BaseTLB::Read; 156410037SARM gem5 Developers break; 156510037SARM gem5 Developers case MISCREG_ATS1CPW: 156610037SARM gem5 Developers flags = TLB::MustBeOne; 156710037SARM gem5 Developers tranType = TLB::S1CTran; 156810037SARM gem5 Developers mode = BaseTLB::Write; 156910037SARM gem5 Developers break; 157010037SARM gem5 Developers case MISCREG_ATS1CUR: 157110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 157210037SARM gem5 Developers tranType = TLB::S1CTran; 157310037SARM gem5 Developers mode = BaseTLB::Read; 157410037SARM gem5 Developers break; 157510037SARM gem5 Developers case MISCREG_ATS1CUW: 157610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 157710037SARM gem5 Developers tranType = TLB::S1CTran; 157810037SARM gem5 Developers mode = BaseTLB::Write; 157910037SARM gem5 Developers break; 158010037SARM gem5 Developers case MISCREG_ATS12NSOPR: 158110037SARM gem5 Developers if (!haveSecurity) 158210037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPR"); 158310037SARM gem5 Developers flags = TLB::MustBeOne; 158410037SARM gem5 Developers tranType = TLB::S1S2NsTran; 158510037SARM gem5 Developers mode = BaseTLB::Read; 158610037SARM gem5 Developers break; 158710037SARM gem5 Developers case MISCREG_ATS12NSOPW: 158810037SARM gem5 Developers if (!haveSecurity) 158910037SARM gem5 Developers panic("Security Extensions required for ATS12NSOPW"); 159010037SARM gem5 Developers flags = TLB::MustBeOne; 159110037SARM gem5 Developers tranType = TLB::S1S2NsTran; 159210037SARM gem5 Developers mode = BaseTLB::Write; 159310037SARM gem5 Developers break; 159410037SARM gem5 Developers case MISCREG_ATS12NSOUR: 159510037SARM gem5 Developers if (!haveSecurity) 159610037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUR"); 159710037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 159810037SARM gem5 Developers tranType = TLB::S1S2NsTran; 159910037SARM gem5 Developers mode = BaseTLB::Read; 160010037SARM gem5 Developers break; 160110037SARM gem5 Developers case MISCREG_ATS12NSOUW: 160210037SARM gem5 Developers if (!haveSecurity) 160310037SARM gem5 Developers panic("Security Extensions required for ATS12NSOUW"); 160410037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 160510037SARM gem5 Developers tranType = TLB::S1S2NsTran; 160610037SARM gem5 Developers mode = BaseTLB::Write; 160710037SARM gem5 Developers break; 160810037SARM gem5 Developers case MISCREG_ATS1HR: // only really useful from secure mode. 160910037SARM gem5 Developers flags = TLB::MustBeOne; 161010037SARM gem5 Developers tranType = TLB::HypMode; 161110037SARM gem5 Developers mode = BaseTLB::Read; 161210037SARM gem5 Developers break; 161310037SARM gem5 Developers case MISCREG_ATS1HW: 161410037SARM gem5 Developers flags = TLB::MustBeOne; 161510037SARM gem5 Developers tranType = TLB::HypMode; 161610037SARM gem5 Developers mode = BaseTLB::Write; 161710037SARM gem5 Developers break; 16187436Sdam.sunwoo@arm.com } 161910037SARM gem5 Developers // If we're in timing mode then doing the translation in 162010037SARM gem5 Developers // functional mode then we're slightly distorting performance 162110037SARM gem5 Developers // results obtained from simulations. The translation should be 162210037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 162310037SARM gem5 Developers // can't be an atomic translation because that causes problems 162410037SARM gem5 Developers // with unexpected atomic snoop requests. 162510037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 162612749Sgiacomo.travaglini@arm.com 162712749Sgiacomo.travaglini@arm.com auto req = std::make_shared<Request>( 162812749Sgiacomo.travaglini@arm.com 0, val, 0, flags, Request::funcMasterId, 162912749Sgiacomo.travaglini@arm.com tc->pcState().pc(), tc->contextId()); 163012749Sgiacomo.travaglini@arm.com 163112406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional( 163212749Sgiacomo.travaglini@arm.com req, tc, mode, tranType); 163312749Sgiacomo.travaglini@arm.com 163410037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 163510037SARM gem5 Developers HCR hcr = readMiscRegNoEffect(MISCREG_HCR); 163610037SARM gem5 Developers 163710037SARM gem5 Developers MiscReg newVal; 16387436Sdam.sunwoo@arm.com if (fault == NoFault) { 163912749Sgiacomo.travaglini@arm.com Addr paddr = req->getPaddr(); 164010037SARM gem5 Developers if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode || 164110037SARM gem5 Developers ((tranType & TLB::S1S2NsTran) && hcr.vm) )) { 164210037SARM gem5 Developers newVal = (paddr & mask(39, 12)) | 164312406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 164410037SARM gem5 Developers } else { 164510037SARM gem5 Developers newVal = (paddr & 0xfffff000) | 164612406Sgabeblack@google.com (getDTBPtr(tc)->getAttr()); 164710037SARM gem5 Developers } 16487436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 16497436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 165010037SARM gem5 Developers val, newVal); 165110037SARM gem5 Developers } else { 165212524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 165312570Sgiacomo.travaglini@arm.com armFault->update(tc); 165410037SARM gem5 Developers // Set fault bit and FSR 165510037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 165610037SARM gem5 Developers 165710037SARM gem5 Developers newVal = ((fsr >> 9) & 1) << 11; 165810037SARM gem5 Developers if (newVal) { 165910037SARM gem5 Developers // LPAE - rearange fault status 166010037SARM gem5 Developers newVal |= ((fsr >> 0) & 0x3f) << 1; 166110037SARM gem5 Developers } else { 166210037SARM gem5 Developers // VMSA - rearange fault status 166310037SARM gem5 Developers newVal |= ((fsr >> 0) & 0xf) << 1; 166410037SARM gem5 Developers newVal |= ((fsr >> 10) & 0x1) << 5; 166510037SARM gem5 Developers newVal |= ((fsr >> 12) & 0x1) << 6; 166610037SARM gem5 Developers } 166710037SARM gem5 Developers newVal |= 0x1; // F bit 166810037SARM gem5 Developers newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 166910037SARM gem5 Developers newVal |= armFault->isStage2() ? 0x200 : 0; 167010037SARM gem5 Developers DPRINTF(MiscRegs, 167110037SARM gem5 Developers "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n", 167210037SARM gem5 Developers val, fsr, newVal); 16737436Sdam.sunwoo@arm.com } 167410037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR, newVal); 16757436Sdam.sunwoo@arm.com return; 16767436Sdam.sunwoo@arm.com } 167710037SARM gem5 Developers case MISCREG_TTBCR: 167810037SARM gem5 Developers { 167910037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 168010037SARM gem5 Developers const uint32_t ones = (uint32_t)(-1); 168110037SARM gem5 Developers TTBCR ttbcrMask = 0; 168210037SARM gem5 Developers TTBCR ttbcrNew = newVal; 168310037SARM gem5 Developers 168410037SARM gem5 Developers // ARM DDI 0406C.b, ARMv7-32 168510037SARM gem5 Developers ttbcrMask.n = ones; // T0SZ 168610037SARM gem5 Developers if (haveSecurity) { 168710037SARM gem5 Developers ttbcrMask.pd0 = ones; 168810037SARM gem5 Developers ttbcrMask.pd1 = ones; 168910037SARM gem5 Developers } 169010037SARM gem5 Developers ttbcrMask.epd0 = ones; 169110037SARM gem5 Developers ttbcrMask.irgn0 = ones; 169210037SARM gem5 Developers ttbcrMask.orgn0 = ones; 169310037SARM gem5 Developers ttbcrMask.sh0 = ones; 169410037SARM gem5 Developers ttbcrMask.ps = ones; // T1SZ 169510037SARM gem5 Developers ttbcrMask.a1 = ones; 169610037SARM gem5 Developers ttbcrMask.epd1 = ones; 169710037SARM gem5 Developers ttbcrMask.irgn1 = ones; 169810037SARM gem5 Developers ttbcrMask.orgn1 = ones; 169910037SARM gem5 Developers ttbcrMask.sh1 = ones; 170010037SARM gem5 Developers if (haveLPAE) 170110037SARM gem5 Developers ttbcrMask.eae = ones; 170210037SARM gem5 Developers 170310037SARM gem5 Developers if (haveLPAE && ttbcrNew.eae) { 170410037SARM gem5 Developers newVal = newVal & ttbcrMask; 170510037SARM gem5 Developers } else { 170610037SARM gem5 Developers newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask)); 170710037SARM gem5 Developers } 170812666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 170912666Sgiacomo.travaglini@arm.com getITBPtr(tc)->invalidateMiscReg(); 171012666Sgiacomo.travaglini@arm.com getDTBPtr(tc)->invalidateMiscReg(); 171112666Sgiacomo.travaglini@arm.com break; 171210037SARM gem5 Developers } 171310037SARM gem5 Developers case MISCREG_TTBR0: 171410037SARM gem5 Developers case MISCREG_TTBR1: 171510037SARM gem5 Developers { 171610037SARM gem5 Developers TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR); 171710037SARM gem5 Developers if (haveLPAE) { 171810037SARM gem5 Developers if (ttbcr.eae) { 171910037SARM gem5 Developers // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP 172010037SARM gem5 Developers // ARMv8 AArch32 bit 63-56 only 172110037SARM gem5 Developers uint64_t ttbrMask = mask(63,56) | mask(47,40); 172210037SARM gem5 Developers newVal = (newVal & (~ttbrMask)); 172310037SARM gem5 Developers } 172410037SARM gem5 Developers } 172512666Sgiacomo.travaglini@arm.com // Invalidate TLB MiscReg 172612406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 172712406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 172812666Sgiacomo.travaglini@arm.com break; 172910508SAli.Saidi@ARM.com } 173012666Sgiacomo.travaglini@arm.com case MISCREG_SCTLR_EL1: 17317749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 17327749SAli.Saidi@ARM.com case MISCREG_PRRR: 17337749SAli.Saidi@ARM.com case MISCREG_NMRR: 173410037SARM gem5 Developers case MISCREG_MAIR0: 173510037SARM gem5 Developers case MISCREG_MAIR1: 17367749SAli.Saidi@ARM.com case MISCREG_DACR: 173710037SARM gem5 Developers case MISCREG_VTTBR: 173810037SARM gem5 Developers case MISCREG_SCR_EL3: 173911575SDylan.Johnson@ARM.com case MISCREG_HCR_EL2: 174010037SARM gem5 Developers case MISCREG_TCR_EL1: 174110037SARM gem5 Developers case MISCREG_TCR_EL2: 174210037SARM gem5 Developers case MISCREG_TCR_EL3: 174310508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL2: 174410508SAli.Saidi@ARM.com case MISCREG_SCTLR_EL3: 174511573SDylan.Johnson@ARM.com case MISCREG_HSCTLR: 174610037SARM gem5 Developers case MISCREG_TTBR0_EL1: 174710037SARM gem5 Developers case MISCREG_TTBR1_EL1: 174810037SARM gem5 Developers case MISCREG_TTBR0_EL2: 174912675Sgiacomo.travaglini@arm.com case MISCREG_TTBR1_EL2: 175010037SARM gem5 Developers case MISCREG_TTBR0_EL3: 175112406Sgabeblack@google.com getITBPtr(tc)->invalidateMiscReg(); 175212406Sgabeblack@google.com getDTBPtr(tc)->invalidateMiscReg(); 17537749SAli.Saidi@ARM.com break; 175410037SARM gem5 Developers case MISCREG_NZCV: 175510037SARM gem5 Developers { 175610037SARM gem5 Developers CPSR cpsr = val; 175710037SARM gem5 Developers 175810338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_NZ, cpsr.nz); 175910338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_C, cpsr.c); 176010338SCurtis.Dunham@arm.com tc->setCCReg(CCREG_V, cpsr.v); 176110037SARM gem5 Developers } 176210037SARM gem5 Developers break; 176310037SARM gem5 Developers case MISCREG_DAIF: 176410037SARM gem5 Developers { 176510037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 176610037SARM gem5 Developers cpsr.daif = (uint8_t) ((CPSR) newVal).daif; 176710037SARM gem5 Developers newVal = cpsr; 176810037SARM gem5 Developers misc_reg = MISCREG_CPSR; 176910037SARM gem5 Developers } 177010037SARM gem5 Developers break; 177110037SARM gem5 Developers case MISCREG_SP_EL0: 177210037SARM gem5 Developers tc->setIntReg(INTREG_SP0, newVal); 177310037SARM gem5 Developers break; 177410037SARM gem5 Developers case MISCREG_SP_EL1: 177510037SARM gem5 Developers tc->setIntReg(INTREG_SP1, newVal); 177610037SARM gem5 Developers break; 177710037SARM gem5 Developers case MISCREG_SP_EL2: 177810037SARM gem5 Developers tc->setIntReg(INTREG_SP2, newVal); 177910037SARM gem5 Developers break; 178010037SARM gem5 Developers case MISCREG_SPSEL: 178110037SARM gem5 Developers { 178210037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 178310037SARM gem5 Developers cpsr.sp = (uint8_t) ((CPSR) newVal).sp; 178410037SARM gem5 Developers newVal = cpsr; 178510037SARM gem5 Developers misc_reg = MISCREG_CPSR; 178610037SARM gem5 Developers } 178710037SARM gem5 Developers break; 178810037SARM gem5 Developers case MISCREG_CURRENTEL: 178910037SARM gem5 Developers { 179010037SARM gem5 Developers CPSR cpsr = miscRegs[MISCREG_CPSR]; 179110037SARM gem5 Developers cpsr.el = (uint8_t) ((CPSR) newVal).el; 179210037SARM gem5 Developers newVal = cpsr; 179310037SARM gem5 Developers misc_reg = MISCREG_CPSR; 179410037SARM gem5 Developers } 179510037SARM gem5 Developers break; 179610037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 179710037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 179810037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 179910037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 180010037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 180110037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 180210037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 180310037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 180410037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 180510037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 180610037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 180710037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 180810037SARM gem5 Developers { 180912749Sgiacomo.travaglini@arm.com RequestPtr req = std::make_shared<Request>(); 181011608Snikos.nikoleris@arm.com Request::Flags flags = 0; 181110037SARM gem5 Developers BaseTLB::Mode mode = BaseTLB::Read; 181210037SARM gem5 Developers TLB::ArmTranslationType tranType = TLB::NormalTran; 181310037SARM gem5 Developers Fault fault; 181410037SARM gem5 Developers switch(misc_reg) { 181510037SARM gem5 Developers case MISCREG_AT_S1E1R_Xt: 181610037SARM gem5 Developers flags = TLB::MustBeOne; 181711577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 181810037SARM gem5 Developers mode = BaseTLB::Read; 181910037SARM gem5 Developers break; 182010037SARM gem5 Developers case MISCREG_AT_S1E1W_Xt: 182110037SARM gem5 Developers flags = TLB::MustBeOne; 182211577SDylan.Johnson@ARM.com tranType = TLB::S1E1Tran; 182310037SARM gem5 Developers mode = BaseTLB::Write; 182410037SARM gem5 Developers break; 182510037SARM gem5 Developers case MISCREG_AT_S1E0R_Xt: 182610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 182711577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 182810037SARM gem5 Developers mode = BaseTLB::Read; 182910037SARM gem5 Developers break; 183010037SARM gem5 Developers case MISCREG_AT_S1E0W_Xt: 183110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 183211577SDylan.Johnson@ARM.com tranType = TLB::S1E0Tran; 183310037SARM gem5 Developers mode = BaseTLB::Write; 183410037SARM gem5 Developers break; 183510037SARM gem5 Developers case MISCREG_AT_S1E2R_Xt: 183610037SARM gem5 Developers flags = TLB::MustBeOne; 183711577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 183810037SARM gem5 Developers mode = BaseTLB::Read; 183910037SARM gem5 Developers break; 184010037SARM gem5 Developers case MISCREG_AT_S1E2W_Xt: 184110037SARM gem5 Developers flags = TLB::MustBeOne; 184211577SDylan.Johnson@ARM.com tranType = TLB::S1E2Tran; 184310037SARM gem5 Developers mode = BaseTLB::Write; 184410037SARM gem5 Developers break; 184510037SARM gem5 Developers case MISCREG_AT_S12E0R_Xt: 184610037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 184711577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 184810037SARM gem5 Developers mode = BaseTLB::Read; 184910037SARM gem5 Developers break; 185010037SARM gem5 Developers case MISCREG_AT_S12E0W_Xt: 185110037SARM gem5 Developers flags = TLB::MustBeOne | TLB::UserMode; 185211577SDylan.Johnson@ARM.com tranType = TLB::S12E0Tran; 185310037SARM gem5 Developers mode = BaseTLB::Write; 185410037SARM gem5 Developers break; 185510037SARM gem5 Developers case MISCREG_AT_S12E1R_Xt: 185610037SARM gem5 Developers flags = TLB::MustBeOne; 185711577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 185810037SARM gem5 Developers mode = BaseTLB::Read; 185910037SARM gem5 Developers break; 186010037SARM gem5 Developers case MISCREG_AT_S12E1W_Xt: 186110037SARM gem5 Developers flags = TLB::MustBeOne; 186211577SDylan.Johnson@ARM.com tranType = TLB::S12E1Tran; 186310037SARM gem5 Developers mode = BaseTLB::Write; 186410037SARM gem5 Developers break; 186510037SARM gem5 Developers case MISCREG_AT_S1E3R_Xt: 186610037SARM gem5 Developers flags = TLB::MustBeOne; 186711577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 186810037SARM gem5 Developers mode = BaseTLB::Read; 186910037SARM gem5 Developers break; 187010037SARM gem5 Developers case MISCREG_AT_S1E3W_Xt: 187110037SARM gem5 Developers flags = TLB::MustBeOne; 187211577SDylan.Johnson@ARM.com tranType = TLB::S1E3Tran; 187310037SARM gem5 Developers mode = BaseTLB::Write; 187410037SARM gem5 Developers break; 187510037SARM gem5 Developers } 187610037SARM gem5 Developers // If we're in timing mode then doing the translation in 187710037SARM gem5 Developers // functional mode then we're slightly distorting performance 187810037SARM gem5 Developers // results obtained from simulations. The translation should be 187910037SARM gem5 Developers // done in the same mode the core is running in. NOTE: This 188010037SARM gem5 Developers // can't be an atomic translation because that causes problems 188110037SARM gem5 Developers // with unexpected atomic snoop requests. 188210037SARM gem5 Developers warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg); 188311560Sandreas.sandberg@arm.com req->setVirt(0, val, 0, flags, Request::funcMasterId, 188410037SARM gem5 Developers tc->pcState().pc()); 188511435Smitch.hayenga@arm.com req->setContext(tc->contextId()); 188612406Sgabeblack@google.com fault = getDTBPtr(tc)->translateFunctional(req, tc, mode, 188712406Sgabeblack@google.com tranType); 188810037SARM gem5 Developers 188910037SARM gem5 Developers MiscReg newVal; 189010037SARM gem5 Developers if (fault == NoFault) { 189110037SARM gem5 Developers Addr paddr = req->getPaddr(); 189212406Sgabeblack@google.com uint64_t attr = getDTBPtr(tc)->getAttr(); 189310037SARM gem5 Developers uint64_t attr1 = attr >> 56; 189410037SARM gem5 Developers if (!attr1 || attr1 ==0x44) { 189510037SARM gem5 Developers attr |= 0x100; 189610037SARM gem5 Developers attr &= ~ uint64_t(0x80); 189710037SARM gem5 Developers } 189810037SARM gem5 Developers newVal = (paddr & mask(47, 12)) | attr; 189910037SARM gem5 Developers DPRINTF(MiscRegs, 190010037SARM gem5 Developers "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n", 190110037SARM gem5 Developers val, newVal); 190210037SARM gem5 Developers } else { 190312524Sgiacomo.travaglini@arm.com ArmFault *armFault = static_cast<ArmFault *>(fault.get()); 190412570Sgiacomo.travaglini@arm.com armFault->update(tc); 190510037SARM gem5 Developers // Set fault bit and FSR 190610037SARM gem5 Developers FSR fsr = armFault->getFsr(tc); 190710037SARM gem5 Developers 190811577SDylan.Johnson@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 190911577SDylan.Johnson@ARM.com if (cpsr.width) { // AArch32 191011577SDylan.Johnson@ARM.com newVal = ((fsr >> 9) & 1) << 11; 191111577SDylan.Johnson@ARM.com // rearrange fault status 191211577SDylan.Johnson@ARM.com newVal |= ((fsr >> 0) & 0x3f) << 1; 191311577SDylan.Johnson@ARM.com newVal |= 0x1; // F bit 191411577SDylan.Johnson@ARM.com newVal |= ((armFault->iss() >> 7) & 0x1) << 8; 191511577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 0x200 : 0; 191611577SDylan.Johnson@ARM.com } else { // AArch64 191711577SDylan.Johnson@ARM.com newVal = 1; // F bit 191811577SDylan.Johnson@ARM.com newVal |= fsr << 1; // FST 191911577SDylan.Johnson@ARM.com // TODO: DDI 0487A.f D7-2083, AbortFault's s1ptw bit. 192011577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 8 : 0; // PTW 192111577SDylan.Johnson@ARM.com newVal |= armFault->isStage2() ? 1 << 9 : 0; // S 192211577SDylan.Johnson@ARM.com newVal |= 1 << 11; // RES1 192311577SDylan.Johnson@ARM.com } 192410037SARM gem5 Developers DPRINTF(MiscRegs, 192510037SARM gem5 Developers "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n", 192610037SARM gem5 Developers val, fsr, newVal); 192710037SARM gem5 Developers } 192810037SARM gem5 Developers setMiscRegNoEffect(MISCREG_PAR_EL1, newVal); 192910037SARM gem5 Developers return; 193010037SARM gem5 Developers } 193110037SARM gem5 Developers case MISCREG_SPSR_EL3: 193210037SARM gem5 Developers case MISCREG_SPSR_EL2: 193310037SARM gem5 Developers case MISCREG_SPSR_EL1: 193410037SARM gem5 Developers // Force bits 23:21 to 0 193510037SARM gem5 Developers newVal = val & ~(0x7 << 21); 193610037SARM gem5 Developers break; 19378549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 19388549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 19398549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 194010037SARM gem5 Developers break; 194110037SARM gem5 Developers 194210037SARM gem5 Developers // Generic Timer registers 194312816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CTL_EL2: 194412816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_CVAL_EL2: 194512816Sgiacomo.travaglini@arm.com case MISCREG_CNTHV_TVAL_EL2: 194610844Sandreas.sandberg@arm.com case MISCREG_CNTFRQ ... MISCREG_CNTHP_CTL: 194710844Sandreas.sandberg@arm.com case MISCREG_CNTPCT ... MISCREG_CNTHP_CVAL: 194810844Sandreas.sandberg@arm.com case MISCREG_CNTKCTL_EL1 ... MISCREG_CNTV_CVAL_EL0: 194910844Sandreas.sandberg@arm.com case MISCREG_CNTVOFF_EL2 ... MISCREG_CNTPS_CVAL_EL1: 195010844Sandreas.sandberg@arm.com getGenericTimer(tc).setMiscReg(misc_reg, newVal); 195110037SARM gem5 Developers break; 19527405SAli.Saidi@ARM.com } 19537405SAli.Saidi@ARM.com } 19547405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 19557405SAli.Saidi@ARM.com} 19567405SAli.Saidi@ARM.com 195710844Sandreas.sandberg@arm.comBaseISADevice & 195810844Sandreas.sandberg@arm.comISA::getGenericTimer(ThreadContext *tc) 195910037SARM gem5 Developers{ 196010844Sandreas.sandberg@arm.com // We only need to create an ISA interface the first time we try 196110844Sandreas.sandberg@arm.com // to access the timer. 196210844Sandreas.sandberg@arm.com if (timer) 196310844Sandreas.sandberg@arm.com return *timer.get(); 196410844Sandreas.sandberg@arm.com 196510844Sandreas.sandberg@arm.com assert(system); 196610844Sandreas.sandberg@arm.com GenericTimer *generic_timer(system->getGenericTimer()); 196710844Sandreas.sandberg@arm.com if (!generic_timer) { 196810844Sandreas.sandberg@arm.com panic("Trying to get a generic timer from a system that hasn't " 196910844Sandreas.sandberg@arm.com "been configured to use a generic timer.\n"); 197010037SARM gem5 Developers } 197110037SARM gem5 Developers 197211150Smitch.hayenga@arm.com timer.reset(new GenericTimerISA(*generic_timer, tc->contextId())); 197312972Sandreas.sandberg@arm.com timer->setThreadContext(tc); 197412972Sandreas.sandberg@arm.com 197510844Sandreas.sandberg@arm.com return *timer.get(); 197610037SARM gem5 Developers} 197710037SARM gem5 Developers 19787405SAli.Saidi@ARM.com} 19799384SAndreas.Sandberg@arm.com 19809384SAndreas.Sandberg@arm.comArmISA::ISA * 19819384SAndreas.Sandberg@arm.comArmISAParams::create() 19829384SAndreas.Sandberg@arm.com{ 19839384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 19849384SAndreas.Sandberg@arm.com} 1985