isa.cc revision 10461
17405SAli.Saidi@ARM.com/*
210338SCurtis.Dunham@arm.com * Copyright (c) 2010-2014 ARM Limited
37405SAli.Saidi@ARM.com * All rights reserved
47405SAli.Saidi@ARM.com *
57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall
67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual
77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating
87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software
97405SAli.Saidi@ARM.com * licensed hereunder.  You may use the software subject to the license
107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated
117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software,
127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form.
137405SAli.Saidi@ARM.com *
147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without
157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are
167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright
177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer;
187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright
197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the
207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution;
217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its
227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from
237405SAli.Saidi@ARM.com * this software without specific prior written permission.
247405SAli.Saidi@ARM.com *
257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
367405SAli.Saidi@ARM.com *
377405SAli.Saidi@ARM.com * Authors: Gabe Black
387405SAli.Saidi@ARM.com *          Ali Saidi
397405SAli.Saidi@ARM.com */
407405SAli.Saidi@ARM.com
417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh"
4210461SAndreas.Sandberg@ARM.com#include "arch/arm/pmu.hh"
439050Schander.sudanthi@arm.com#include "arch/arm/system.hh"
448887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh"
4510461SAndreas.Sandberg@ARM.com#include "cpu/base.hh"
468232Snate@binkert.org#include "debug/Arm.hh"
478232Snate@binkert.org#include "debug/MiscRegs.hh"
489384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh"
497678Sgblack@eecs.umich.edu#include "sim/faults.hh"
508059SAli.Saidi@ARM.com#include "sim/stat_control.hh"
518284SAli.Saidi@ARM.com#include "sim/system.hh"
527405SAli.Saidi@ARM.com
537405SAli.Saidi@ARM.comnamespace ArmISA
547405SAli.Saidi@ARM.com{
557405SAli.Saidi@ARM.com
5610037SARM gem5 Developers
5710037SARM gem5 Developers/**
5810037SARM gem5 Developers * Some registers aliase with others, and therefore need to be translated.
5910037SARM gem5 Developers * For each entry:
6010037SARM gem5 Developers * The first value is the misc register that is to be looked up
6110037SARM gem5 Developers * the second value is the lower part of the translation
6210037SARM gem5 Developers * the third the upper part
6310037SARM gem5 Developers */
6410037SARM gem5 Developersconst struct ISA::MiscRegInitializerEntry
6510037SARM gem5 Developers    ISA::MiscRegSwitch[miscRegTranslateMax] = {
6610037SARM gem5 Developers    {MISCREG_CSSELR_EL1, {MISCREG_CSSELR, 0}},
6710037SARM gem5 Developers    {MISCREG_SCTLR_EL1, {MISCREG_SCTLR, 0}},
6810037SARM gem5 Developers    {MISCREG_SCTLR_EL2, {MISCREG_HSCTLR, 0}},
6910037SARM gem5 Developers    {MISCREG_ACTLR_EL1, {MISCREG_ACTLR, 0}},
7010037SARM gem5 Developers    {MISCREG_ACTLR_EL2, {MISCREG_HACTLR, 0}},
7110037SARM gem5 Developers    {MISCREG_CPACR_EL1, {MISCREG_CPACR, 0}},
7210037SARM gem5 Developers    {MISCREG_CPTR_EL2, {MISCREG_HCPTR, 0}},
7310037SARM gem5 Developers    {MISCREG_HCR_EL2, {MISCREG_HCR, 0}},
7410037SARM gem5 Developers    {MISCREG_MDCR_EL2, {MISCREG_HDCR, 0}},
7510037SARM gem5 Developers    {MISCREG_HSTR_EL2, {MISCREG_HSTR, 0}},
7610037SARM gem5 Developers    {MISCREG_HACR_EL2, {MISCREG_HACR, 0}},
7710037SARM gem5 Developers    {MISCREG_TTBR0_EL1, {MISCREG_TTBR0, 0}},
7810037SARM gem5 Developers    {MISCREG_TTBR1_EL1, {MISCREG_TTBR1, 0}},
7910037SARM gem5 Developers    {MISCREG_TTBR0_EL2, {MISCREG_HTTBR, 0}},
8010037SARM gem5 Developers    {MISCREG_VTTBR_EL2, {MISCREG_VTTBR, 0}},
8110037SARM gem5 Developers    {MISCREG_TCR_EL1, {MISCREG_TTBCR, 0}},
8210037SARM gem5 Developers    {MISCREG_TCR_EL2, {MISCREG_HTCR, 0}},
8310037SARM gem5 Developers    {MISCREG_VTCR_EL2, {MISCREG_VTCR, 0}},
8410037SARM gem5 Developers    {MISCREG_AFSR0_EL1, {MISCREG_ADFSR, 0}},
8510037SARM gem5 Developers    {MISCREG_AFSR1_EL1, {MISCREG_AIFSR, 0}},
8610037SARM gem5 Developers    {MISCREG_AFSR0_EL2, {MISCREG_HADFSR, 0}},
8710037SARM gem5 Developers    {MISCREG_AFSR1_EL2, {MISCREG_HAIFSR, 0}},
8810037SARM gem5 Developers    {MISCREG_ESR_EL2, {MISCREG_HSR, 0}},
8910037SARM gem5 Developers    {MISCREG_FAR_EL1, {MISCREG_DFAR, MISCREG_IFAR}},
9010037SARM gem5 Developers    {MISCREG_FAR_EL2, {MISCREG_HDFAR, MISCREG_HIFAR}},
9110037SARM gem5 Developers    {MISCREG_HPFAR_EL2, {MISCREG_HPFAR, 0}},
9210037SARM gem5 Developers    {MISCREG_PAR_EL1, {MISCREG_PAR, 0}},
9310037SARM gem5 Developers    {MISCREG_MAIR_EL1, {MISCREG_PRRR, MISCREG_NMRR}},
9410037SARM gem5 Developers    {MISCREG_MAIR_EL2, {MISCREG_HMAIR0, MISCREG_HMAIR1}},
9510037SARM gem5 Developers    {MISCREG_AMAIR_EL1, {MISCREG_AMAIR0, MISCREG_AMAIR1}},
9610037SARM gem5 Developers    {MISCREG_VBAR_EL1, {MISCREG_VBAR, 0}},
9710037SARM gem5 Developers    {MISCREG_VBAR_EL2, {MISCREG_HVBAR, 0}},
9810037SARM gem5 Developers    {MISCREG_CONTEXTIDR_EL1, {MISCREG_CONTEXTIDR, 0}},
9910037SARM gem5 Developers    {MISCREG_TPIDR_EL0, {MISCREG_TPIDRURW, 0}},
10010037SARM gem5 Developers    {MISCREG_TPIDRRO_EL0, {MISCREG_TPIDRURO, 0}},
10110037SARM gem5 Developers    {MISCREG_TPIDR_EL1, {MISCREG_TPIDRPRW, 0}},
10210037SARM gem5 Developers    {MISCREG_TPIDR_EL2, {MISCREG_HTPIDR, 0}},
10310037SARM gem5 Developers    {MISCREG_TEECR32_EL1, {MISCREG_TEECR, 0}},
10410037SARM gem5 Developers    {MISCREG_CNTFRQ_EL0, {MISCREG_CNTFRQ, 0}},
10510037SARM gem5 Developers    {MISCREG_CNTPCT_EL0, {MISCREG_CNTPCT, 0}},
10610037SARM gem5 Developers    {MISCREG_CNTVCT_EL0, {MISCREG_CNTVCT, 0}},
10710037SARM gem5 Developers    {MISCREG_CNTVOFF_EL2, {MISCREG_CNTVOFF, 0}},
10810037SARM gem5 Developers    {MISCREG_CNTKCTL_EL1, {MISCREG_CNTKCTL, 0}},
10910037SARM gem5 Developers    {MISCREG_CNTHCTL_EL2, {MISCREG_CNTHCTL, 0}},
11010037SARM gem5 Developers    {MISCREG_CNTP_TVAL_EL0, {MISCREG_CNTP_TVAL, 0}},
11110037SARM gem5 Developers    {MISCREG_CNTP_CTL_EL0, {MISCREG_CNTP_CTL, 0}},
11210037SARM gem5 Developers    {MISCREG_CNTP_CVAL_EL0, {MISCREG_CNTP_CVAL, 0}},
11310037SARM gem5 Developers    {MISCREG_CNTV_TVAL_EL0, {MISCREG_CNTV_TVAL, 0}},
11410037SARM gem5 Developers    {MISCREG_CNTV_CTL_EL0, {MISCREG_CNTV_CTL, 0}},
11510037SARM gem5 Developers    {MISCREG_CNTV_CVAL_EL0, {MISCREG_CNTV_CVAL, 0}},
11610037SARM gem5 Developers    {MISCREG_CNTHP_TVAL_EL2, {MISCREG_CNTHP_TVAL, 0}},
11710037SARM gem5 Developers    {MISCREG_CNTHP_CTL_EL2, {MISCREG_CNTHP_CTL, 0}},
11810037SARM gem5 Developers    {MISCREG_CNTHP_CVAL_EL2, {MISCREG_CNTHP_CVAL, 0}},
11910037SARM gem5 Developers    {MISCREG_DACR32_EL2, {MISCREG_DACR, 0}},
12010037SARM gem5 Developers    {MISCREG_IFSR32_EL2, {MISCREG_IFSR, 0}},
12110037SARM gem5 Developers    {MISCREG_TEEHBR32_EL1, {MISCREG_TEEHBR, 0}},
12210037SARM gem5 Developers    {MISCREG_SDER32_EL3, {MISCREG_SDER, 0}}
12310037SARM gem5 Developers};
12410037SARM gem5 Developers
12510037SARM gem5 Developers
1269384SAndreas.Sandberg@arm.comISA::ISA(Params *p)
12710461SAndreas.Sandberg@ARM.com    : SimObject(p),
12810461SAndreas.Sandberg@ARM.com      system(NULL),
12910461SAndreas.Sandberg@ARM.com      pmu(p->pmu),
13010461SAndreas.Sandberg@ARM.com      lookUpMiscReg(NUM_MISCREGS, {0,0})
1319384SAndreas.Sandberg@arm.com{
1329384SAndreas.Sandberg@arm.com    SCTLR sctlr;
1339384SAndreas.Sandberg@arm.com    sctlr = 0;
1349384SAndreas.Sandberg@arm.com    miscRegs[MISCREG_SCTLR_RST] = sctlr;
13510037SARM gem5 Developers
13610461SAndreas.Sandberg@ARM.com    // Hook up a dummy device if we haven't been configured with a
13710461SAndreas.Sandberg@ARM.com    // real PMU. By using a dummy device, we don't need to check that
13810461SAndreas.Sandberg@ARM.com    // the PMU exist every time we try to access a PMU register.
13910461SAndreas.Sandberg@ARM.com    if (!pmu)
14010461SAndreas.Sandberg@ARM.com        pmu = &dummyDevice;
14110461SAndreas.Sandberg@ARM.com
14210037SARM gem5 Developers    system = dynamic_cast<ArmSystem *>(p->system);
14310037SARM gem5 Developers    DPRINTFN("ISA system set to: %p %p\n", system, p->system);
14410037SARM gem5 Developers
14510037SARM gem5 Developers    // Cache system-level properties
14610037SARM gem5 Developers    if (FullSystem && system) {
14710037SARM gem5 Developers        haveSecurity = system->haveSecurity();
14810037SARM gem5 Developers        haveLPAE = system->haveLPAE();
14910037SARM gem5 Developers        haveVirtualization = system->haveVirtualization();
15010037SARM gem5 Developers        haveLargeAsid64 = system->haveLargeAsid64();
15110037SARM gem5 Developers        physAddrRange64 = system->physAddrRange64();
15210037SARM gem5 Developers    } else {
15310037SARM gem5 Developers        haveSecurity = haveLPAE = haveVirtualization = false;
15410037SARM gem5 Developers        haveLargeAsid64 = false;
15510037SARM gem5 Developers        physAddrRange64 = 32;  // dummy value
15610037SARM gem5 Developers    }
15710037SARM gem5 Developers
15810037SARM gem5 Developers    /** Fill in the miscReg translation table */
15910037SARM gem5 Developers    for (uint32_t i = 0; i < miscRegTranslateMax; i++) {
16010037SARM gem5 Developers        struct MiscRegLUTEntry new_entry;
16110037SARM gem5 Developers
16210037SARM gem5 Developers        uint32_t select = MiscRegSwitch[i].index;
16310037SARM gem5 Developers        new_entry = MiscRegSwitch[i].entry;
16410037SARM gem5 Developers
16510037SARM gem5 Developers        lookUpMiscReg[select] = new_entry;
16610037SARM gem5 Developers    }
16710037SARM gem5 Developers
16810037SARM gem5 Developers    preUnflattenMiscReg();
16910037SARM gem5 Developers
1709384SAndreas.Sandberg@arm.com    clear();
1719384SAndreas.Sandberg@arm.com}
1729384SAndreas.Sandberg@arm.com
1739384SAndreas.Sandberg@arm.comconst ArmISAParams *
1749384SAndreas.Sandberg@arm.comISA::params() const
1759384SAndreas.Sandberg@arm.com{
1769384SAndreas.Sandberg@arm.com    return dynamic_cast<const Params *>(_params);
1779384SAndreas.Sandberg@arm.com}
1789384SAndreas.Sandberg@arm.com
1797427Sgblack@eecs.umich.eduvoid
1807427Sgblack@eecs.umich.eduISA::clear()
1817427Sgblack@eecs.umich.edu{
1829385SAndreas.Sandberg@arm.com    const Params *p(params());
1839385SAndreas.Sandberg@arm.com
1847427Sgblack@eecs.umich.edu    SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST];
1857427Sgblack@eecs.umich.edu    memset(miscRegs, 0, sizeof(miscRegs));
18610037SARM gem5 Developers
18710037SARM gem5 Developers    // Initialize configurable default values
18810037SARM gem5 Developers    miscRegs[MISCREG_MIDR] = p->midr;
18910037SARM gem5 Developers    miscRegs[MISCREG_MIDR_EL1] = p->midr;
19010037SARM gem5 Developers    miscRegs[MISCREG_VPIDR] = p->midr;
19110037SARM gem5 Developers
19210037SARM gem5 Developers    if (FullSystem && system->highestELIs64()) {
19310037SARM gem5 Developers        // Initialize AArch64 state
19410037SARM gem5 Developers        clear64(p);
19510037SARM gem5 Developers        return;
19610037SARM gem5 Developers    }
19710037SARM gem5 Developers
19810037SARM gem5 Developers    // Initialize AArch32 state...
19910037SARM gem5 Developers
2007427Sgblack@eecs.umich.edu    CPSR cpsr = 0;
2017427Sgblack@eecs.umich.edu    cpsr.mode = MODE_USER;
2027427Sgblack@eecs.umich.edu    miscRegs[MISCREG_CPSR] = cpsr;
2037427Sgblack@eecs.umich.edu    updateRegMap(cpsr);
2047427Sgblack@eecs.umich.edu
2057427Sgblack@eecs.umich.edu    SCTLR sctlr = 0;
20610037SARM gem5 Developers    sctlr.te = (bool) sctlr_rst.te;
20710037SARM gem5 Developers    sctlr.nmfi = (bool) sctlr_rst.nmfi;
20810037SARM gem5 Developers    sctlr.v = (bool) sctlr_rst.v;
20910037SARM gem5 Developers    sctlr.u = 1;
2107427Sgblack@eecs.umich.edu    sctlr.xp = 1;
2117427Sgblack@eecs.umich.edu    sctlr.rao2 = 1;
2127427Sgblack@eecs.umich.edu    sctlr.rao3 = 1;
21310037SARM gem5 Developers    sctlr.rao4 = 0xf;  // SCTLR[6:3]
21410204SAli.Saidi@ARM.com    sctlr.uci = 1;
21510204SAli.Saidi@ARM.com    sctlr.dze = 1;
21610037SARM gem5 Developers    miscRegs[MISCREG_SCTLR_NS] = sctlr;
2177427Sgblack@eecs.umich.edu    miscRegs[MISCREG_SCTLR_RST] = sctlr_rst;
21810037SARM gem5 Developers    miscRegs[MISCREG_HCPTR] = 0;
2197427Sgblack@eecs.umich.edu
22010037SARM gem5 Developers    // Start with an event in the mailbox
2217427Sgblack@eecs.umich.edu    miscRegs[MISCREG_SEV_MAILBOX] = 1;
2227427Sgblack@eecs.umich.edu
22310037SARM gem5 Developers    // Separate Instruction and Data TLBs
2247427Sgblack@eecs.umich.edu    miscRegs[MISCREG_TLBTR] = 1;
2257427Sgblack@eecs.umich.edu
2267427Sgblack@eecs.umich.edu    MVFR0 mvfr0 = 0;
2277427Sgblack@eecs.umich.edu    mvfr0.advSimdRegisters = 2;
2287427Sgblack@eecs.umich.edu    mvfr0.singlePrecision = 2;
2297427Sgblack@eecs.umich.edu    mvfr0.doublePrecision = 2;
2307427Sgblack@eecs.umich.edu    mvfr0.vfpExceptionTrapping = 0;
2317427Sgblack@eecs.umich.edu    mvfr0.divide = 1;
2327427Sgblack@eecs.umich.edu    mvfr0.squareRoot = 1;
2337427Sgblack@eecs.umich.edu    mvfr0.shortVectors = 1;
2347427Sgblack@eecs.umich.edu    mvfr0.roundingModes = 1;
2357427Sgblack@eecs.umich.edu    miscRegs[MISCREG_MVFR0] = mvfr0;
2367427Sgblack@eecs.umich.edu
2377427Sgblack@eecs.umich.edu    MVFR1 mvfr1 = 0;
2387427Sgblack@eecs.umich.edu    mvfr1.flushToZero = 1;
2397427Sgblack@eecs.umich.edu    mvfr1.defaultNaN = 1;
2407427Sgblack@eecs.umich.edu    mvfr1.advSimdLoadStore = 1;
2417427Sgblack@eecs.umich.edu    mvfr1.advSimdInteger = 1;
2427427Sgblack@eecs.umich.edu    mvfr1.advSimdSinglePrecision = 1;
2437427Sgblack@eecs.umich.edu    mvfr1.advSimdHalfPrecision = 1;
2447427Sgblack@eecs.umich.edu    mvfr1.vfpHalfPrecision = 1;
2457427Sgblack@eecs.umich.edu    miscRegs[MISCREG_MVFR1] = mvfr1;
2467427Sgblack@eecs.umich.edu
2477436Sdam.sunwoo@arm.com    // Reset values of PRRR and NMRR are implementation dependent
2487436Sdam.sunwoo@arm.com
24910037SARM gem5 Developers    // @todo: PRRR and NMRR in secure state?
25010037SARM gem5 Developers    miscRegs[MISCREG_PRRR_NS] =
2517436Sdam.sunwoo@arm.com        (1 << 19) | // 19
2527436Sdam.sunwoo@arm.com        (0 << 18) | // 18
2537436Sdam.sunwoo@arm.com        (0 << 17) | // 17
2547436Sdam.sunwoo@arm.com        (1 << 16) | // 16
2557436Sdam.sunwoo@arm.com        (2 << 14) | // 15:14
2567436Sdam.sunwoo@arm.com        (0 << 12) | // 13:12
2577436Sdam.sunwoo@arm.com        (2 << 10) | // 11:10
2587436Sdam.sunwoo@arm.com        (2 << 8)  | // 9:8
2597436Sdam.sunwoo@arm.com        (2 << 6)  | // 7:6
2607436Sdam.sunwoo@arm.com        (2 << 4)  | // 5:4
2617436Sdam.sunwoo@arm.com        (1 << 2)  | // 3:2
2627436Sdam.sunwoo@arm.com        0;          // 1:0
26310037SARM gem5 Developers    miscRegs[MISCREG_NMRR_NS] =
2647436Sdam.sunwoo@arm.com        (1 << 30) | // 31:30
2657436Sdam.sunwoo@arm.com        (0 << 26) | // 27:26
2667436Sdam.sunwoo@arm.com        (0 << 24) | // 25:24
2677436Sdam.sunwoo@arm.com        (3 << 22) | // 23:22
2687436Sdam.sunwoo@arm.com        (2 << 20) | // 21:20
2697436Sdam.sunwoo@arm.com        (0 << 18) | // 19:18
2707436Sdam.sunwoo@arm.com        (0 << 16) | // 17:16
2717436Sdam.sunwoo@arm.com        (1 << 14) | // 15:14
2727436Sdam.sunwoo@arm.com        (0 << 12) | // 13:12
2737436Sdam.sunwoo@arm.com        (2 << 10) | // 11:10
2747436Sdam.sunwoo@arm.com        (0 << 8)  | // 9:8
2757436Sdam.sunwoo@arm.com        (3 << 6)  | // 7:6
2767436Sdam.sunwoo@arm.com        (2 << 4)  | // 5:4
2777436Sdam.sunwoo@arm.com        (0 << 2)  | // 3:2
2787436Sdam.sunwoo@arm.com        0;          // 1:0
2797436Sdam.sunwoo@arm.com
2807644Sali.saidi@arm.com    miscRegs[MISCREG_CPACR] = 0;
2818147SAli.Saidi@ARM.com
2829385SAndreas.Sandberg@arm.com
2839385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_PFR0] = p->id_pfr0;
2849385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_PFR1] = p->id_pfr1;
2859385SAndreas.Sandberg@arm.com
2869385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0;
2879385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1;
2889385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2;
2899385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3;
2909385SAndreas.Sandberg@arm.com
2919385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR0] = p->id_isar0;
2929385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR1] = p->id_isar1;
2939385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR2] = p->id_isar2;
2949385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR3] = p->id_isar3;
2959385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR4] = p->id_isar4;
2969385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_ID_ISAR5] = p->id_isar5;
2979385SAndreas.Sandberg@arm.com
2989385SAndreas.Sandberg@arm.com    miscRegs[MISCREG_FPSID] = p->fpsid;
2999385SAndreas.Sandberg@arm.com
30010037SARM gem5 Developers    if (haveLPAE) {
30110037SARM gem5 Developers        TTBCR ttbcr = miscRegs[MISCREG_TTBCR_NS];
30210037SARM gem5 Developers        ttbcr.eae = 0;
30310037SARM gem5 Developers        miscRegs[MISCREG_TTBCR_NS] = ttbcr;
30410037SARM gem5 Developers        // Enforce consistency with system-level settings
30510037SARM gem5 Developers        miscRegs[MISCREG_ID_MMFR0] = (miscRegs[MISCREG_ID_MMFR0] & ~0xf) | 0x5;
30610037SARM gem5 Developers    }
30710037SARM gem5 Developers
30810037SARM gem5 Developers    if (haveSecurity) {
30910037SARM gem5 Developers        miscRegs[MISCREG_SCTLR_S] = sctlr;
31010037SARM gem5 Developers        miscRegs[MISCREG_SCR] = 0;
31110037SARM gem5 Developers        miscRegs[MISCREG_VBAR_S] = 0;
31210037SARM gem5 Developers    } else {
31310037SARM gem5 Developers        // we're always non-secure
31410037SARM gem5 Developers        miscRegs[MISCREG_SCR] = 1;
31510037SARM gem5 Developers    }
3168147SAli.Saidi@ARM.com
3177427Sgblack@eecs.umich.edu    //XXX We need to initialize the rest of the state.
3187427Sgblack@eecs.umich.edu}
3197427Sgblack@eecs.umich.edu
32010037SARM gem5 Developersvoid
32110037SARM gem5 DevelopersISA::clear64(const ArmISAParams *p)
32210037SARM gem5 Developers{
32310037SARM gem5 Developers    CPSR cpsr = 0;
32410037SARM gem5 Developers    Addr rvbar = system->resetAddr64();
32510037SARM gem5 Developers    switch (system->highestEL()) {
32610037SARM gem5 Developers        // Set initial EL to highest implemented EL using associated stack
32710037SARM gem5 Developers        // pointer (SP_ELx); set RVBAR_ELx to implementation defined reset
32810037SARM gem5 Developers        // value
32910037SARM gem5 Developers      case EL3:
33010037SARM gem5 Developers        cpsr.mode = MODE_EL3H;
33110037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL3] = rvbar;
33210037SARM gem5 Developers        break;
33310037SARM gem5 Developers      case EL2:
33410037SARM gem5 Developers        cpsr.mode = MODE_EL2H;
33510037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL2] = rvbar;
33610037SARM gem5 Developers        break;
33710037SARM gem5 Developers      case EL1:
33810037SARM gem5 Developers        cpsr.mode = MODE_EL1H;
33910037SARM gem5 Developers        miscRegs[MISCREG_RVBAR_EL1] = rvbar;
34010037SARM gem5 Developers        break;
34110037SARM gem5 Developers      default:
34210037SARM gem5 Developers        panic("Invalid highest implemented exception level");
34310037SARM gem5 Developers        break;
34410037SARM gem5 Developers    }
34510037SARM gem5 Developers
34610037SARM gem5 Developers    // Initialize rest of CPSR
34710037SARM gem5 Developers    cpsr.daif = 0xf;  // Mask all interrupts
34810037SARM gem5 Developers    cpsr.ss = 0;
34910037SARM gem5 Developers    cpsr.il = 0;
35010037SARM gem5 Developers    miscRegs[MISCREG_CPSR] = cpsr;
35110037SARM gem5 Developers    updateRegMap(cpsr);
35210037SARM gem5 Developers
35310037SARM gem5 Developers    // Initialize other control registers
35410037SARM gem5 Developers    miscRegs[MISCREG_MPIDR_EL1] = 0x80000000;
35510037SARM gem5 Developers    if (haveSecurity) {
35610037SARM gem5 Developers        miscRegs[MISCREG_SCTLR_EL3] = 0x30c50870;
35710037SARM gem5 Developers        miscRegs[MISCREG_SCR_EL3]   = 0x00000030;  // RES1 fields
35810037SARM gem5 Developers    // @todo: uncomment this to enable Virtualization
35910037SARM gem5 Developers    // } else if (haveVirtualization) {
36010037SARM gem5 Developers    //     miscRegs[MISCREG_SCTLR_EL2] = 0x30c50870;
36110037SARM gem5 Developers    } else {
36210037SARM gem5 Developers        miscRegs[MISCREG_SCTLR_EL1] = 0x30c50870;
36310037SARM gem5 Developers        // Always non-secure
36410037SARM gem5 Developers        miscRegs[MISCREG_SCR_EL3] = 1;
36510037SARM gem5 Developers    }
36610037SARM gem5 Developers
36710037SARM gem5 Developers    // Initialize configurable id registers
36810037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64AFR0_EL1] = p->id_aa64afr0_el1;
36910037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64AFR1_EL1] = p->id_aa64afr1_el1;
37010461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_AA64DFR0_EL1] =
37110461SAndreas.Sandberg@ARM.com        (p->id_aa64dfr0_el1 & 0xfffffffffffff0ffULL) |
37210461SAndreas.Sandberg@ARM.com        (p->pmu ?             0x0000000000000100ULL : 0); // Enable PMUv3
37310461SAndreas.Sandberg@ARM.com
37410037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64DFR1_EL1] = p->id_aa64dfr1_el1;
37510037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64ISAR0_EL1] = p->id_aa64isar0_el1;
37610037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64ISAR1_EL1] = p->id_aa64isar1_el1;
37710037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = p->id_aa64mmfr0_el1;
37810037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR1_EL1] = p->id_aa64mmfr1_el1;
37910037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR0_EL1] = p->id_aa64pfr0_el1;
38010037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR1_EL1] = p->id_aa64pfr1_el1;
38110037SARM gem5 Developers
38210461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_DFR0_EL1] =
38310461SAndreas.Sandberg@ARM.com        (p->pmu ? 0x03000000ULL : 0); // Enable PMUv3
38410461SAndreas.Sandberg@ARM.com
38510461SAndreas.Sandberg@ARM.com    miscRegs[MISCREG_ID_DFR0] = miscRegs[MISCREG_ID_DFR0_EL1];
38610461SAndreas.Sandberg@ARM.com
38710037SARM gem5 Developers    // Enforce consistency with system-level settings...
38810037SARM gem5 Developers
38910037SARM gem5 Developers    // EL3
39010037SARM gem5 Developers    // (no AArch32/64 interprocessing support for now)
39110037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
39210037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64PFR0_EL1], 15, 12,
39310037SARM gem5 Developers        haveSecurity ? 0x1 : 0x0);
39410037SARM gem5 Developers    // EL2
39510037SARM gem5 Developers    // (no AArch32/64 interprocessing support for now)
39610037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64PFR0_EL1] = insertBits(
39710037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64PFR0_EL1], 11, 8,
39810037SARM gem5 Developers        haveVirtualization ? 0x1 : 0x0);
39910037SARM gem5 Developers    // Large ASID support
40010037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
40110037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 7, 4,
40210037SARM gem5 Developers        haveLargeAsid64 ? 0x2 : 0x0);
40310037SARM gem5 Developers    // Physical address size
40410037SARM gem5 Developers    miscRegs[MISCREG_ID_AA64MMFR0_EL1] = insertBits(
40510037SARM gem5 Developers        miscRegs[MISCREG_ID_AA64MMFR0_EL1], 3, 0,
40610037SARM gem5 Developers        encodePhysAddrRange64(physAddrRange64));
40710037SARM gem5 Developers}
40810037SARM gem5 Developers
4097405SAli.Saidi@ARM.comMiscReg
41010035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const
4117405SAli.Saidi@ARM.com{
4127405SAli.Saidi@ARM.com    assert(misc_reg < NumMiscRegs);
4137614Sminkyu.jeong@arm.com
41410037SARM gem5 Developers    int flat_idx = flattenMiscIndex(misc_reg);  // Note: indexes of AArch64
41510037SARM gem5 Developers                                                // registers are left unchanged
41610037SARM gem5 Developers    MiscReg val;
4177614Sminkyu.jeong@arm.com
41810037SARM gem5 Developers    if (lookUpMiscReg[flat_idx].lower == 0 || flat_idx == MISCREG_SPSR
41910037SARM gem5 Developers            || flat_idx == MISCREG_SCTLR_EL1) {
42010037SARM gem5 Developers        if (flat_idx == MISCREG_SPSR)
42110037SARM gem5 Developers            flat_idx = flattenMiscIndex(MISCREG_SPSR);
42210037SARM gem5 Developers        if (flat_idx == MISCREG_SCTLR_EL1)
42310037SARM gem5 Developers            flat_idx = flattenMiscIndex(MISCREG_SCTLR);
42410037SARM gem5 Developers        val = miscRegs[flat_idx];
42510037SARM gem5 Developers    } else
42610037SARM gem5 Developers        if (lookUpMiscReg[flat_idx].upper > 0)
42710037SARM gem5 Developers            val = ((miscRegs[lookUpMiscReg[flat_idx].lower] & mask(32))
42810037SARM gem5 Developers                    | (miscRegs[lookUpMiscReg[flat_idx].upper] << 32));
42910037SARM gem5 Developers        else
43010037SARM gem5 Developers            val = miscRegs[lookUpMiscReg[flat_idx].lower];
43110037SARM gem5 Developers
4327614Sminkyu.jeong@arm.com    return val;
4337405SAli.Saidi@ARM.com}
4347405SAli.Saidi@ARM.com
4357405SAli.Saidi@ARM.com
4367405SAli.Saidi@ARM.comMiscReg
4377405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc)
4387405SAli.Saidi@ARM.com{
43910037SARM gem5 Developers    CPSR cpsr = 0;
44010037SARM gem5 Developers    PCState pc = 0;
44110037SARM gem5 Developers    SCR scr = 0;
4429050Schander.sudanthi@arm.com
4437405SAli.Saidi@ARM.com    if (misc_reg == MISCREG_CPSR) {
44410037SARM gem5 Developers        cpsr = miscRegs[misc_reg];
44510037SARM gem5 Developers        pc = tc->pcState();
4467720Sgblack@eecs.umich.edu        cpsr.j = pc.jazelle() ? 1 : 0;
4477720Sgblack@eecs.umich.edu        cpsr.t = pc.thumb() ? 1 : 0;
4487405SAli.Saidi@ARM.com        return cpsr;
4497405SAli.Saidi@ARM.com    }
4507757SAli.Saidi@ARM.com
45110037SARM gem5 Developers#ifndef NDEBUG
45210037SARM gem5 Developers    if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
45310037SARM gem5 Developers        if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
45410037SARM gem5 Developers            warn("Unimplemented system register %s read.\n",
45510037SARM gem5 Developers                 miscRegName[misc_reg]);
45610037SARM gem5 Developers        else
45710037SARM gem5 Developers            panic("Unimplemented system register %s read.\n",
45810037SARM gem5 Developers                  miscRegName[misc_reg]);
45910037SARM gem5 Developers    }
46010037SARM gem5 Developers#endif
46110037SARM gem5 Developers
46210037SARM gem5 Developers    switch (unflattenMiscReg(misc_reg)) {
46310037SARM gem5 Developers      case MISCREG_HCR:
46410037SARM gem5 Developers        {
46510037SARM gem5 Developers            if (!haveVirtualization)
46610037SARM gem5 Developers                return 0;
46710037SARM gem5 Developers            else
46810037SARM gem5 Developers                return readMiscRegNoEffect(MISCREG_HCR);
46910037SARM gem5 Developers        }
47010037SARM gem5 Developers      case MISCREG_CPACR:
47110037SARM gem5 Developers        {
47210037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
47310037SARM gem5 Developers            CPACR cpacrMask = 0;
47410037SARM gem5 Developers            // Only cp10, cp11, and ase are implemented, nothing else should
47510037SARM gem5 Developers            // be readable? (straight copy from the write code)
47610037SARM gem5 Developers            cpacrMask.cp10 = ones;
47710037SARM gem5 Developers            cpacrMask.cp11 = ones;
47810037SARM gem5 Developers            cpacrMask.asedis = ones;
47910037SARM gem5 Developers
48010037SARM gem5 Developers            // Security Extensions may limit the readability of CPACR
48110037SARM gem5 Developers            if (haveSecurity) {
48210037SARM gem5 Developers                scr = readMiscRegNoEffect(MISCREG_SCR);
48310037SARM gem5 Developers                cpsr = readMiscRegNoEffect(MISCREG_CPSR);
48410037SARM gem5 Developers                if (scr.ns && (cpsr.mode != MODE_MON)) {
48510037SARM gem5 Developers                    NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
48610037SARM gem5 Developers                    // NB: Skipping the full loop, here
48710037SARM gem5 Developers                    if (!nsacr.cp10) cpacrMask.cp10 = 0;
48810037SARM gem5 Developers                    if (!nsacr.cp11) cpacrMask.cp11 = 0;
48910037SARM gem5 Developers                }
49010037SARM gem5 Developers            }
49110037SARM gem5 Developers            MiscReg val = readMiscRegNoEffect(MISCREG_CPACR);
49210037SARM gem5 Developers            val &= cpacrMask;
49310037SARM gem5 Developers            DPRINTF(MiscRegs, "Reading misc reg %s: %#x\n",
49410037SARM gem5 Developers                    miscRegName[misc_reg], val);
49510037SARM gem5 Developers            return val;
49610037SARM gem5 Developers        }
4978284SAli.Saidi@ARM.com      case MISCREG_MPIDR:
49810037SARM gem5 Developers        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
49910037SARM gem5 Developers        scr  = readMiscRegNoEffect(MISCREG_SCR);
50010037SARM gem5 Developers        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
50110037SARM gem5 Developers            return getMPIDR(system, tc);
5029050Schander.sudanthi@arm.com        } else {
50310037SARM gem5 Developers            return readMiscReg(MISCREG_VMPIDR, tc);
50410037SARM gem5 Developers        }
50510037SARM gem5 Developers            break;
50610037SARM gem5 Developers      case MISCREG_MPIDR_EL1:
50710037SARM gem5 Developers        // @todo in the absence of v8 virtualization support just return MPIDR_EL1
50810037SARM gem5 Developers        return getMPIDR(system, tc) & 0xffffffff;
50910037SARM gem5 Developers      case MISCREG_VMPIDR:
51010037SARM gem5 Developers        // top bit defined as RES1
51110037SARM gem5 Developers        return readMiscRegNoEffect(misc_reg) | 0x80000000;
51210037SARM gem5 Developers      case MISCREG_ID_AFR0: // not implemented, so alias MIDR
51310037SARM gem5 Developers      case MISCREG_REVIDR:  // not implemented, so alias MIDR
51410037SARM gem5 Developers      case MISCREG_MIDR:
51510037SARM gem5 Developers        cpsr = readMiscRegNoEffect(MISCREG_CPSR);
51610037SARM gem5 Developers        scr  = readMiscRegNoEffect(MISCREG_SCR);
51710037SARM gem5 Developers        if ((cpsr.mode == MODE_HYP) || inSecureState(scr, cpsr)) {
51810037SARM gem5 Developers            return readMiscRegNoEffect(misc_reg);
51910037SARM gem5 Developers        } else {
52010037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_VPIDR);
5219050Schander.sudanthi@arm.com        }
5228284SAli.Saidi@ARM.com        break;
52310037SARM gem5 Developers      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
52410037SARM gem5 Developers      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
52510037SARM gem5 Developers      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
52610037SARM gem5 Developers      case MISCREG_AIDR:  // AUX ID set to 0
52710037SARM gem5 Developers      case MISCREG_TCMTR: // No TCM's
52810037SARM gem5 Developers        return 0;
52910037SARM gem5 Developers
5307405SAli.Saidi@ARM.com      case MISCREG_CLIDR:
5317731SAli.Saidi@ARM.com        warn_once("The clidr register always reports 0 caches.\n");
5328468Swade.walker@arm.com        warn_once("clidr LoUIS field of 0b001 to match current "
5338468Swade.walker@arm.com                  "ARM implementations.\n");
5348468Swade.walker@arm.com        return 0x00200000;
5357405SAli.Saidi@ARM.com      case MISCREG_CCSIDR:
5367731SAli.Saidi@ARM.com        warn_once("The ccsidr register isn't implemented and "
5377405SAli.Saidi@ARM.com                "always reads as 0.\n");
5387405SAli.Saidi@ARM.com        break;
5397583SAli.Saidi@arm.com      case MISCREG_CTR:
5409130Satgutier@umich.edu        {
5419130Satgutier@umich.edu            //all caches have the same line size in gem5
5429130Satgutier@umich.edu            //4 byte words in ARM
5439130Satgutier@umich.edu            unsigned lineSizeWords =
5449814Sandreas.hansson@arm.com                tc->getSystemPtr()->cacheLineSize() / 4;
5459130Satgutier@umich.edu            unsigned log2LineSizeWords = 0;
5469130Satgutier@umich.edu
5479130Satgutier@umich.edu            while (lineSizeWords >>= 1) {
5489130Satgutier@umich.edu                ++log2LineSizeWords;
5499130Satgutier@umich.edu            }
5509130Satgutier@umich.edu
5519130Satgutier@umich.edu            CTR ctr = 0;
5529130Satgutier@umich.edu            //log2 of minimun i-cache line size (words)
5539130Satgutier@umich.edu            ctr.iCacheLineSize = log2LineSizeWords;
5549130Satgutier@umich.edu            //b11 - gem5 uses pipt
5559130Satgutier@umich.edu            ctr.l1IndexPolicy = 0x3;
5569130Satgutier@umich.edu            //log2 of minimum d-cache line size (words)
5579130Satgutier@umich.edu            ctr.dCacheLineSize = log2LineSizeWords;
5589130Satgutier@umich.edu            //log2 of max reservation size (words)
5599130Satgutier@umich.edu            ctr.erg = log2LineSizeWords;
5609130Satgutier@umich.edu            //log2 of max writeback size (words)
5619130Satgutier@umich.edu            ctr.cwg = log2LineSizeWords;
5629130Satgutier@umich.edu            //b100 - gem5 format is ARMv7
5639130Satgutier@umich.edu            ctr.format = 0x4;
5649130Satgutier@umich.edu
5659130Satgutier@umich.edu            return ctr;
5669130Satgutier@umich.edu        }
5677583SAli.Saidi@arm.com      case MISCREG_ACTLR:
5687583SAli.Saidi@arm.com        warn("Not doing anything for miscreg ACTLR\n");
5697583SAli.Saidi@arm.com        break;
57010461SAndreas.Sandberg@ARM.com
57110461SAndreas.Sandberg@ARM.com      case MISCREG_PMXEVTYPER_PMCCFILTR:
57210461SAndreas.Sandberg@ARM.com      case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
57310461SAndreas.Sandberg@ARM.com      case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
57410461SAndreas.Sandberg@ARM.com      case MISCREG_PMCR ... MISCREG_PMOVSSET:
57510461SAndreas.Sandberg@ARM.com        return pmu->readMiscReg(misc_reg);
57610461SAndreas.Sandberg@ARM.com
5778302SAli.Saidi@ARM.com      case MISCREG_CPSR_Q:
5788302SAli.Saidi@ARM.com        panic("shouldn't be reading this register seperately\n");
5797783SGiacomo.Gabrielli@arm.com      case MISCREG_FPSCR_QC:
5807783SGiacomo.Gabrielli@arm.com        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask;
5817783SGiacomo.Gabrielli@arm.com      case MISCREG_FPSCR_EXC:
5827783SGiacomo.Gabrielli@arm.com        return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask;
58310037SARM gem5 Developers      case MISCREG_FPSR:
58410037SARM gem5 Developers        {
58510037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
58610037SARM gem5 Developers            FPSCR fpscrMask = 0;
58710037SARM gem5 Developers            fpscrMask.ioc = ones;
58810037SARM gem5 Developers            fpscrMask.dzc = ones;
58910037SARM gem5 Developers            fpscrMask.ofc = ones;
59010037SARM gem5 Developers            fpscrMask.ufc = ones;
59110037SARM gem5 Developers            fpscrMask.ixc = ones;
59210037SARM gem5 Developers            fpscrMask.idc = ones;
59310037SARM gem5 Developers            fpscrMask.qc = ones;
59410037SARM gem5 Developers            fpscrMask.v = ones;
59510037SARM gem5 Developers            fpscrMask.c = ones;
59610037SARM gem5 Developers            fpscrMask.z = ones;
59710037SARM gem5 Developers            fpscrMask.n = ones;
59810037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
59910037SARM gem5 Developers        }
60010037SARM gem5 Developers      case MISCREG_FPCR:
60110037SARM gem5 Developers        {
60210037SARM gem5 Developers            const uint32_t ones = (uint32_t)(-1);
60310037SARM gem5 Developers            FPSCR fpscrMask  = 0;
60410037SARM gem5 Developers            fpscrMask.ioe = ones;
60510037SARM gem5 Developers            fpscrMask.dze = ones;
60610037SARM gem5 Developers            fpscrMask.ofe = ones;
60710037SARM gem5 Developers            fpscrMask.ufe = ones;
60810037SARM gem5 Developers            fpscrMask.ixe = ones;
60910037SARM gem5 Developers            fpscrMask.ide = ones;
61010037SARM gem5 Developers            fpscrMask.len    = ones;
61110037SARM gem5 Developers            fpscrMask.stride = ones;
61210037SARM gem5 Developers            fpscrMask.rMode  = ones;
61310037SARM gem5 Developers            fpscrMask.fz     = ones;
61410037SARM gem5 Developers            fpscrMask.dn     = ones;
61510037SARM gem5 Developers            fpscrMask.ahp    = ones;
61610037SARM gem5 Developers            return readMiscRegNoEffect(MISCREG_FPSCR) & (uint32_t)fpscrMask;
61710037SARM gem5 Developers        }
61810037SARM gem5 Developers      case MISCREG_NZCV:
61910037SARM gem5 Developers        {
62010037SARM gem5 Developers            CPSR cpsr = 0;
62110338SCurtis.Dunham@arm.com            cpsr.nz   = tc->readCCReg(CCREG_NZ);
62210338SCurtis.Dunham@arm.com            cpsr.c    = tc->readCCReg(CCREG_C);
62310338SCurtis.Dunham@arm.com            cpsr.v    = tc->readCCReg(CCREG_V);
62410037SARM gem5 Developers            return cpsr;
62510037SARM gem5 Developers        }
62610037SARM gem5 Developers      case MISCREG_DAIF:
62710037SARM gem5 Developers        {
62810037SARM gem5 Developers            CPSR cpsr = 0;
62910037SARM gem5 Developers            cpsr.daif = (uint8_t) ((CPSR) miscRegs[MISCREG_CPSR]).daif;
63010037SARM gem5 Developers            return cpsr;
63110037SARM gem5 Developers        }
63210037SARM gem5 Developers      case MISCREG_SP_EL0:
63310037SARM gem5 Developers        {
63410037SARM gem5 Developers            return tc->readIntReg(INTREG_SP0);
63510037SARM gem5 Developers        }
63610037SARM gem5 Developers      case MISCREG_SP_EL1:
63710037SARM gem5 Developers        {
63810037SARM gem5 Developers            return tc->readIntReg(INTREG_SP1);
63910037SARM gem5 Developers        }
64010037SARM gem5 Developers      case MISCREG_SP_EL2:
64110037SARM gem5 Developers        {
64210037SARM gem5 Developers            return tc->readIntReg(INTREG_SP2);
64310037SARM gem5 Developers        }
64410037SARM gem5 Developers      case MISCREG_SPSEL:
64510037SARM gem5 Developers        {
64610037SARM gem5 Developers            return miscRegs[MISCREG_CPSR] & 0x1;
64710037SARM gem5 Developers        }
64810037SARM gem5 Developers      case MISCREG_CURRENTEL:
64910037SARM gem5 Developers        {
65010037SARM gem5 Developers            return miscRegs[MISCREG_CPSR] & 0xc;
65110037SARM gem5 Developers        }
6528549Sdaniel.johnson@arm.com      case MISCREG_L2CTLR:
6538868SMatt.Horsnell@arm.com        {
6548868SMatt.Horsnell@arm.com            // mostly unimplemented, just set NumCPUs field from sim and return
6558868SMatt.Horsnell@arm.com            L2CTLR l2ctlr = 0;
6568868SMatt.Horsnell@arm.com            // b00:1CPU to b11:4CPUs
6578868SMatt.Horsnell@arm.com            l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1;
6588868SMatt.Horsnell@arm.com            return l2ctlr;
6598868SMatt.Horsnell@arm.com        }
6608868SMatt.Horsnell@arm.com      case MISCREG_DBGDIDR:
6618868SMatt.Horsnell@arm.com        /* For now just implement the version number.
66210461SAndreas.Sandberg@ARM.com         * ARMv7, v7.1 Debug architecture (0b0101 --> 0x5)
6638868SMatt.Horsnell@arm.com         */
66410461SAndreas.Sandberg@ARM.com        return 0x5 << 16;
66510037SARM gem5 Developers      case MISCREG_DBGDSCRint:
6668868SMatt.Horsnell@arm.com        return 0;
66710037SARM gem5 Developers      case MISCREG_ISR:
66810037SARM gem5 Developers        return tc->getCpuPtr()->getInterruptController()->getISR(
66910037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_HCR),
67010037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_CPSR),
67110037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_SCR));
67210037SARM gem5 Developers      case MISCREG_ISR_EL1:
67310037SARM gem5 Developers        return tc->getCpuPtr()->getInterruptController()->getISR(
67410037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_HCR_EL2),
67510037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_CPSR),
67610037SARM gem5 Developers            readMiscRegNoEffect(MISCREG_SCR_EL3));
67710037SARM gem5 Developers      case MISCREG_DCZID_EL0:
67810037SARM gem5 Developers        return 0x04;  // DC ZVA clear 64-byte chunks
67910037SARM gem5 Developers      case MISCREG_HCPTR:
68010037SARM gem5 Developers        {
68110037SARM gem5 Developers            MiscReg val = readMiscRegNoEffect(misc_reg);
68210037SARM gem5 Developers            // The trap bit associated with CP14 is defined as RAZ
68310037SARM gem5 Developers            val &= ~(1 << 14);
68410037SARM gem5 Developers            // If a CP bit in NSACR is 0 then the corresponding bit in
68510037SARM gem5 Developers            // HCPTR is RAO/WI
68610037SARM gem5 Developers            bool secure_lookup = haveSecurity &&
68710037SARM gem5 Developers                inSecureState(readMiscRegNoEffect(MISCREG_SCR),
68810037SARM gem5 Developers                              readMiscRegNoEffect(MISCREG_CPSR));
68910037SARM gem5 Developers            if (!secure_lookup) {
69010037SARM gem5 Developers                MiscReg mask = readMiscRegNoEffect(MISCREG_NSACR);
69110037SARM gem5 Developers                val |= (mask ^ 0x7FFF) & 0xBFFF;
69210037SARM gem5 Developers            }
69310037SARM gem5 Developers            // Set the bits for unimplemented coprocessors to RAO/WI
69410037SARM gem5 Developers            val |= 0x33FF;
69510037SARM gem5 Developers            return (val);
69610037SARM gem5 Developers        }
69710037SARM gem5 Developers      case MISCREG_HDFAR: // alias for secure DFAR
69810037SARM gem5 Developers        return readMiscRegNoEffect(MISCREG_DFAR_S);
69910037SARM gem5 Developers      case MISCREG_HIFAR: // alias for secure IFAR
70010037SARM gem5 Developers        return readMiscRegNoEffect(MISCREG_IFAR_S);
70110037SARM gem5 Developers      case MISCREG_HVBAR: // bottom bits reserved
70210037SARM gem5 Developers        return readMiscRegNoEffect(MISCREG_HVBAR) & 0xFFFFFFE0;
70310037SARM gem5 Developers      case MISCREG_SCTLR: // Some bits hardwired
70410037SARM gem5 Developers        // The FI field (bit 21) is common between S/NS versions of the register
70510037SARM gem5 Developers        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
70610037SARM gem5 Developers               (readMiscRegNoEffect(misc_reg)        & 0x72DD39FF) | 0x00C00818; // V8 SCTLR
70710037SARM gem5 Developers      case MISCREG_SCTLR_EL1:
70810037SARM gem5 Developers        // The FI field (bit 21) is common between S/NS versions of the register
70910037SARM gem5 Developers        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
71010037SARM gem5 Developers               (readMiscRegNoEffect(misc_reg)        & 0x37DDDBFF) | 0x30D00800; // V8 SCTLR_EL1
71110037SARM gem5 Developers      case MISCREG_SCTLR_EL3:
71210037SARM gem5 Developers        // The FI field (bit 21) is common between S/NS versions of the register
71310037SARM gem5 Developers        return (readMiscRegNoEffect(MISCREG_SCTLR_S) & (1 << 21))  |
71410037SARM gem5 Developers               (readMiscRegNoEffect(misc_reg)        & 0x32CD183F) | 0x30C50830; // V8 SCTLR_EL3
71510037SARM gem5 Developers      case MISCREG_HSCTLR: // FI comes from SCTLR
71610037SARM gem5 Developers        {
71710037SARM gem5 Developers            uint32_t mask = 1 << 27;
71810037SARM gem5 Developers            return (readMiscRegNoEffect(MISCREG_HSCTLR) & ~mask) |
71910037SARM gem5 Developers                (readMiscRegNoEffect(MISCREG_SCTLR)  &  mask);
72010037SARM gem5 Developers        }
72110037SARM gem5 Developers      case MISCREG_SCR:
72210037SARM gem5 Developers        {
72310037SARM gem5 Developers            CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
72410037SARM gem5 Developers            if (cpsr.width) {
72510037SARM gem5 Developers                return readMiscRegNoEffect(MISCREG_SCR);
72610037SARM gem5 Developers            } else {
72710037SARM gem5 Developers                return readMiscRegNoEffect(MISCREG_SCR_EL3);
72810037SARM gem5 Developers            }
72910037SARM gem5 Developers        }
73010037SARM gem5 Developers      // Generic Timer registers
73110037SARM gem5 Developers      case MISCREG_CNTFRQ:
73210037SARM gem5 Developers      case MISCREG_CNTFRQ_EL0:
73310037SARM gem5 Developers        inform_once("Read CNTFREQ_EL0 frequency\n");
73410037SARM gem5 Developers        return getSystemCounter(tc)->freq();
73510037SARM gem5 Developers      case MISCREG_CNTPCT:
73610037SARM gem5 Developers      case MISCREG_CNTPCT_EL0:
73710037SARM gem5 Developers        return getSystemCounter(tc)->value();
73810037SARM gem5 Developers      case MISCREG_CNTVCT:
73910037SARM gem5 Developers        return getSystemCounter(tc)->value();
74010037SARM gem5 Developers      case MISCREG_CNTVCT_EL0:
74110037SARM gem5 Developers        return getSystemCounter(tc)->value();
74210037SARM gem5 Developers      case MISCREG_CNTP_CVAL:
74310037SARM gem5 Developers      case MISCREG_CNTP_CVAL_EL0:
74410037SARM gem5 Developers        return getArchTimer(tc, tc->cpuId())->compareValue();
74510037SARM gem5 Developers      case MISCREG_CNTP_TVAL:
74610037SARM gem5 Developers      case MISCREG_CNTP_TVAL_EL0:
74710037SARM gem5 Developers        return getArchTimer(tc, tc->cpuId())->timerValue();
74810037SARM gem5 Developers      case MISCREG_CNTP_CTL:
74910037SARM gem5 Developers      case MISCREG_CNTP_CTL_EL0:
75010037SARM gem5 Developers        return getArchTimer(tc, tc->cpuId())->control();
75110037SARM gem5 Developers      // PL1 phys. timer, secure
75210037SARM gem5 Developers      //   AArch64
75310188Sgeoffrey.blake@arm.com      // case MISCREG_CNTPS_CVAL_EL1:
75410188Sgeoffrey.blake@arm.com      // case MISCREG_CNTPS_TVAL_EL1:
75510188Sgeoffrey.blake@arm.com      // case MISCREG_CNTPS_CTL_EL1:
75610037SARM gem5 Developers      // PL2 phys. timer, non-secure
75710037SARM gem5 Developers      //   AArch32
75810188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHCTL:
75910188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_CVAL:
76010188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_TVAL:
76110188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_CTL:
76210037SARM gem5 Developers      //   AArch64
76310188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHCTL_EL2:
76410188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_CVAL_EL2:
76510188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_TVAL_EL2:
76610188Sgeoffrey.blake@arm.com      // case MISCREG_CNTHP_CTL_EL2:
76710037SARM gem5 Developers      // Virtual timer
76810037SARM gem5 Developers      //   AArch32
76910188Sgeoffrey.blake@arm.com      // case MISCREG_CNTV_CVAL:
77010188Sgeoffrey.blake@arm.com      // case MISCREG_CNTV_TVAL:
77110188Sgeoffrey.blake@arm.com      // case MISCREG_CNTV_CTL:
77210037SARM gem5 Developers      //   AArch64
77310037SARM gem5 Developers      // case MISCREG_CNTV_CVAL_EL2:
77410037SARM gem5 Developers      // case MISCREG_CNTV_TVAL_EL2:
77510037SARM gem5 Developers      // case MISCREG_CNTV_CTL_EL2:
77610188Sgeoffrey.blake@arm.com      default:
77710037SARM gem5 Developers        break;
77810037SARM gem5 Developers
7797405SAli.Saidi@ARM.com    }
7807405SAli.Saidi@ARM.com    return readMiscRegNoEffect(misc_reg);
7817405SAli.Saidi@ARM.com}
7827405SAli.Saidi@ARM.com
7837405SAli.Saidi@ARM.comvoid
7847405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val)
7857405SAli.Saidi@ARM.com{
7867405SAli.Saidi@ARM.com    assert(misc_reg < NumMiscRegs);
7877614Sminkyu.jeong@arm.com
78810037SARM gem5 Developers    int flat_idx = flattenMiscIndex(misc_reg);  // Note: indexes of AArch64
78910037SARM gem5 Developers                                                // registers are left unchanged
7907614Sminkyu.jeong@arm.com
79110037SARM gem5 Developers    int flat_idx2 = lookUpMiscReg[flat_idx].upper;
79210037SARM gem5 Developers
79310037SARM gem5 Developers    if (flat_idx2 > 0) {
79410037SARM gem5 Developers        miscRegs[lookUpMiscReg[flat_idx].lower] = bits(val, 31, 0);
79510037SARM gem5 Developers        miscRegs[flat_idx2] = bits(val, 63, 32);
79610037SARM gem5 Developers        DPRINTF(MiscRegs, "Writing to misc reg %d (%d:%d) : %#x\n",
79710037SARM gem5 Developers                misc_reg, flat_idx, flat_idx2, val);
79810037SARM gem5 Developers    } else {
79910037SARM gem5 Developers        if (flat_idx == MISCREG_SPSR)
80010037SARM gem5 Developers            flat_idx = flattenMiscIndex(MISCREG_SPSR);
80110037SARM gem5 Developers        else if (flat_idx == MISCREG_SCTLR_EL1)
80210037SARM gem5 Developers            flat_idx = flattenMiscIndex(MISCREG_SCTLR);
80310037SARM gem5 Developers        else
80410037SARM gem5 Developers            flat_idx = (lookUpMiscReg[flat_idx].lower > 0) ?
80510037SARM gem5 Developers                       lookUpMiscReg[flat_idx].lower : flat_idx;
80610037SARM gem5 Developers        miscRegs[flat_idx] = val;
80710037SARM gem5 Developers        DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n",
80810037SARM gem5 Developers                misc_reg, flat_idx, val);
80910037SARM gem5 Developers    }
8107405SAli.Saidi@ARM.com}
8117405SAli.Saidi@ARM.com
8127405SAli.Saidi@ARM.comvoid
8137405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc)
8147405SAli.Saidi@ARM.com{
8157749SAli.Saidi@ARM.com
8167405SAli.Saidi@ARM.com    MiscReg newVal = val;
8178284SAli.Saidi@ARM.com    int x;
81810037SARM gem5 Developers    bool secure_lookup;
81910037SARM gem5 Developers    bool hyp;
8208284SAli.Saidi@ARM.com    System *sys;
8218284SAli.Saidi@ARM.com    ThreadContext *oc;
82210037SARM gem5 Developers    uint8_t target_el;
82310037SARM gem5 Developers    uint16_t asid;
82410037SARM gem5 Developers    SCR scr;
8258284SAli.Saidi@ARM.com
8267405SAli.Saidi@ARM.com    if (misc_reg == MISCREG_CPSR) {
8277405SAli.Saidi@ARM.com        updateRegMap(val);
8287749SAli.Saidi@ARM.com
8297749SAli.Saidi@ARM.com
8307749SAli.Saidi@ARM.com        CPSR old_cpsr = miscRegs[MISCREG_CPSR];
8317749SAli.Saidi@ARM.com        int old_mode = old_cpsr.mode;
8327405SAli.Saidi@ARM.com        CPSR cpsr = val;
8337749SAli.Saidi@ARM.com        if (old_mode != cpsr.mode) {
8347749SAli.Saidi@ARM.com            tc->getITBPtr()->invalidateMiscReg();
8357749SAli.Saidi@ARM.com            tc->getDTBPtr()->invalidateMiscReg();
8367749SAli.Saidi@ARM.com        }
8377749SAli.Saidi@ARM.com
8387614Sminkyu.jeong@arm.com        DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
8397614Sminkyu.jeong@arm.com                miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
8407720Sgblack@eecs.umich.edu        PCState pc = tc->pcState();
8417720Sgblack@eecs.umich.edu        pc.nextThumb(cpsr.t);
8427720Sgblack@eecs.umich.edu        pc.nextJazelle(cpsr.j);
8438887Sgeoffrey.blake@arm.com
8448887Sgeoffrey.blake@arm.com        // Follow slightly different semantics if a CheckerCPU object
8458887Sgeoffrey.blake@arm.com        // is connected
8468887Sgeoffrey.blake@arm.com        CheckerCPU *checker = tc->getCheckerCpuPtr();
8478887Sgeoffrey.blake@arm.com        if (checker) {
8488887Sgeoffrey.blake@arm.com            tc->pcStateNoRecord(pc);
8498887Sgeoffrey.blake@arm.com        } else {
8508887Sgeoffrey.blake@arm.com            tc->pcState(pc);
8518887Sgeoffrey.blake@arm.com        }
8527408Sgblack@eecs.umich.edu    } else {
85310037SARM gem5 Developers#ifndef NDEBUG
85410037SARM gem5 Developers        if (!miscRegInfo[misc_reg][MISCREG_IMPLEMENTED]) {
85510037SARM gem5 Developers            if (miscRegInfo[misc_reg][MISCREG_WARN_NOT_FAIL])
85610037SARM gem5 Developers                warn("Unimplemented system register %s write with %#x.\n",
85710037SARM gem5 Developers                    miscRegName[misc_reg], val);
85810037SARM gem5 Developers            else
85910037SARM gem5 Developers                panic("Unimplemented system register %s write with %#x.\n",
86010037SARM gem5 Developers                    miscRegName[misc_reg], val);
86110037SARM gem5 Developers        }
86210037SARM gem5 Developers#endif
86310037SARM gem5 Developers        switch (unflattenMiscReg(misc_reg)) {
8647408Sgblack@eecs.umich.edu          case MISCREG_CPACR:
8657408Sgblack@eecs.umich.edu            {
8668206SWilliam.Wang@arm.com
8678206SWilliam.Wang@arm.com                const uint32_t ones = (uint32_t)(-1);
8688206SWilliam.Wang@arm.com                CPACR cpacrMask = 0;
8698206SWilliam.Wang@arm.com                // Only cp10, cp11, and ase are implemented, nothing else should
8708206SWilliam.Wang@arm.com                // be writable
8718206SWilliam.Wang@arm.com                cpacrMask.cp10 = ones;
8728206SWilliam.Wang@arm.com                cpacrMask.cp11 = ones;
8738206SWilliam.Wang@arm.com                cpacrMask.asedis = ones;
87410037SARM gem5 Developers
87510037SARM gem5 Developers                // Security Extensions may limit the writability of CPACR
87610037SARM gem5 Developers                if (haveSecurity) {
87710037SARM gem5 Developers                    scr = readMiscRegNoEffect(MISCREG_SCR);
87810037SARM gem5 Developers                    CPSR cpsr = readMiscRegNoEffect(MISCREG_CPSR);
87910037SARM gem5 Developers                    if (scr.ns && (cpsr.mode != MODE_MON)) {
88010037SARM gem5 Developers                        NSACR nsacr = readMiscRegNoEffect(MISCREG_NSACR);
88110037SARM gem5 Developers                        // NB: Skipping the full loop, here
88210037SARM gem5 Developers                        if (!nsacr.cp10) cpacrMask.cp10 = 0;
88310037SARM gem5 Developers                        if (!nsacr.cp11) cpacrMask.cp11 = 0;
88410037SARM gem5 Developers                    }
88510037SARM gem5 Developers                }
88610037SARM gem5 Developers
88710037SARM gem5 Developers                MiscReg old_val = readMiscRegNoEffect(MISCREG_CPACR);
8888206SWilliam.Wang@arm.com                newVal &= cpacrMask;
88910037SARM gem5 Developers                newVal |= old_val & ~cpacrMask;
89010037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
89110037SARM gem5 Developers                        miscRegName[misc_reg], newVal);
89210037SARM gem5 Developers            }
89310037SARM gem5 Developers            break;
89410037SARM gem5 Developers          case MISCREG_CPACR_EL1:
89510037SARM gem5 Developers            {
89610037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
89710037SARM gem5 Developers                CPACR cpacrMask = 0;
89810037SARM gem5 Developers                cpacrMask.tta = ones;
89910037SARM gem5 Developers                cpacrMask.fpen = ones;
90010037SARM gem5 Developers                newVal &= cpacrMask;
90110037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
90210037SARM gem5 Developers                        miscRegName[misc_reg], newVal);
90310037SARM gem5 Developers            }
90410037SARM gem5 Developers            break;
90510037SARM gem5 Developers          case MISCREG_CPTR_EL2:
90610037SARM gem5 Developers            {
90710037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
90810037SARM gem5 Developers                CPTR cptrMask = 0;
90910037SARM gem5 Developers                cptrMask.tcpac = ones;
91010037SARM gem5 Developers                cptrMask.tta = ones;
91110037SARM gem5 Developers                cptrMask.tfp = ones;
91210037SARM gem5 Developers                newVal &= cptrMask;
91310037SARM gem5 Developers                cptrMask = 0;
91410037SARM gem5 Developers                cptrMask.res1_13_12_el2 = ones;
91510037SARM gem5 Developers                cptrMask.res1_9_0_el2 = ones;
91610037SARM gem5 Developers                newVal |= cptrMask;
91710037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
91810037SARM gem5 Developers                        miscRegName[misc_reg], newVal);
91910037SARM gem5 Developers            }
92010037SARM gem5 Developers            break;
92110037SARM gem5 Developers          case MISCREG_CPTR_EL3:
92210037SARM gem5 Developers            {
92310037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
92410037SARM gem5 Developers                CPTR cptrMask = 0;
92510037SARM gem5 Developers                cptrMask.tcpac = ones;
92610037SARM gem5 Developers                cptrMask.tta = ones;
92710037SARM gem5 Developers                cptrMask.tfp = ones;
92810037SARM gem5 Developers                newVal &= cptrMask;
9298206SWilliam.Wang@arm.com                DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n",
9308206SWilliam.Wang@arm.com                        miscRegName[misc_reg], newVal);
9317408Sgblack@eecs.umich.edu            }
9327408Sgblack@eecs.umich.edu            break;
9337408Sgblack@eecs.umich.edu          case MISCREG_CSSELR:
9347731SAli.Saidi@ARM.com            warn_once("The csselr register isn't implemented.\n");
9358206SWilliam.Wang@arm.com            return;
93610037SARM gem5 Developers
93710037SARM gem5 Developers          case MISCREG_DC_ZVA_Xt:
93810037SARM gem5 Developers            warn("Calling DC ZVA! Not Implemeted! Expect WEIRD results\n");
93910037SARM gem5 Developers            return;
94010037SARM gem5 Developers
9417408Sgblack@eecs.umich.edu          case MISCREG_FPSCR:
9427408Sgblack@eecs.umich.edu            {
9437408Sgblack@eecs.umich.edu                const uint32_t ones = (uint32_t)(-1);
9447408Sgblack@eecs.umich.edu                FPSCR fpscrMask = 0;
9457408Sgblack@eecs.umich.edu                fpscrMask.ioc = ones;
9467408Sgblack@eecs.umich.edu                fpscrMask.dzc = ones;
9477408Sgblack@eecs.umich.edu                fpscrMask.ofc = ones;
9487408Sgblack@eecs.umich.edu                fpscrMask.ufc = ones;
9497408Sgblack@eecs.umich.edu                fpscrMask.ixc = ones;
9507408Sgblack@eecs.umich.edu                fpscrMask.idc = ones;
95110037SARM gem5 Developers                fpscrMask.ioe = ones;
95210037SARM gem5 Developers                fpscrMask.dze = ones;
95310037SARM gem5 Developers                fpscrMask.ofe = ones;
95410037SARM gem5 Developers                fpscrMask.ufe = ones;
95510037SARM gem5 Developers                fpscrMask.ixe = ones;
95610037SARM gem5 Developers                fpscrMask.ide = ones;
9577408Sgblack@eecs.umich.edu                fpscrMask.len = ones;
9587408Sgblack@eecs.umich.edu                fpscrMask.stride = ones;
9597408Sgblack@eecs.umich.edu                fpscrMask.rMode = ones;
9607408Sgblack@eecs.umich.edu                fpscrMask.fz = ones;
9617408Sgblack@eecs.umich.edu                fpscrMask.dn = ones;
9627408Sgblack@eecs.umich.edu                fpscrMask.ahp = ones;
9637408Sgblack@eecs.umich.edu                fpscrMask.qc = ones;
9647408Sgblack@eecs.umich.edu                fpscrMask.v = ones;
9657408Sgblack@eecs.umich.edu                fpscrMask.c = ones;
9667408Sgblack@eecs.umich.edu                fpscrMask.z = ones;
9677408Sgblack@eecs.umich.edu                fpscrMask.n = ones;
9687408Sgblack@eecs.umich.edu                newVal = (newVal & (uint32_t)fpscrMask) |
96910037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
97010037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
9719377Sgblack@eecs.umich.edu                tc->getDecoderPtr()->setContext(newVal);
9727408Sgblack@eecs.umich.edu            }
9737408Sgblack@eecs.umich.edu            break;
97410037SARM gem5 Developers          case MISCREG_FPSR:
97510037SARM gem5 Developers            {
97610037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
97710037SARM gem5 Developers                FPSCR fpscrMask = 0;
97810037SARM gem5 Developers                fpscrMask.ioc = ones;
97910037SARM gem5 Developers                fpscrMask.dzc = ones;
98010037SARM gem5 Developers                fpscrMask.ofc = ones;
98110037SARM gem5 Developers                fpscrMask.ufc = ones;
98210037SARM gem5 Developers                fpscrMask.ixc = ones;
98310037SARM gem5 Developers                fpscrMask.idc = ones;
98410037SARM gem5 Developers                fpscrMask.qc = ones;
98510037SARM gem5 Developers                fpscrMask.v = ones;
98610037SARM gem5 Developers                fpscrMask.c = ones;
98710037SARM gem5 Developers                fpscrMask.z = ones;
98810037SARM gem5 Developers                fpscrMask.n = ones;
98910037SARM gem5 Developers                newVal = (newVal & (uint32_t)fpscrMask) |
99010037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
99110037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
99210037SARM gem5 Developers                misc_reg = MISCREG_FPSCR;
99310037SARM gem5 Developers            }
99410037SARM gem5 Developers            break;
99510037SARM gem5 Developers          case MISCREG_FPCR:
99610037SARM gem5 Developers            {
99710037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
99810037SARM gem5 Developers                FPSCR fpscrMask  = 0;
99910037SARM gem5 Developers                fpscrMask.ioe = ones;
100010037SARM gem5 Developers                fpscrMask.dze = ones;
100110037SARM gem5 Developers                fpscrMask.ofe = ones;
100210037SARM gem5 Developers                fpscrMask.ufe = ones;
100310037SARM gem5 Developers                fpscrMask.ixe = ones;
100410037SARM gem5 Developers                fpscrMask.ide = ones;
100510037SARM gem5 Developers                fpscrMask.len    = ones;
100610037SARM gem5 Developers                fpscrMask.stride = ones;
100710037SARM gem5 Developers                fpscrMask.rMode  = ones;
100810037SARM gem5 Developers                fpscrMask.fz     = ones;
100910037SARM gem5 Developers                fpscrMask.dn     = ones;
101010037SARM gem5 Developers                fpscrMask.ahp    = ones;
101110037SARM gem5 Developers                newVal = (newVal & (uint32_t)fpscrMask) |
101210037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPSCR) &
101310037SARM gem5 Developers                          ~(uint32_t)fpscrMask);
101410037SARM gem5 Developers                misc_reg = MISCREG_FPSCR;
101510037SARM gem5 Developers            }
101610037SARM gem5 Developers            break;
10178302SAli.Saidi@ARM.com          case MISCREG_CPSR_Q:
10188302SAli.Saidi@ARM.com            {
10198302SAli.Saidi@ARM.com                assert(!(newVal & ~CpsrMaskQ));
102010037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_CPSR) | newVal;
10218302SAli.Saidi@ARM.com                misc_reg = MISCREG_CPSR;
10228302SAli.Saidi@ARM.com            }
10238302SAli.Saidi@ARM.com            break;
10247783SGiacomo.Gabrielli@arm.com          case MISCREG_FPSCR_QC:
10257783SGiacomo.Gabrielli@arm.com            {
102610037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
102710037SARM gem5 Developers                         (newVal & FpscrQcMask);
10287783SGiacomo.Gabrielli@arm.com                misc_reg = MISCREG_FPSCR;
10297783SGiacomo.Gabrielli@arm.com            }
10307783SGiacomo.Gabrielli@arm.com            break;
10317783SGiacomo.Gabrielli@arm.com          case MISCREG_FPSCR_EXC:
10327783SGiacomo.Gabrielli@arm.com            {
103310037SARM gem5 Developers                newVal = readMiscRegNoEffect(MISCREG_FPSCR) |
103410037SARM gem5 Developers                         (newVal & FpscrExcMask);
10357783SGiacomo.Gabrielli@arm.com                misc_reg = MISCREG_FPSCR;
10367783SGiacomo.Gabrielli@arm.com            }
10377783SGiacomo.Gabrielli@arm.com            break;
10387408Sgblack@eecs.umich.edu          case MISCREG_FPEXC:
10397408Sgblack@eecs.umich.edu            {
10408206SWilliam.Wang@arm.com                // vfpv3 architecture, section B.6.1 of DDI04068
10418206SWilliam.Wang@arm.com                // bit 29 - valid only if fpexc[31] is 0
10427408Sgblack@eecs.umich.edu                const uint32_t fpexcMask = 0x60000000;
10437408Sgblack@eecs.umich.edu                newVal = (newVal & fpexcMask) |
104410037SARM gem5 Developers                         (readMiscRegNoEffect(MISCREG_FPEXC) & ~fpexcMask);
10457408Sgblack@eecs.umich.edu            }
10467408Sgblack@eecs.umich.edu            break;
104710037SARM gem5 Developers          case MISCREG_HCR:
104810037SARM gem5 Developers            {
104910037SARM gem5 Developers                if (!haveVirtualization)
105010037SARM gem5 Developers                    return;
105110037SARM gem5 Developers            }
105210037SARM gem5 Developers            break;
105310037SARM gem5 Developers          case MISCREG_IFSR:
105410037SARM gem5 Developers            {
105510037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.96
105610037SARM gem5 Developers                const uint32_t ifsrMask =
105710037SARM gem5 Developers                    mask(31, 13) | mask(11, 11) | mask(8, 6);
105810037SARM gem5 Developers                newVal = newVal & ~ifsrMask;
105910037SARM gem5 Developers            }
106010037SARM gem5 Developers            break;
106110037SARM gem5 Developers          case MISCREG_DFSR:
106210037SARM gem5 Developers            {
106310037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.52
106410037SARM gem5 Developers                const uint32_t dfsrMask = mask(31, 14) | mask(8, 8);
106510037SARM gem5 Developers                newVal = newVal & ~dfsrMask;
106610037SARM gem5 Developers            }
106710037SARM gem5 Developers            break;
106810037SARM gem5 Developers          case MISCREG_AMAIR0:
106910037SARM gem5 Developers          case MISCREG_AMAIR1:
107010037SARM gem5 Developers            {
107110037SARM gem5 Developers                // ARM ARM (ARM DDI 0406C.b) B4.1.5
107210037SARM gem5 Developers                // Valid only with LPAE
107310037SARM gem5 Developers                if (!haveLPAE)
107410037SARM gem5 Developers                    return;
107510037SARM gem5 Developers                DPRINTF(MiscRegs, "Writing AMAIR: %#x\n", newVal);
107610037SARM gem5 Developers            }
107710037SARM gem5 Developers            break;
107810037SARM gem5 Developers          case MISCREG_SCR:
107910037SARM gem5 Developers            tc->getITBPtr()->invalidateMiscReg();
108010037SARM gem5 Developers            tc->getDTBPtr()->invalidateMiscReg();
108110037SARM gem5 Developers            break;
10827408Sgblack@eecs.umich.edu          case MISCREG_SCTLR:
10837408Sgblack@eecs.umich.edu            {
10847408Sgblack@eecs.umich.edu                DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal);
108510037SARM gem5 Developers                MiscRegIndex sctlr_idx;
108610037SARM gem5 Developers                scr = readMiscRegNoEffect(MISCREG_SCR);
108710037SARM gem5 Developers                if (haveSecurity && !scr.ns) {
108810037SARM gem5 Developers                    sctlr_idx = MISCREG_SCTLR_S;
108910037SARM gem5 Developers                } else {
109010037SARM gem5 Developers                    sctlr_idx = MISCREG_SCTLR_NS;
109110037SARM gem5 Developers                    // The FI field (bit 21) is common between S/NS versions
109210037SARM gem5 Developers                    // of the register, we store this in the secure copy of
109310037SARM gem5 Developers                    // the reg
109410037SARM gem5 Developers                    miscRegs[MISCREG_SCTLR_S] &=         ~(1 << 21);
109510037SARM gem5 Developers                    miscRegs[MISCREG_SCTLR_S] |= newVal & (1 << 21);
109610037SARM gem5 Developers                }
109710037SARM gem5 Developers                SCTLR sctlr = miscRegs[sctlr_idx];
10987408Sgblack@eecs.umich.edu                SCTLR new_sctlr = newVal;
109910037SARM gem5 Developers                new_sctlr.nmfi =  ((bool)sctlr.nmfi) && !haveVirtualization;
110010037SARM gem5 Developers                miscRegs[sctlr_idx] = (MiscReg)new_sctlr;
11017749SAli.Saidi@ARM.com                tc->getITBPtr()->invalidateMiscReg();
11027749SAli.Saidi@ARM.com                tc->getDTBPtr()->invalidateMiscReg();
11038527SAli.Saidi@ARM.com
11048527SAli.Saidi@ARM.com                // Check if all CPUs are booted with caches enabled
11058527SAli.Saidi@ARM.com                // so we can stop enforcing coherency of some kernel
11068527SAli.Saidi@ARM.com                // structures manually.
11078527SAli.Saidi@ARM.com                sys = tc->getSystemPtr();
11088527SAli.Saidi@ARM.com                for (x = 0; x < sys->numContexts(); x++) {
11098527SAli.Saidi@ARM.com                    oc = sys->getThreadContext(x);
111010037SARM gem5 Developers                    // @todo: double check this for security
11118527SAli.Saidi@ARM.com                    SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR);
11128527SAli.Saidi@ARM.com                    if (!other_sctlr.c && oc->status() != ThreadContext::Halted)
11138527SAli.Saidi@ARM.com                        return;
11148527SAli.Saidi@ARM.com                }
11158527SAli.Saidi@ARM.com
11168527SAli.Saidi@ARM.com                for (x = 0; x < sys->numContexts(); x++) {
11178527SAli.Saidi@ARM.com                    oc = sys->getThreadContext(x);
11188527SAli.Saidi@ARM.com                    oc->getDTBPtr()->allCpusCaching();
11198527SAli.Saidi@ARM.com                    oc->getITBPtr()->allCpusCaching();
11208887Sgeoffrey.blake@arm.com
11218887Sgeoffrey.blake@arm.com                    // If CheckerCPU is connected, need to notify it.
11228887Sgeoffrey.blake@arm.com                    CheckerCPU *checker = oc->getCheckerCpuPtr();
11238733Sgeoffrey.blake@arm.com                    if (checker) {
11248733Sgeoffrey.blake@arm.com                        checker->getDTBPtr()->allCpusCaching();
11258733Sgeoffrey.blake@arm.com                        checker->getITBPtr()->allCpusCaching();
11268733Sgeoffrey.blake@arm.com                    }
11278527SAli.Saidi@ARM.com                }
11287408Sgblack@eecs.umich.edu                return;
11297408Sgblack@eecs.umich.edu            }
11309385SAndreas.Sandberg@arm.com
11319385SAndreas.Sandberg@arm.com          case MISCREG_MIDR:
11329385SAndreas.Sandberg@arm.com          case MISCREG_ID_PFR0:
11339385SAndreas.Sandberg@arm.com          case MISCREG_ID_PFR1:
113410461SAndreas.Sandberg@ARM.com          case MISCREG_ID_DFR0:
11359385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR0:
11369385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR1:
11379385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR2:
11389385SAndreas.Sandberg@arm.com          case MISCREG_ID_MMFR3:
11399385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR0:
11409385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR1:
11419385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR2:
11429385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR3:
11439385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR4:
11449385SAndreas.Sandberg@arm.com          case MISCREG_ID_ISAR5:
11459385SAndreas.Sandberg@arm.com
11469385SAndreas.Sandberg@arm.com          case MISCREG_MPIDR:
11479385SAndreas.Sandberg@arm.com          case MISCREG_FPSID:
11487408Sgblack@eecs.umich.edu          case MISCREG_TLBTR:
11497408Sgblack@eecs.umich.edu          case MISCREG_MVFR0:
11507408Sgblack@eecs.umich.edu          case MISCREG_MVFR1:
115110037SARM gem5 Developers
115210037SARM gem5 Developers          case MISCREG_ID_AA64AFR0_EL1:
115310037SARM gem5 Developers          case MISCREG_ID_AA64AFR1_EL1:
115410037SARM gem5 Developers          case MISCREG_ID_AA64DFR0_EL1:
115510037SARM gem5 Developers          case MISCREG_ID_AA64DFR1_EL1:
115610037SARM gem5 Developers          case MISCREG_ID_AA64ISAR0_EL1:
115710037SARM gem5 Developers          case MISCREG_ID_AA64ISAR1_EL1:
115810037SARM gem5 Developers          case MISCREG_ID_AA64MMFR0_EL1:
115910037SARM gem5 Developers          case MISCREG_ID_AA64MMFR1_EL1:
116010037SARM gem5 Developers          case MISCREG_ID_AA64PFR0_EL1:
116110037SARM gem5 Developers          case MISCREG_ID_AA64PFR1_EL1:
11629385SAndreas.Sandberg@arm.com            // ID registers are constants.
11637408Sgblack@eecs.umich.edu            return;
11649385SAndreas.Sandberg@arm.com
116510037SARM gem5 Developers          // TLBI all entries, EL0&1 inner sharable (ignored)
11667408Sgblack@eecs.umich.edu          case MISCREG_TLBIALLIS:
116710037SARM gem5 Developers          case MISCREG_TLBIALL: // TLBI all entries, EL0&1,
116810037SARM gem5 Developers            assert32(tc);
116910037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
117010037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
117110037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
11728284SAli.Saidi@ARM.com            sys = tc->getSystemPtr();
11738284SAli.Saidi@ARM.com            for (x = 0; x < sys->numContexts(); x++) {
11748284SAli.Saidi@ARM.com                oc = sys->getThreadContext(x);
11758284SAli.Saidi@ARM.com                assert(oc->getITBPtr() && oc->getDTBPtr());
117610037SARM gem5 Developers                oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
117710037SARM gem5 Developers                oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
11788887Sgeoffrey.blake@arm.com
11798887Sgeoffrey.blake@arm.com                // If CheckerCPU is connected, need to notify it of a flush
11808887Sgeoffrey.blake@arm.com                CheckerCPU *checker = oc->getCheckerCpuPtr();
11818733Sgeoffrey.blake@arm.com                if (checker) {
118210037SARM gem5 Developers                    checker->getITBPtr()->flushAllSecurity(secure_lookup,
118310037SARM gem5 Developers                                                           target_el);
118410037SARM gem5 Developers                    checker->getDTBPtr()->flushAllSecurity(secure_lookup,
118510037SARM gem5 Developers                                                           target_el);
11868733Sgeoffrey.blake@arm.com                }
11878284SAli.Saidi@ARM.com            }
11887408Sgblack@eecs.umich.edu            return;
118910037SARM gem5 Developers          // TLBI all entries, EL0&1, instruction side
11907408Sgblack@eecs.umich.edu          case MISCREG_ITLBIALL:
119110037SARM gem5 Developers            assert32(tc);
119210037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
119310037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
119410037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
119510037SARM gem5 Developers            tc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
11967408Sgblack@eecs.umich.edu            return;
119710037SARM gem5 Developers          // TLBI all entries, EL0&1, data side
11987408Sgblack@eecs.umich.edu          case MISCREG_DTLBIALL:
119910037SARM gem5 Developers            assert32(tc);
120010037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
120110037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
120210037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
120310037SARM gem5 Developers            tc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
12047408Sgblack@eecs.umich.edu            return;
120510037SARM gem5 Developers          // TLBI based on VA, EL0&1 inner sharable (ignored)
12067408Sgblack@eecs.umich.edu          case MISCREG_TLBIMVAIS:
12077408Sgblack@eecs.umich.edu          case MISCREG_TLBIMVA:
120810037SARM gem5 Developers            assert32(tc);
120910037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
121010037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
121110037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
12128284SAli.Saidi@ARM.com            sys = tc->getSystemPtr();
12138284SAli.Saidi@ARM.com            for (x = 0; x < sys->numContexts(); x++) {
12148284SAli.Saidi@ARM.com                oc = sys->getThreadContext(x);
12158284SAli.Saidi@ARM.com                assert(oc->getITBPtr() && oc->getDTBPtr());
12168284SAli.Saidi@ARM.com                oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
121710037SARM gem5 Developers                                              bits(newVal, 7,0),
121810037SARM gem5 Developers                                              secure_lookup, target_el);
12198284SAli.Saidi@ARM.com                oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
122010037SARM gem5 Developers                                              bits(newVal, 7,0),
122110037SARM gem5 Developers                                              secure_lookup, target_el);
12228887Sgeoffrey.blake@arm.com
12238887Sgeoffrey.blake@arm.com                CheckerCPU *checker = oc->getCheckerCpuPtr();
12248733Sgeoffrey.blake@arm.com                if (checker) {
12258733Sgeoffrey.blake@arm.com                    checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
122610037SARM gem5 Developers                        bits(newVal, 7,0), secure_lookup, target_el);
12278733Sgeoffrey.blake@arm.com                    checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
122810037SARM gem5 Developers                        bits(newVal, 7,0), secure_lookup, target_el);
12298733Sgeoffrey.blake@arm.com                }
12308284SAli.Saidi@ARM.com            }
12317408Sgblack@eecs.umich.edu            return;
123210037SARM gem5 Developers          // TLBI by ASID, EL0&1, inner sharable
12337408Sgblack@eecs.umich.edu          case MISCREG_TLBIASIDIS:
12347408Sgblack@eecs.umich.edu          case MISCREG_TLBIASID:
123510037SARM gem5 Developers            assert32(tc);
123610037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
123710037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
123810037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
12398284SAli.Saidi@ARM.com            sys = tc->getSystemPtr();
12408284SAli.Saidi@ARM.com            for (x = 0; x < sys->numContexts(); x++) {
12418284SAli.Saidi@ARM.com                oc = sys->getThreadContext(x);
12428284SAli.Saidi@ARM.com                assert(oc->getITBPtr() && oc->getDTBPtr());
124310037SARM gem5 Developers                oc->getITBPtr()->flushAsid(bits(newVal, 7,0),
124410037SARM gem5 Developers                    secure_lookup, target_el);
124510037SARM gem5 Developers                oc->getDTBPtr()->flushAsid(bits(newVal, 7,0),
124610037SARM gem5 Developers                    secure_lookup, target_el);
12478887Sgeoffrey.blake@arm.com                CheckerCPU *checker = oc->getCheckerCpuPtr();
12488733Sgeoffrey.blake@arm.com                if (checker) {
124910037SARM gem5 Developers                    checker->getITBPtr()->flushAsid(bits(newVal, 7,0),
125010037SARM gem5 Developers                        secure_lookup, target_el);
125110037SARM gem5 Developers                    checker->getDTBPtr()->flushAsid(bits(newVal, 7,0),
125210037SARM gem5 Developers                        secure_lookup, target_el);
12538733Sgeoffrey.blake@arm.com                }
12548284SAli.Saidi@ARM.com            }
12557408Sgblack@eecs.umich.edu            return;
125610037SARM gem5 Developers          // TLBI by address, EL0&1, inner sharable (ignored)
12577408Sgblack@eecs.umich.edu          case MISCREG_TLBIMVAAIS:
12587408Sgblack@eecs.umich.edu          case MISCREG_TLBIMVAA:
125910037SARM gem5 Developers            assert32(tc);
126010037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
126110037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
126210037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
126310037SARM gem5 Developers            hyp = 0;
126410037SARM gem5 Developers            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
126510037SARM gem5 Developers            return;
126610037SARM gem5 Developers          // TLBI by address, EL2, hypervisor mode
126710037SARM gem5 Developers          case MISCREG_TLBIMVAH:
126810037SARM gem5 Developers          case MISCREG_TLBIMVAHIS:
126910037SARM gem5 Developers            assert32(tc);
127010037SARM gem5 Developers            target_el = 1; // aarch32, use hyp bit
127110037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
127210037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
127310037SARM gem5 Developers            hyp = 1;
127410037SARM gem5 Developers            tlbiMVA(tc, newVal, secure_lookup, hyp, target_el);
127510037SARM gem5 Developers            return;
127610037SARM gem5 Developers          // TLBI by address and asid, EL0&1, instruction side only
127710037SARM gem5 Developers          case MISCREG_ITLBIMVA:
127810037SARM gem5 Developers            assert32(tc);
127910037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
128010037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
128110037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
128210037SARM gem5 Developers            tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
128310037SARM gem5 Developers                bits(newVal, 7,0), secure_lookup, target_el);
128410037SARM gem5 Developers            return;
128510037SARM gem5 Developers          // TLBI by address and asid, EL0&1, data side only
128610037SARM gem5 Developers          case MISCREG_DTLBIMVA:
128710037SARM gem5 Developers            assert32(tc);
128810037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
128910037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
129010037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
129110037SARM gem5 Developers            tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12),
129210037SARM gem5 Developers                bits(newVal, 7,0), secure_lookup, target_el);
129310037SARM gem5 Developers            return;
129410037SARM gem5 Developers          // TLBI by ASID, EL0&1, instrution side only
129510037SARM gem5 Developers          case MISCREG_ITLBIASID:
129610037SARM gem5 Developers            assert32(tc);
129710037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
129810037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
129910037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
130010037SARM gem5 Developers            tc->getITBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
130110037SARM gem5 Developers                                       target_el);
130210037SARM gem5 Developers            return;
130310037SARM gem5 Developers          // TLBI by ASID EL0&1 data size only
130410037SARM gem5 Developers          case MISCREG_DTLBIASID:
130510037SARM gem5 Developers            assert32(tc);
130610037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
130710037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
130810037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
130910037SARM gem5 Developers            tc->getDTBPtr()->flushAsid(bits(newVal, 7,0), secure_lookup,
131010037SARM gem5 Developers                                       target_el);
131110037SARM gem5 Developers            return;
131210037SARM gem5 Developers          // Invalidate entire Non-secure Hyp/Non-Hyp Unified TLB
131310037SARM gem5 Developers          case MISCREG_TLBIALLNSNH:
131410037SARM gem5 Developers          case MISCREG_TLBIALLNSNHIS:
131510037SARM gem5 Developers            assert32(tc);
131610037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
131710037SARM gem5 Developers            hyp = 0;
131810037SARM gem5 Developers            tlbiALLN(tc, hyp, target_el);
131910037SARM gem5 Developers            return;
132010037SARM gem5 Developers          // TLBI all entries, EL2, hyp,
132110037SARM gem5 Developers          case MISCREG_TLBIALLH:
132210037SARM gem5 Developers          case MISCREG_TLBIALLHIS:
132310037SARM gem5 Developers            assert32(tc);
132410037SARM gem5 Developers            target_el = 1; // aarch32, use hyp bit
132510037SARM gem5 Developers            hyp = 1;
132610037SARM gem5 Developers            tlbiALLN(tc, hyp, target_el);
132710037SARM gem5 Developers            return;
132810037SARM gem5 Developers          // AArch64 TLBI: invalidate all entries EL3
132910037SARM gem5 Developers          case MISCREG_TLBI_ALLE3IS:
133010037SARM gem5 Developers          case MISCREG_TLBI_ALLE3:
133110037SARM gem5 Developers            assert64(tc);
133210037SARM gem5 Developers            target_el = 3;
133310037SARM gem5 Developers            secure_lookup = true;
133410037SARM gem5 Developers            tlbiALL(tc, secure_lookup, target_el);
133510037SARM gem5 Developers            return;
133610037SARM gem5 Developers          // @todo: uncomment this to enable Virtualization
133710037SARM gem5 Developers          // case MISCREG_TLBI_ALLE2IS:
133810037SARM gem5 Developers          // case MISCREG_TLBI_ALLE2:
133910037SARM gem5 Developers          // TLBI all entries, EL0&1
134010037SARM gem5 Developers          case MISCREG_TLBI_ALLE1IS:
134110037SARM gem5 Developers          case MISCREG_TLBI_ALLE1:
134210037SARM gem5 Developers          // AArch64 TLBI: invalidate all entries, stage 1, current VMID
134310037SARM gem5 Developers          case MISCREG_TLBI_VMALLE1IS:
134410037SARM gem5 Developers          case MISCREG_TLBI_VMALLE1:
134510037SARM gem5 Developers          // AArch64 TLBI: invalidate all entries, stages 1 & 2, current VMID
134610037SARM gem5 Developers          case MISCREG_TLBI_VMALLS12E1IS:
134710037SARM gem5 Developers          case MISCREG_TLBI_VMALLS12E1:
134810037SARM gem5 Developers            // @todo: handle VMID and stage 2 to enable Virtualization
134910037SARM gem5 Developers            assert64(tc);
135010037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
135110037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
135210037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
135310037SARM gem5 Developers            tlbiALL(tc, secure_lookup, target_el);
135410037SARM gem5 Developers            return;
135510037SARM gem5 Developers          // AArch64 TLBI: invalidate by VA and ASID, stage 1, current VMID
135610037SARM gem5 Developers          // VAEx(IS) and VALEx(IS) are the same because TLBs only store entries
135710037SARM gem5 Developers          // from the last level of translation table walks
135810037SARM gem5 Developers          // @todo: handle VMID to enable Virtualization
135910037SARM gem5 Developers          // TLBI all entries, EL0&1
136010037SARM gem5 Developers          case MISCREG_TLBI_VAE3IS_Xt:
136110037SARM gem5 Developers          case MISCREG_TLBI_VAE3_Xt:
136210037SARM gem5 Developers          // TLBI by VA, EL3  regime stage 1, last level walk
136310037SARM gem5 Developers          case MISCREG_TLBI_VALE3IS_Xt:
136410037SARM gem5 Developers          case MISCREG_TLBI_VALE3_Xt:
136510037SARM gem5 Developers            assert64(tc);
136610037SARM gem5 Developers            target_el = 3;
136710037SARM gem5 Developers            asid = 0xbeef; // does not matter, tlbi is global
136810037SARM gem5 Developers            secure_lookup = true;
136910037SARM gem5 Developers            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
137010037SARM gem5 Developers            return;
137110037SARM gem5 Developers          // TLBI by VA, EL2
137210037SARM gem5 Developers          case MISCREG_TLBI_VAE2IS_Xt:
137310037SARM gem5 Developers          case MISCREG_TLBI_VAE2_Xt:
137410037SARM gem5 Developers          // TLBI by VA, EL2, stage1 last level walk
137510037SARM gem5 Developers          case MISCREG_TLBI_VALE2IS_Xt:
137610037SARM gem5 Developers          case MISCREG_TLBI_VALE2_Xt:
137710037SARM gem5 Developers            assert64(tc);
137810037SARM gem5 Developers            target_el = 2;
137910037SARM gem5 Developers            asid = 0xbeef; // does not matter, tlbi is global
138010037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
138110037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
138210037SARM gem5 Developers            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
138310037SARM gem5 Developers            return;
138410037SARM gem5 Developers          // TLBI by VA EL1 & 0, stage1, ASID, current VMID
138510037SARM gem5 Developers          case MISCREG_TLBI_VAE1IS_Xt:
138610037SARM gem5 Developers          case MISCREG_TLBI_VAE1_Xt:
138710037SARM gem5 Developers          case MISCREG_TLBI_VALE1IS_Xt:
138810037SARM gem5 Developers          case MISCREG_TLBI_VALE1_Xt:
138910037SARM gem5 Developers            assert64(tc);
139010037SARM gem5 Developers            asid = bits(newVal, 63, 48);
139110037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
139210037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
139310037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
139410037SARM gem5 Developers            tlbiVA(tc, newVal, asid, secure_lookup, target_el);
139510037SARM gem5 Developers            return;
139610037SARM gem5 Developers          // AArch64 TLBI: invalidate by ASID, stage 1, current VMID
139710037SARM gem5 Developers          // @todo: handle VMID to enable Virtualization
139810037SARM gem5 Developers          case MISCREG_TLBI_ASIDE1IS_Xt:
139910037SARM gem5 Developers          case MISCREG_TLBI_ASIDE1_Xt:
140010037SARM gem5 Developers            assert64(tc);
140110037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
140210037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
140310037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
14048284SAli.Saidi@ARM.com            sys = tc->getSystemPtr();
14058284SAli.Saidi@ARM.com            for (x = 0; x < sys->numContexts(); x++) {
14068284SAli.Saidi@ARM.com                oc = sys->getThreadContext(x);
14078284SAli.Saidi@ARM.com                assert(oc->getITBPtr() && oc->getDTBPtr());
140810037SARM gem5 Developers                asid = bits(newVal, 63, 48);
140910037SARM gem5 Developers                if (haveLargeAsid64)
141010037SARM gem5 Developers                    asid &= mask(8);
141110037SARM gem5 Developers                oc->getITBPtr()->flushAsid(asid, secure_lookup, target_el);
141210037SARM gem5 Developers                oc->getDTBPtr()->flushAsid(asid, secure_lookup, target_el);
141310037SARM gem5 Developers                CheckerCPU *checker = oc->getCheckerCpuPtr();
141410037SARM gem5 Developers                if (checker) {
141510037SARM gem5 Developers                    checker->getITBPtr()->flushAsid(asid,
141610037SARM gem5 Developers                        secure_lookup, target_el);
141710037SARM gem5 Developers                    checker->getDTBPtr()->flushAsid(asid,
141810037SARM gem5 Developers                        secure_lookup, target_el);
141910037SARM gem5 Developers                }
142010037SARM gem5 Developers            }
142110037SARM gem5 Developers            return;
142210037SARM gem5 Developers          // AArch64 TLBI: invalidate by VA, ASID, stage 1, current VMID
142310037SARM gem5 Developers          // VAAE1(IS) and VAALE1(IS) are the same because TLBs only store
142410037SARM gem5 Developers          // entries from the last level of translation table walks
142510037SARM gem5 Developers          // @todo: handle VMID to enable Virtualization
142610037SARM gem5 Developers          case MISCREG_TLBI_VAAE1IS_Xt:
142710037SARM gem5 Developers          case MISCREG_TLBI_VAAE1_Xt:
142810037SARM gem5 Developers          case MISCREG_TLBI_VAALE1IS_Xt:
142910037SARM gem5 Developers          case MISCREG_TLBI_VAALE1_Xt:
143010037SARM gem5 Developers            assert64(tc);
143110037SARM gem5 Developers            target_el = 1; // el 0 and 1 are handled together
143210037SARM gem5 Developers            scr = readMiscReg(MISCREG_SCR, tc);
143310037SARM gem5 Developers            secure_lookup = haveSecurity && !scr.ns;
143410037SARM gem5 Developers            sys = tc->getSystemPtr();
143510037SARM gem5 Developers            for (x = 0; x < sys->numContexts(); x++) {
143610037SARM gem5 Developers                // @todo: extra controls on TLBI broadcast?
143710037SARM gem5 Developers                oc = sys->getThreadContext(x);
143810037SARM gem5 Developers                assert(oc->getITBPtr() && oc->getDTBPtr());
143910037SARM gem5 Developers                Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
144010037SARM gem5 Developers                oc->getITBPtr()->flushMva(va,
144110037SARM gem5 Developers                    secure_lookup, false, target_el);
144210037SARM gem5 Developers                oc->getDTBPtr()->flushMva(va,
144310037SARM gem5 Developers                    secure_lookup, false, target_el);
14448887Sgeoffrey.blake@arm.com
14458887Sgeoffrey.blake@arm.com                CheckerCPU *checker = oc->getCheckerCpuPtr();
14468733Sgeoffrey.blake@arm.com                if (checker) {
144710037SARM gem5 Developers                    checker->getITBPtr()->flushMva(va,
144810037SARM gem5 Developers                        secure_lookup, false, target_el);
144910037SARM gem5 Developers                    checker->getDTBPtr()->flushMva(va,
145010037SARM gem5 Developers                        secure_lookup, false, target_el);
14518733Sgeoffrey.blake@arm.com                }
14528284SAli.Saidi@ARM.com            }
14537408Sgblack@eecs.umich.edu            return;
145410037SARM gem5 Developers          // AArch64 TLBI: invalidate by IPA, stage 2, current VMID
145510037SARM gem5 Developers          case MISCREG_TLBI_IPAS2LE1IS_Xt:
145610037SARM gem5 Developers          case MISCREG_TLBI_IPAS2LE1_Xt:
145710037SARM gem5 Developers          case MISCREG_TLBI_IPAS2E1IS_Xt:
145810037SARM gem5 Developers          case MISCREG_TLBI_IPAS2E1_Xt:
145910037SARM gem5 Developers            assert64(tc);
146010037SARM gem5 Developers            // @todo: implement these as part of Virtualization
146110037SARM gem5 Developers            warn("Not doing anything for write of miscreg ITLB_IPAS2\n");
14627405SAli.Saidi@ARM.com            return;
14637583SAli.Saidi@arm.com          case MISCREG_ACTLR:
14647583SAli.Saidi@arm.com            warn("Not doing anything for write of miscreg ACTLR\n");
14657583SAli.Saidi@arm.com            break;
146610461SAndreas.Sandberg@ARM.com
146710461SAndreas.Sandberg@ARM.com          case MISCREG_PMXEVTYPER_PMCCFILTR:
146810461SAndreas.Sandberg@ARM.com          case MISCREG_PMINTENSET_EL1 ... MISCREG_PMOVSSET_EL0:
146910461SAndreas.Sandberg@ARM.com          case MISCREG_PMEVCNTR0_EL0 ... MISCREG_PMEVTYPER5_EL0:
147010461SAndreas.Sandberg@ARM.com          case MISCREG_PMCR ... MISCREG_PMOVSSET:
147110461SAndreas.Sandberg@ARM.com            pmu->setMiscReg(misc_reg, newVal);
14727583SAli.Saidi@arm.com            break;
147310461SAndreas.Sandberg@ARM.com
147410461SAndreas.Sandberg@ARM.com
147510037SARM gem5 Developers          case MISCREG_HSTR: // TJDBX, now redifined to be RES0
147610037SARM gem5 Developers            {
147710037SARM gem5 Developers                HSTR hstrMask = 0;
147810037SARM gem5 Developers                hstrMask.tjdbx = 1;
147910037SARM gem5 Developers                newVal &= ~((uint32_t) hstrMask);
148010037SARM gem5 Developers                break;
148110037SARM gem5 Developers            }
148210037SARM gem5 Developers          case MISCREG_HCPTR:
148310037SARM gem5 Developers            {
148410037SARM gem5 Developers                // If a CP bit in NSACR is 0 then the corresponding bit in
148510037SARM gem5 Developers                // HCPTR is RAO/WI. Same applies to NSASEDIS
148610037SARM gem5 Developers                secure_lookup = haveSecurity &&
148710037SARM gem5 Developers                    inSecureState(readMiscRegNoEffect(MISCREG_SCR),
148810037SARM gem5 Developers                                  readMiscRegNoEffect(MISCREG_CPSR));
148910037SARM gem5 Developers                if (!secure_lookup) {
149010037SARM gem5 Developers                    MiscReg oldValue = readMiscRegNoEffect(MISCREG_HCPTR);
149110037SARM gem5 Developers                    MiscReg mask = (readMiscRegNoEffect(MISCREG_NSACR) ^ 0x7FFF) & 0xBFFF;
149210037SARM gem5 Developers                    newVal = (newVal & ~mask) | (oldValue & mask);
149310037SARM gem5 Developers                }
149410037SARM gem5 Developers                break;
149510037SARM gem5 Developers            }
149610037SARM gem5 Developers          case MISCREG_HDFAR: // alias for secure DFAR
149710037SARM gem5 Developers            misc_reg = MISCREG_DFAR_S;
149810037SARM gem5 Developers            break;
149910037SARM gem5 Developers          case MISCREG_HIFAR: // alias for secure IFAR
150010037SARM gem5 Developers            misc_reg = MISCREG_IFAR_S;
150110037SARM gem5 Developers            break;
150210037SARM gem5 Developers          case MISCREG_ATS1CPR:
150310037SARM gem5 Developers          case MISCREG_ATS1CPW:
150410037SARM gem5 Developers          case MISCREG_ATS1CUR:
150510037SARM gem5 Developers          case MISCREG_ATS1CUW:
150610037SARM gem5 Developers          case MISCREG_ATS12NSOPR:
150710037SARM gem5 Developers          case MISCREG_ATS12NSOPW:
150810037SARM gem5 Developers          case MISCREG_ATS12NSOUR:
150910037SARM gem5 Developers          case MISCREG_ATS12NSOUW:
151010037SARM gem5 Developers          case MISCREG_ATS1HR:
151110037SARM gem5 Developers          case MISCREG_ATS1HW:
15127436Sdam.sunwoo@arm.com            {
15137436Sdam.sunwoo@arm.com              RequestPtr req = new Request;
151410037SARM gem5 Developers              unsigned flags = 0;
151510037SARM gem5 Developers              BaseTLB::Mode mode = BaseTLB::Read;
151610037SARM gem5 Developers              TLB::ArmTranslationType tranType = TLB::NormalTran;
15177436Sdam.sunwoo@arm.com              Fault fault;
15187436Sdam.sunwoo@arm.com              switch(misc_reg) {
151910037SARM gem5 Developers                case MISCREG_ATS1CPR:
152010037SARM gem5 Developers                  flags    = TLB::MustBeOne;
152110037SARM gem5 Developers                  tranType = TLB::S1CTran;
152210037SARM gem5 Developers                  mode     = BaseTLB::Read;
152310037SARM gem5 Developers                  break;
152410037SARM gem5 Developers                case MISCREG_ATS1CPW:
152510037SARM gem5 Developers                  flags    = TLB::MustBeOne;
152610037SARM gem5 Developers                  tranType = TLB::S1CTran;
152710037SARM gem5 Developers                  mode     = BaseTLB::Write;
152810037SARM gem5 Developers                  break;
152910037SARM gem5 Developers                case MISCREG_ATS1CUR:
153010037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
153110037SARM gem5 Developers                  tranType = TLB::S1CTran;
153210037SARM gem5 Developers                  mode     = BaseTLB::Read;
153310037SARM gem5 Developers                  break;
153410037SARM gem5 Developers                case MISCREG_ATS1CUW:
153510037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
153610037SARM gem5 Developers                  tranType = TLB::S1CTran;
153710037SARM gem5 Developers                  mode     = BaseTLB::Write;
153810037SARM gem5 Developers                  break;
153910037SARM gem5 Developers                case MISCREG_ATS12NSOPR:
154010037SARM gem5 Developers                  if (!haveSecurity)
154110037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOPR");
154210037SARM gem5 Developers                  flags    = TLB::MustBeOne;
154310037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
154410037SARM gem5 Developers                  mode     = BaseTLB::Read;
154510037SARM gem5 Developers                  break;
154610037SARM gem5 Developers                case MISCREG_ATS12NSOPW:
154710037SARM gem5 Developers                  if (!haveSecurity)
154810037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOPW");
154910037SARM gem5 Developers                  flags    = TLB::MustBeOne;
155010037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
155110037SARM gem5 Developers                  mode     = BaseTLB::Write;
155210037SARM gem5 Developers                  break;
155310037SARM gem5 Developers                case MISCREG_ATS12NSOUR:
155410037SARM gem5 Developers                  if (!haveSecurity)
155510037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOUR");
155610037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
155710037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
155810037SARM gem5 Developers                  mode     = BaseTLB::Read;
155910037SARM gem5 Developers                  break;
156010037SARM gem5 Developers                case MISCREG_ATS12NSOUW:
156110037SARM gem5 Developers                  if (!haveSecurity)
156210037SARM gem5 Developers                      panic("Security Extensions required for ATS12NSOUW");
156310037SARM gem5 Developers                  flags    = TLB::MustBeOne | TLB::UserMode;
156410037SARM gem5 Developers                  tranType = TLB::S1S2NsTran;
156510037SARM gem5 Developers                  mode     = BaseTLB::Write;
156610037SARM gem5 Developers                  break;
156710037SARM gem5 Developers                case MISCREG_ATS1HR: // only really useful from secure mode.
156810037SARM gem5 Developers                  flags    = TLB::MustBeOne;
156910037SARM gem5 Developers                  tranType = TLB::HypMode;
157010037SARM gem5 Developers                  mode     = BaseTLB::Read;
157110037SARM gem5 Developers                  break;
157210037SARM gem5 Developers                case MISCREG_ATS1HW:
157310037SARM gem5 Developers                  flags    = TLB::MustBeOne;
157410037SARM gem5 Developers                  tranType = TLB::HypMode;
157510037SARM gem5 Developers                  mode     = BaseTLB::Write;
157610037SARM gem5 Developers                  break;
15777436Sdam.sunwoo@arm.com              }
157810037SARM gem5 Developers              // If we're in timing mode then doing the translation in
157910037SARM gem5 Developers              // functional mode then we're slightly distorting performance
158010037SARM gem5 Developers              // results obtained from simulations. The translation should be
158110037SARM gem5 Developers              // done in the same mode the core is running in. NOTE: This
158210037SARM gem5 Developers              // can't be an atomic translation because that causes problems
158310037SARM gem5 Developers              // with unexpected atomic snoop requests.
158410037SARM gem5 Developers              warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
158510037SARM gem5 Developers              req->setVirt(0, val, 1, flags,  Request::funcMasterId,
158610037SARM gem5 Developers                           tc->pcState().pc());
158710037SARM gem5 Developers              req->setThreadContext(tc->contextId(), tc->threadId());
158810037SARM gem5 Developers              fault = tc->getDTBPtr()->translateFunctional(req, tc, mode, tranType);
158910037SARM gem5 Developers              TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
159010037SARM gem5 Developers              HCR   hcr   = readMiscRegNoEffect(MISCREG_HCR);
159110037SARM gem5 Developers
159210037SARM gem5 Developers              MiscReg newVal;
15937436Sdam.sunwoo@arm.com              if (fault == NoFault) {
159410037SARM gem5 Developers                  Addr paddr = req->getPaddr();
159510037SARM gem5 Developers                  if (haveLPAE && (ttbcr.eae || tranType & TLB::HypMode ||
159610037SARM gem5 Developers                     ((tranType & TLB::S1S2NsTran) && hcr.vm) )) {
159710037SARM gem5 Developers                      newVal = (paddr & mask(39, 12)) |
159810037SARM gem5 Developers                               (tc->getDTBPtr()->getAttr());
159910037SARM gem5 Developers                  } else {
160010037SARM gem5 Developers                      newVal = (paddr & 0xfffff000) |
160110037SARM gem5 Developers                               (tc->getDTBPtr()->getAttr());
160210037SARM gem5 Developers                  }
16037436Sdam.sunwoo@arm.com                  DPRINTF(MiscRegs,
16047436Sdam.sunwoo@arm.com                          "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n",
160510037SARM gem5 Developers                          val, newVal);
160610037SARM gem5 Developers              } else {
160710037SARM gem5 Developers                  ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
160810037SARM gem5 Developers                  // Set fault bit and FSR
160910037SARM gem5 Developers                  FSR fsr = armFault->getFsr(tc);
161010037SARM gem5 Developers
161110037SARM gem5 Developers                  newVal = ((fsr >> 9) & 1) << 11;
161210037SARM gem5 Developers                  if (newVal) {
161310037SARM gem5 Developers                    // LPAE - rearange fault status
161410037SARM gem5 Developers                    newVal |= ((fsr >>  0) & 0x3f) << 1;
161510037SARM gem5 Developers                  } else {
161610037SARM gem5 Developers                    // VMSA - rearange fault status
161710037SARM gem5 Developers                    newVal |= ((fsr >>  0) & 0xf) << 1;
161810037SARM gem5 Developers                    newVal |= ((fsr >> 10) & 0x1) << 5;
161910037SARM gem5 Developers                    newVal |= ((fsr >> 12) & 0x1) << 6;
162010037SARM gem5 Developers                  }
162110037SARM gem5 Developers                  newVal |= 0x1; // F bit
162210037SARM gem5 Developers                  newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
162310037SARM gem5 Developers                  newVal |= armFault->isStage2() ? 0x200 : 0;
162410037SARM gem5 Developers                  DPRINTF(MiscRegs,
162510037SARM gem5 Developers                          "MISCREG: Translated addr 0x%08x fault fsr %#x: PAR: 0x%08x\n",
162610037SARM gem5 Developers                          val, fsr, newVal);
16277436Sdam.sunwoo@arm.com              }
162810037SARM gem5 Developers              delete req;
162910037SARM gem5 Developers              setMiscRegNoEffect(MISCREG_PAR, newVal);
16307436Sdam.sunwoo@arm.com              return;
16317436Sdam.sunwoo@arm.com            }
163210037SARM gem5 Developers          case MISCREG_TTBCR:
163310037SARM gem5 Developers            {
163410037SARM gem5 Developers                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
163510037SARM gem5 Developers                const uint32_t ones = (uint32_t)(-1);
163610037SARM gem5 Developers                TTBCR ttbcrMask = 0;
163710037SARM gem5 Developers                TTBCR ttbcrNew = newVal;
163810037SARM gem5 Developers
163910037SARM gem5 Developers                // ARM DDI 0406C.b, ARMv7-32
164010037SARM gem5 Developers                ttbcrMask.n = ones; // T0SZ
164110037SARM gem5 Developers                if (haveSecurity) {
164210037SARM gem5 Developers                    ttbcrMask.pd0 = ones;
164310037SARM gem5 Developers                    ttbcrMask.pd1 = ones;
164410037SARM gem5 Developers                }
164510037SARM gem5 Developers                ttbcrMask.epd0 = ones;
164610037SARM gem5 Developers                ttbcrMask.irgn0 = ones;
164710037SARM gem5 Developers                ttbcrMask.orgn0 = ones;
164810037SARM gem5 Developers                ttbcrMask.sh0 = ones;
164910037SARM gem5 Developers                ttbcrMask.ps = ones; // T1SZ
165010037SARM gem5 Developers                ttbcrMask.a1 = ones;
165110037SARM gem5 Developers                ttbcrMask.epd1 = ones;
165210037SARM gem5 Developers                ttbcrMask.irgn1 = ones;
165310037SARM gem5 Developers                ttbcrMask.orgn1 = ones;
165410037SARM gem5 Developers                ttbcrMask.sh1 = ones;
165510037SARM gem5 Developers                if (haveLPAE)
165610037SARM gem5 Developers                    ttbcrMask.eae = ones;
165710037SARM gem5 Developers
165810037SARM gem5 Developers                if (haveLPAE && ttbcrNew.eae) {
165910037SARM gem5 Developers                    newVal = newVal & ttbcrMask;
166010037SARM gem5 Developers                } else {
166110037SARM gem5 Developers                    newVal = (newVal & ttbcrMask) | (ttbcr & (~ttbcrMask));
166210037SARM gem5 Developers                }
166310037SARM gem5 Developers            }
166410037SARM gem5 Developers          case MISCREG_TTBR0:
166510037SARM gem5 Developers          case MISCREG_TTBR1:
166610037SARM gem5 Developers            {
166710037SARM gem5 Developers                TTBCR ttbcr = readMiscRegNoEffect(MISCREG_TTBCR);
166810037SARM gem5 Developers                if (haveLPAE) {
166910037SARM gem5 Developers                    if (ttbcr.eae) {
167010037SARM gem5 Developers                        // ARMv7 bit 63-56, 47-40 reserved, UNK/SBZP
167110037SARM gem5 Developers                        // ARMv8 AArch32 bit 63-56 only
167210037SARM gem5 Developers                        uint64_t ttbrMask = mask(63,56) | mask(47,40);
167310037SARM gem5 Developers                        newVal = (newVal & (~ttbrMask));
167410037SARM gem5 Developers                    }
167510037SARM gem5 Developers                }
167610037SARM gem5 Developers            }
16777749SAli.Saidi@ARM.com          case MISCREG_CONTEXTIDR:
16787749SAli.Saidi@ARM.com          case MISCREG_PRRR:
16797749SAli.Saidi@ARM.com          case MISCREG_NMRR:
168010037SARM gem5 Developers          case MISCREG_MAIR0:
168110037SARM gem5 Developers          case MISCREG_MAIR1:
16827749SAli.Saidi@ARM.com          case MISCREG_DACR:
168310037SARM gem5 Developers          case MISCREG_VTTBR:
168410037SARM gem5 Developers          case MISCREG_SCR_EL3:
168510037SARM gem5 Developers          case MISCREG_SCTLR_EL1:
168610037SARM gem5 Developers          case MISCREG_SCTLR_EL2:
168710037SARM gem5 Developers          case MISCREG_SCTLR_EL3:
168810037SARM gem5 Developers          case MISCREG_TCR_EL1:
168910037SARM gem5 Developers          case MISCREG_TCR_EL2:
169010037SARM gem5 Developers          case MISCREG_TCR_EL3:
169110037SARM gem5 Developers          case MISCREG_TTBR0_EL1:
169210037SARM gem5 Developers          case MISCREG_TTBR1_EL1:
169310037SARM gem5 Developers          case MISCREG_TTBR0_EL2:
169410037SARM gem5 Developers          case MISCREG_TTBR0_EL3:
16957749SAli.Saidi@ARM.com            tc->getITBPtr()->invalidateMiscReg();
16967749SAli.Saidi@ARM.com            tc->getDTBPtr()->invalidateMiscReg();
16977749SAli.Saidi@ARM.com            break;
169810037SARM gem5 Developers          case MISCREG_NZCV:
169910037SARM gem5 Developers            {
170010037SARM gem5 Developers                CPSR cpsr = val;
170110037SARM gem5 Developers
170210338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_NZ, cpsr.nz);
170310338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_C,  cpsr.c);
170410338SCurtis.Dunham@arm.com                tc->setCCReg(CCREG_V,  cpsr.v);
170510037SARM gem5 Developers            }
170610037SARM gem5 Developers            break;
170710037SARM gem5 Developers          case MISCREG_DAIF:
170810037SARM gem5 Developers            {
170910037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
171010037SARM gem5 Developers                cpsr.daif = (uint8_t) ((CPSR) newVal).daif;
171110037SARM gem5 Developers                newVal = cpsr;
171210037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
171310037SARM gem5 Developers            }
171410037SARM gem5 Developers            break;
171510037SARM gem5 Developers          case MISCREG_SP_EL0:
171610037SARM gem5 Developers            tc->setIntReg(INTREG_SP0, newVal);
171710037SARM gem5 Developers            break;
171810037SARM gem5 Developers          case MISCREG_SP_EL1:
171910037SARM gem5 Developers            tc->setIntReg(INTREG_SP1, newVal);
172010037SARM gem5 Developers            break;
172110037SARM gem5 Developers          case MISCREG_SP_EL2:
172210037SARM gem5 Developers            tc->setIntReg(INTREG_SP2, newVal);
172310037SARM gem5 Developers            break;
172410037SARM gem5 Developers          case MISCREG_SPSEL:
172510037SARM gem5 Developers            {
172610037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
172710037SARM gem5 Developers                cpsr.sp = (uint8_t) ((CPSR) newVal).sp;
172810037SARM gem5 Developers                newVal = cpsr;
172910037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
173010037SARM gem5 Developers            }
173110037SARM gem5 Developers            break;
173210037SARM gem5 Developers          case MISCREG_CURRENTEL:
173310037SARM gem5 Developers            {
173410037SARM gem5 Developers                CPSR cpsr = miscRegs[MISCREG_CPSR];
173510037SARM gem5 Developers                cpsr.el = (uint8_t) ((CPSR) newVal).el;
173610037SARM gem5 Developers                newVal = cpsr;
173710037SARM gem5 Developers                misc_reg = MISCREG_CPSR;
173810037SARM gem5 Developers            }
173910037SARM gem5 Developers            break;
174010037SARM gem5 Developers          case MISCREG_AT_S1E1R_Xt:
174110037SARM gem5 Developers          case MISCREG_AT_S1E1W_Xt:
174210037SARM gem5 Developers          case MISCREG_AT_S1E0R_Xt:
174310037SARM gem5 Developers          case MISCREG_AT_S1E0W_Xt:
174410037SARM gem5 Developers          case MISCREG_AT_S1E2R_Xt:
174510037SARM gem5 Developers          case MISCREG_AT_S1E2W_Xt:
174610037SARM gem5 Developers          case MISCREG_AT_S12E1R_Xt:
174710037SARM gem5 Developers          case MISCREG_AT_S12E1W_Xt:
174810037SARM gem5 Developers          case MISCREG_AT_S12E0R_Xt:
174910037SARM gem5 Developers          case MISCREG_AT_S12E0W_Xt:
175010037SARM gem5 Developers          case MISCREG_AT_S1E3R_Xt:
175110037SARM gem5 Developers          case MISCREG_AT_S1E3W_Xt:
175210037SARM gem5 Developers            {
175310037SARM gem5 Developers                RequestPtr req = new Request;
175410037SARM gem5 Developers                unsigned flags = 0;
175510037SARM gem5 Developers                BaseTLB::Mode mode = BaseTLB::Read;
175610037SARM gem5 Developers                TLB::ArmTranslationType tranType = TLB::NormalTran;
175710037SARM gem5 Developers                Fault fault;
175810037SARM gem5 Developers                switch(misc_reg) {
175910037SARM gem5 Developers                  case MISCREG_AT_S1E1R_Xt:
176010037SARM gem5 Developers                    flags    = TLB::MustBeOne;
176110037SARM gem5 Developers                    tranType = TLB::S1CTran;
176210037SARM gem5 Developers                    mode     = BaseTLB::Read;
176310037SARM gem5 Developers                    break;
176410037SARM gem5 Developers                  case MISCREG_AT_S1E1W_Xt:
176510037SARM gem5 Developers                    flags    = TLB::MustBeOne;
176610037SARM gem5 Developers                    tranType = TLB::S1CTran;
176710037SARM gem5 Developers                    mode     = BaseTLB::Write;
176810037SARM gem5 Developers                    break;
176910037SARM gem5 Developers                  case MISCREG_AT_S1E0R_Xt:
177010037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
177110037SARM gem5 Developers                    tranType = TLB::S1CTran;
177210037SARM gem5 Developers                    mode     = BaseTLB::Read;
177310037SARM gem5 Developers                    break;
177410037SARM gem5 Developers                  case MISCREG_AT_S1E0W_Xt:
177510037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
177610037SARM gem5 Developers                    tranType = TLB::S1CTran;
177710037SARM gem5 Developers                    mode     = BaseTLB::Write;
177810037SARM gem5 Developers                    break;
177910037SARM gem5 Developers                  case MISCREG_AT_S1E2R_Xt:
178010037SARM gem5 Developers                    flags    = TLB::MustBeOne;
178110037SARM gem5 Developers                    tranType = TLB::HypMode;
178210037SARM gem5 Developers                    mode     = BaseTLB::Read;
178310037SARM gem5 Developers                    break;
178410037SARM gem5 Developers                  case MISCREG_AT_S1E2W_Xt:
178510037SARM gem5 Developers                    flags    = TLB::MustBeOne;
178610037SARM gem5 Developers                    tranType = TLB::HypMode;
178710037SARM gem5 Developers                    mode     = BaseTLB::Write;
178810037SARM gem5 Developers                    break;
178910037SARM gem5 Developers                  case MISCREG_AT_S12E0R_Xt:
179010037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
179110037SARM gem5 Developers                    tranType = TLB::S1S2NsTran;
179210037SARM gem5 Developers                    mode     = BaseTLB::Read;
179310037SARM gem5 Developers                    break;
179410037SARM gem5 Developers                  case MISCREG_AT_S12E0W_Xt:
179510037SARM gem5 Developers                    flags    = TLB::MustBeOne | TLB::UserMode;
179610037SARM gem5 Developers                    tranType = TLB::S1S2NsTran;
179710037SARM gem5 Developers                    mode     = BaseTLB::Write;
179810037SARM gem5 Developers                    break;
179910037SARM gem5 Developers                  case MISCREG_AT_S12E1R_Xt:
180010037SARM gem5 Developers                    flags    = TLB::MustBeOne;
180110037SARM gem5 Developers                    tranType = TLB::S1S2NsTran;
180210037SARM gem5 Developers                    mode     = BaseTLB::Read;
180310037SARM gem5 Developers                    break;
180410037SARM gem5 Developers                  case MISCREG_AT_S12E1W_Xt:
180510037SARM gem5 Developers                    flags    = TLB::MustBeOne;
180610037SARM gem5 Developers                    tranType = TLB::S1S2NsTran;
180710037SARM gem5 Developers                    mode     = BaseTLB::Write;
180810037SARM gem5 Developers                    break;
180910037SARM gem5 Developers                  case MISCREG_AT_S1E3R_Xt:
181010037SARM gem5 Developers                    flags    = TLB::MustBeOne;
181110037SARM gem5 Developers                    tranType = TLB::HypMode; // There is no TZ mode defined.
181210037SARM gem5 Developers                    mode     = BaseTLB::Read;
181310037SARM gem5 Developers                    break;
181410037SARM gem5 Developers                  case MISCREG_AT_S1E3W_Xt:
181510037SARM gem5 Developers                    flags    = TLB::MustBeOne;
181610037SARM gem5 Developers                    tranType = TLB::HypMode; // There is no TZ mode defined.
181710037SARM gem5 Developers                    mode     = BaseTLB::Write;
181810037SARM gem5 Developers                    break;
181910037SARM gem5 Developers                }
182010037SARM gem5 Developers                // If we're in timing mode then doing the translation in
182110037SARM gem5 Developers                // functional mode then we're slightly distorting performance
182210037SARM gem5 Developers                // results obtained from simulations. The translation should be
182310037SARM gem5 Developers                // done in the same mode the core is running in. NOTE: This
182410037SARM gem5 Developers                // can't be an atomic translation because that causes problems
182510037SARM gem5 Developers                // with unexpected atomic snoop requests.
182610037SARM gem5 Developers                warn("Translating via MISCREG(%d) in functional mode! Fix Me!\n", misc_reg);
182710037SARM gem5 Developers                req->setVirt(0, val, 1, flags,  Request::funcMasterId,
182810037SARM gem5 Developers                               tc->pcState().pc());
182910037SARM gem5 Developers                req->setThreadContext(tc->contextId(), tc->threadId());
183010037SARM gem5 Developers                fault = tc->getDTBPtr()->translateFunctional(req, tc, mode,
183110037SARM gem5 Developers                                                             tranType);
183210037SARM gem5 Developers
183310037SARM gem5 Developers                MiscReg newVal;
183410037SARM gem5 Developers                if (fault == NoFault) {
183510037SARM gem5 Developers                    Addr paddr = req->getPaddr();
183610037SARM gem5 Developers                    uint64_t attr = tc->getDTBPtr()->getAttr();
183710037SARM gem5 Developers                    uint64_t attr1 = attr >> 56;
183810037SARM gem5 Developers                    if (!attr1 || attr1 ==0x44) {
183910037SARM gem5 Developers                        attr |= 0x100;
184010037SARM gem5 Developers                        attr &= ~ uint64_t(0x80);
184110037SARM gem5 Developers                    }
184210037SARM gem5 Developers                    newVal = (paddr & mask(47, 12)) | attr;
184310037SARM gem5 Developers                    DPRINTF(MiscRegs,
184410037SARM gem5 Developers                          "MISCREG: Translated addr %#x: PAR_EL1: %#xx\n",
184510037SARM gem5 Developers                          val, newVal);
184610037SARM gem5 Developers                } else {
184710037SARM gem5 Developers                    ArmFault *armFault = reinterpret_cast<ArmFault *>(fault.get());
184810037SARM gem5 Developers                    // Set fault bit and FSR
184910037SARM gem5 Developers                    FSR fsr = armFault->getFsr(tc);
185010037SARM gem5 Developers
185110037SARM gem5 Developers                    newVal = ((fsr >> 9) & 1) << 11;
185210037SARM gem5 Developers                    // rearange fault status
185310037SARM gem5 Developers                    newVal |= ((fsr >>  0) & 0x3f) << 1;
185410037SARM gem5 Developers                    newVal |= 0x1; // F bit
185510037SARM gem5 Developers                    newVal |= ((armFault->iss() >> 7) & 0x1) << 8;
185610037SARM gem5 Developers                    newVal |= armFault->isStage2() ? 0x200 : 0;
185710037SARM gem5 Developers                    DPRINTF(MiscRegs,
185810037SARM gem5 Developers                            "MISCREG: Translated addr %#x fault fsr %#x: PAR: %#x\n",
185910037SARM gem5 Developers                            val, fsr, newVal);
186010037SARM gem5 Developers                }
186110037SARM gem5 Developers                delete req;
186210037SARM gem5 Developers                setMiscRegNoEffect(MISCREG_PAR_EL1, newVal);
186310037SARM gem5 Developers                return;
186410037SARM gem5 Developers            }
186510037SARM gem5 Developers          case MISCREG_SPSR_EL3:
186610037SARM gem5 Developers          case MISCREG_SPSR_EL2:
186710037SARM gem5 Developers          case MISCREG_SPSR_EL1:
186810037SARM gem5 Developers            // Force bits 23:21 to 0
186910037SARM gem5 Developers            newVal = val & ~(0x7 << 21);
187010037SARM gem5 Developers            break;
18718549Sdaniel.johnson@arm.com          case MISCREG_L2CTLR:
18728549Sdaniel.johnson@arm.com            warn("miscreg L2CTLR (%s) written with %#x. ignored...\n",
18738549Sdaniel.johnson@arm.com                 miscRegName[misc_reg], uint32_t(val));
187410037SARM gem5 Developers            break;
187510037SARM gem5 Developers
187610037SARM gem5 Developers          // Generic Timer registers
187710037SARM gem5 Developers          case MISCREG_CNTFRQ:
187810037SARM gem5 Developers          case MISCREG_CNTFRQ_EL0:
187910037SARM gem5 Developers            getSystemCounter(tc)->setFreq(val);
188010037SARM gem5 Developers            break;
188110037SARM gem5 Developers          case MISCREG_CNTP_CVAL:
188210037SARM gem5 Developers          case MISCREG_CNTP_CVAL_EL0:
188310037SARM gem5 Developers            getArchTimer(tc, tc->cpuId())->setCompareValue(val);
188410037SARM gem5 Developers            break;
188510037SARM gem5 Developers          case MISCREG_CNTP_TVAL:
188610037SARM gem5 Developers          case MISCREG_CNTP_TVAL_EL0:
188710037SARM gem5 Developers            getArchTimer(tc, tc->cpuId())->setTimerValue(val);
188810037SARM gem5 Developers            break;
188910037SARM gem5 Developers          case MISCREG_CNTP_CTL:
189010037SARM gem5 Developers          case MISCREG_CNTP_CTL_EL0:
189110037SARM gem5 Developers            getArchTimer(tc, tc->cpuId())->setControl(val);
189210037SARM gem5 Developers            break;
189310037SARM gem5 Developers          // PL1 phys. timer, secure
189410037SARM gem5 Developers          //   AArch64
189510037SARM gem5 Developers          case MISCREG_CNTPS_CVAL_EL1:
189610037SARM gem5 Developers          case MISCREG_CNTPS_TVAL_EL1:
189710037SARM gem5 Developers          case MISCREG_CNTPS_CTL_EL1:
189810037SARM gem5 Developers          // PL2 phys. timer, non-secure
189910037SARM gem5 Developers          //   AArch32
190010037SARM gem5 Developers          case MISCREG_CNTHCTL:
190110037SARM gem5 Developers          case MISCREG_CNTHP_CVAL:
190210037SARM gem5 Developers          case MISCREG_CNTHP_TVAL:
190310037SARM gem5 Developers          case MISCREG_CNTHP_CTL:
190410037SARM gem5 Developers          //   AArch64
190510037SARM gem5 Developers          case MISCREG_CNTHCTL_EL2:
190610037SARM gem5 Developers          case MISCREG_CNTHP_CVAL_EL2:
190710037SARM gem5 Developers          case MISCREG_CNTHP_TVAL_EL2:
190810037SARM gem5 Developers          case MISCREG_CNTHP_CTL_EL2:
190910037SARM gem5 Developers          // Virtual timer
191010037SARM gem5 Developers          //   AArch32
191110037SARM gem5 Developers          case MISCREG_CNTV_CVAL:
191210037SARM gem5 Developers          case MISCREG_CNTV_TVAL:
191310037SARM gem5 Developers          case MISCREG_CNTV_CTL:
191410037SARM gem5 Developers          //   AArch64
191510037SARM gem5 Developers          // case MISCREG_CNTV_CVAL_EL2:
191610037SARM gem5 Developers          // case MISCREG_CNTV_TVAL_EL2:
191710037SARM gem5 Developers          // case MISCREG_CNTV_CTL_EL2:
191810037SARM gem5 Developers            break;
19197405SAli.Saidi@ARM.com        }
19207405SAli.Saidi@ARM.com    }
19217405SAli.Saidi@ARM.com    setMiscRegNoEffect(misc_reg, newVal);
19227405SAli.Saidi@ARM.com}
19237405SAli.Saidi@ARM.com
192410037SARM gem5 Developersvoid
192510037SARM gem5 DevelopersISA::tlbiVA(ThreadContext *tc, MiscReg newVal, uint8_t asid, bool secure_lookup,
192610037SARM gem5 Developers            uint8_t target_el)
192710037SARM gem5 Developers{
192810037SARM gem5 Developers    if (haveLargeAsid64)
192910037SARM gem5 Developers        asid &= mask(8);
193010037SARM gem5 Developers    Addr va = ((Addr) bits(newVal, 43, 0)) << 12;
193110037SARM gem5 Developers    System *sys = tc->getSystemPtr();
193210037SARM gem5 Developers    for (int x = 0; x < sys->numContexts(); x++) {
193310037SARM gem5 Developers        ThreadContext *oc = sys->getThreadContext(x);
193410037SARM gem5 Developers        assert(oc->getITBPtr() && oc->getDTBPtr());
193510037SARM gem5 Developers        oc->getITBPtr()->flushMvaAsid(va, asid,
193610037SARM gem5 Developers                                      secure_lookup, target_el);
193710037SARM gem5 Developers        oc->getDTBPtr()->flushMvaAsid(va, asid,
193810037SARM gem5 Developers                                      secure_lookup, target_el);
193910037SARM gem5 Developers
194010037SARM gem5 Developers        CheckerCPU *checker = oc->getCheckerCpuPtr();
194110037SARM gem5 Developers        if (checker) {
194210037SARM gem5 Developers            checker->getITBPtr()->flushMvaAsid(
194310037SARM gem5 Developers                va, asid, secure_lookup, target_el);
194410037SARM gem5 Developers            checker->getDTBPtr()->flushMvaAsid(
194510037SARM gem5 Developers                va, asid, secure_lookup, target_el);
194610037SARM gem5 Developers        }
194710037SARM gem5 Developers    }
194810037SARM gem5 Developers}
194910037SARM gem5 Developers
195010037SARM gem5 Developersvoid
195110037SARM gem5 DevelopersISA::tlbiALL(ThreadContext *tc, bool secure_lookup, uint8_t target_el)
195210037SARM gem5 Developers{
195310037SARM gem5 Developers    System *sys = tc->getSystemPtr();
195410037SARM gem5 Developers    for (int x = 0; x < sys->numContexts(); x++) {
195510037SARM gem5 Developers        ThreadContext *oc = sys->getThreadContext(x);
195610037SARM gem5 Developers        assert(oc->getITBPtr() && oc->getDTBPtr());
195710037SARM gem5 Developers        oc->getITBPtr()->flushAllSecurity(secure_lookup, target_el);
195810037SARM gem5 Developers        oc->getDTBPtr()->flushAllSecurity(secure_lookup, target_el);
195910037SARM gem5 Developers
196010037SARM gem5 Developers        // If CheckerCPU is connected, need to notify it of a flush
196110037SARM gem5 Developers        CheckerCPU *checker = oc->getCheckerCpuPtr();
196210037SARM gem5 Developers        if (checker) {
196310037SARM gem5 Developers            checker->getITBPtr()->flushAllSecurity(secure_lookup,
196410037SARM gem5 Developers                                                   target_el);
196510037SARM gem5 Developers            checker->getDTBPtr()->flushAllSecurity(secure_lookup,
196610037SARM gem5 Developers                                                   target_el);
196710037SARM gem5 Developers        }
196810037SARM gem5 Developers    }
196910037SARM gem5 Developers}
197010037SARM gem5 Developers
197110037SARM gem5 Developersvoid
197210037SARM gem5 DevelopersISA::tlbiALLN(ThreadContext *tc, bool hyp, uint8_t target_el)
197310037SARM gem5 Developers{
197410037SARM gem5 Developers    System *sys = tc->getSystemPtr();
197510037SARM gem5 Developers    for (int x = 0; x < sys->numContexts(); x++) {
197610037SARM gem5 Developers      ThreadContext *oc = sys->getThreadContext(x);
197710037SARM gem5 Developers      assert(oc->getITBPtr() && oc->getDTBPtr());
197810037SARM gem5 Developers      oc->getITBPtr()->flushAllNs(hyp, target_el);
197910037SARM gem5 Developers      oc->getDTBPtr()->flushAllNs(hyp, target_el);
198010037SARM gem5 Developers
198110037SARM gem5 Developers      CheckerCPU *checker = oc->getCheckerCpuPtr();
198210037SARM gem5 Developers      if (checker) {
198310037SARM gem5 Developers          checker->getITBPtr()->flushAllNs(hyp, target_el);
198410037SARM gem5 Developers          checker->getDTBPtr()->flushAllNs(hyp, target_el);
198510037SARM gem5 Developers      }
198610037SARM gem5 Developers    }
198710037SARM gem5 Developers}
198810037SARM gem5 Developers
198910037SARM gem5 Developersvoid
199010037SARM gem5 DevelopersISA::tlbiMVA(ThreadContext *tc, MiscReg newVal, bool secure_lookup, bool hyp,
199110037SARM gem5 Developers             uint8_t target_el)
199210037SARM gem5 Developers{
199310037SARM gem5 Developers    System *sys = tc->getSystemPtr();
199410037SARM gem5 Developers    for (int x = 0; x < sys->numContexts(); x++) {
199510037SARM gem5 Developers        ThreadContext *oc = sys->getThreadContext(x);
199610037SARM gem5 Developers        assert(oc->getITBPtr() && oc->getDTBPtr());
199710037SARM gem5 Developers        oc->getITBPtr()->flushMva(mbits(newVal, 31,12),
199810037SARM gem5 Developers            secure_lookup, hyp, target_el);
199910037SARM gem5 Developers        oc->getDTBPtr()->flushMva(mbits(newVal, 31,12),
200010037SARM gem5 Developers            secure_lookup, hyp, target_el);
200110037SARM gem5 Developers
200210037SARM gem5 Developers        CheckerCPU *checker = oc->getCheckerCpuPtr();
200310037SARM gem5 Developers        if (checker) {
200410037SARM gem5 Developers            checker->getITBPtr()->flushMva(mbits(newVal, 31,12),
200510037SARM gem5 Developers                secure_lookup, hyp, target_el);
200610037SARM gem5 Developers            checker->getDTBPtr()->flushMva(mbits(newVal, 31,12),
200710037SARM gem5 Developers                secure_lookup, hyp, target_el);
200810037SARM gem5 Developers        }
200910037SARM gem5 Developers    }
201010037SARM gem5 Developers}
201110037SARM gem5 Developers
201210037SARM gem5 Developers::GenericTimer::SystemCounter *
201310037SARM gem5 DevelopersISA::getSystemCounter(ThreadContext *tc)
201410037SARM gem5 Developers{
201510037SARM gem5 Developers    ::GenericTimer::SystemCounter *cnt = ((ArmSystem *) tc->getSystemPtr())->
201610037SARM gem5 Developers        getSystemCounter();
201710037SARM gem5 Developers    if (cnt == NULL) {
201810037SARM gem5 Developers        panic("System counter not available\n");
201910037SARM gem5 Developers    }
202010037SARM gem5 Developers    return cnt;
202110037SARM gem5 Developers}
202210037SARM gem5 Developers
202310037SARM gem5 Developers::GenericTimer::ArchTimer *
202410037SARM gem5 DevelopersISA::getArchTimer(ThreadContext *tc, int cpu_id)
202510037SARM gem5 Developers{
202610037SARM gem5 Developers    ::GenericTimer::ArchTimer *timer = ((ArmSystem *) tc->getSystemPtr())->
202710037SARM gem5 Developers        getArchTimer(cpu_id);
202810037SARM gem5 Developers    if (timer == NULL) {
202910037SARM gem5 Developers        panic("Architected timer not available\n");
203010037SARM gem5 Developers    }
203110037SARM gem5 Developers    return timer;
203210037SARM gem5 Developers}
203310037SARM gem5 Developers
20347405SAli.Saidi@ARM.com}
20359384SAndreas.Sandberg@arm.com
20369384SAndreas.Sandberg@arm.comArmISA::ISA *
20379384SAndreas.Sandberg@arm.comArmISAParams::create()
20389384SAndreas.Sandberg@arm.com{
20399384SAndreas.Sandberg@arm.com    return new ArmISA::ISA(this);
20409384SAndreas.Sandberg@arm.com}
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