isa.cc revision 10035
17405SAli.Saidi@ARM.com/* 29814Sandreas.hansson@arm.com * Copyright (c) 2010-2013 ARM Limited 37405SAli.Saidi@ARM.com * All rights reserved 47405SAli.Saidi@ARM.com * 57405SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67405SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77405SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87405SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97405SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107405SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117405SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127405SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137405SAli.Saidi@ARM.com * 147405SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 157405SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 167405SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 177405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 187405SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 197405SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 207405SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 217405SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 227405SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 237405SAli.Saidi@ARM.com * this software without specific prior written permission. 247405SAli.Saidi@ARM.com * 257405SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 267405SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 277405SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 287405SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 297405SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 307405SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 317405SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 327405SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 337405SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 347405SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 357405SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 367405SAli.Saidi@ARM.com * 377405SAli.Saidi@ARM.com * Authors: Gabe Black 387405SAli.Saidi@ARM.com * Ali Saidi 397405SAli.Saidi@ARM.com */ 407405SAli.Saidi@ARM.com 417405SAli.Saidi@ARM.com#include "arch/arm/isa.hh" 429050Schander.sudanthi@arm.com#include "arch/arm/system.hh" 438887Sgeoffrey.blake@arm.com#include "cpu/checker/cpu.hh" 448232Snate@binkert.org#include "debug/Arm.hh" 458232Snate@binkert.org#include "debug/MiscRegs.hh" 469384SAndreas.Sandberg@arm.com#include "params/ArmISA.hh" 477678Sgblack@eecs.umich.edu#include "sim/faults.hh" 488059SAli.Saidi@ARM.com#include "sim/stat_control.hh" 498284SAli.Saidi@ARM.com#include "sim/system.hh" 507405SAli.Saidi@ARM.com 517405SAli.Saidi@ARM.comnamespace ArmISA 527405SAli.Saidi@ARM.com{ 537405SAli.Saidi@ARM.com 549384SAndreas.Sandberg@arm.comISA::ISA(Params *p) 559384SAndreas.Sandberg@arm.com : SimObject(p) 569384SAndreas.Sandberg@arm.com{ 579384SAndreas.Sandberg@arm.com SCTLR sctlr; 589384SAndreas.Sandberg@arm.com sctlr = 0; 599384SAndreas.Sandberg@arm.com miscRegs[MISCREG_SCTLR_RST] = sctlr; 609384SAndreas.Sandberg@arm.com clear(); 619384SAndreas.Sandberg@arm.com} 629384SAndreas.Sandberg@arm.com 639384SAndreas.Sandberg@arm.comconst ArmISAParams * 649384SAndreas.Sandberg@arm.comISA::params() const 659384SAndreas.Sandberg@arm.com{ 669384SAndreas.Sandberg@arm.com return dynamic_cast<const Params *>(_params); 679384SAndreas.Sandberg@arm.com} 689384SAndreas.Sandberg@arm.com 697427Sgblack@eecs.umich.eduvoid 707427Sgblack@eecs.umich.eduISA::clear() 717427Sgblack@eecs.umich.edu{ 729385SAndreas.Sandberg@arm.com const Params *p(params()); 739385SAndreas.Sandberg@arm.com 747427Sgblack@eecs.umich.edu SCTLR sctlr_rst = miscRegs[MISCREG_SCTLR_RST]; 757427Sgblack@eecs.umich.edu memset(miscRegs, 0, sizeof(miscRegs)); 767427Sgblack@eecs.umich.edu CPSR cpsr = 0; 777427Sgblack@eecs.umich.edu cpsr.mode = MODE_USER; 787427Sgblack@eecs.umich.edu miscRegs[MISCREG_CPSR] = cpsr; 797427Sgblack@eecs.umich.edu updateRegMap(cpsr); 807427Sgblack@eecs.umich.edu 817427Sgblack@eecs.umich.edu SCTLR sctlr = 0; 827604SGene.Wu@arm.com sctlr.te = (bool)sctlr_rst.te; 837427Sgblack@eecs.umich.edu sctlr.nmfi = (bool)sctlr_rst.nmfi; 847427Sgblack@eecs.umich.edu sctlr.v = (bool)sctlr_rst.v; 857427Sgblack@eecs.umich.edu sctlr.u = 1; 867427Sgblack@eecs.umich.edu sctlr.xp = 1; 877427Sgblack@eecs.umich.edu sctlr.rao2 = 1; 887427Sgblack@eecs.umich.edu sctlr.rao3 = 1; 897427Sgblack@eecs.umich.edu sctlr.rao4 = 1; 907427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = sctlr; 917427Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR_RST] = sctlr_rst; 927427Sgblack@eecs.umich.edu 937427Sgblack@eecs.umich.edu /* Start with an event in the mailbox */ 947427Sgblack@eecs.umich.edu miscRegs[MISCREG_SEV_MAILBOX] = 1; 957427Sgblack@eecs.umich.edu 967427Sgblack@eecs.umich.edu // Separate Instruction and Data TLBs. 977427Sgblack@eecs.umich.edu miscRegs[MISCREG_TLBTR] = 1; 987427Sgblack@eecs.umich.edu 997427Sgblack@eecs.umich.edu MVFR0 mvfr0 = 0; 1007427Sgblack@eecs.umich.edu mvfr0.advSimdRegisters = 2; 1017427Sgblack@eecs.umich.edu mvfr0.singlePrecision = 2; 1027427Sgblack@eecs.umich.edu mvfr0.doublePrecision = 2; 1037427Sgblack@eecs.umich.edu mvfr0.vfpExceptionTrapping = 0; 1047427Sgblack@eecs.umich.edu mvfr0.divide = 1; 1057427Sgblack@eecs.umich.edu mvfr0.squareRoot = 1; 1067427Sgblack@eecs.umich.edu mvfr0.shortVectors = 1; 1077427Sgblack@eecs.umich.edu mvfr0.roundingModes = 1; 1087427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR0] = mvfr0; 1097427Sgblack@eecs.umich.edu 1107427Sgblack@eecs.umich.edu MVFR1 mvfr1 = 0; 1117427Sgblack@eecs.umich.edu mvfr1.flushToZero = 1; 1127427Sgblack@eecs.umich.edu mvfr1.defaultNaN = 1; 1137427Sgblack@eecs.umich.edu mvfr1.advSimdLoadStore = 1; 1147427Sgblack@eecs.umich.edu mvfr1.advSimdInteger = 1; 1157427Sgblack@eecs.umich.edu mvfr1.advSimdSinglePrecision = 1; 1167427Sgblack@eecs.umich.edu mvfr1.advSimdHalfPrecision = 1; 1177427Sgblack@eecs.umich.edu mvfr1.vfpHalfPrecision = 1; 1187427Sgblack@eecs.umich.edu miscRegs[MISCREG_MVFR1] = mvfr1; 1197427Sgblack@eecs.umich.edu 1207436Sdam.sunwoo@arm.com // Reset values of PRRR and NMRR are implementation dependent 1217436Sdam.sunwoo@arm.com 1227436Sdam.sunwoo@arm.com miscRegs[MISCREG_PRRR] = 1237436Sdam.sunwoo@arm.com (1 << 19) | // 19 1247436Sdam.sunwoo@arm.com (0 << 18) | // 18 1257436Sdam.sunwoo@arm.com (0 << 17) | // 17 1267436Sdam.sunwoo@arm.com (1 << 16) | // 16 1277436Sdam.sunwoo@arm.com (2 << 14) | // 15:14 1287436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1297436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1307436Sdam.sunwoo@arm.com (2 << 8) | // 9:8 1317436Sdam.sunwoo@arm.com (2 << 6) | // 7:6 1327436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1337436Sdam.sunwoo@arm.com (1 << 2) | // 3:2 1347436Sdam.sunwoo@arm.com 0; // 1:0 1357436Sdam.sunwoo@arm.com miscRegs[MISCREG_NMRR] = 1367436Sdam.sunwoo@arm.com (1 << 30) | // 31:30 1377436Sdam.sunwoo@arm.com (0 << 26) | // 27:26 1387436Sdam.sunwoo@arm.com (0 << 24) | // 25:24 1397436Sdam.sunwoo@arm.com (3 << 22) | // 23:22 1407436Sdam.sunwoo@arm.com (2 << 20) | // 21:20 1417436Sdam.sunwoo@arm.com (0 << 18) | // 19:18 1427436Sdam.sunwoo@arm.com (0 << 16) | // 17:16 1437436Sdam.sunwoo@arm.com (1 << 14) | // 15:14 1447436Sdam.sunwoo@arm.com (0 << 12) | // 13:12 1457436Sdam.sunwoo@arm.com (2 << 10) | // 11:10 1467436Sdam.sunwoo@arm.com (0 << 8) | // 9:8 1477436Sdam.sunwoo@arm.com (3 << 6) | // 7:6 1487436Sdam.sunwoo@arm.com (2 << 4) | // 5:4 1497436Sdam.sunwoo@arm.com (0 << 2) | // 3:2 1507436Sdam.sunwoo@arm.com 0; // 1:0 1517436Sdam.sunwoo@arm.com 1527644Sali.saidi@arm.com miscRegs[MISCREG_CPACR] = 0; 1538147SAli.Saidi@ARM.com 1549385SAndreas.Sandberg@arm.com // Initialize configurable default values 1559385SAndreas.Sandberg@arm.com miscRegs[MISCREG_MIDR] = p->midr; 1569385SAndreas.Sandberg@arm.com 1579385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_PFR0] = p->id_pfr0; 1589385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_PFR1] = p->id_pfr1; 1599385SAndreas.Sandberg@arm.com 1609385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR0] = p->id_mmfr0; 1619385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR1] = p->id_mmfr1; 1629385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR2] = p->id_mmfr2; 1639385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_MMFR3] = p->id_mmfr3; 1649385SAndreas.Sandberg@arm.com 1659385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR0] = p->id_isar0; 1669385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR1] = p->id_isar1; 1679385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR2] = p->id_isar2; 1689385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR3] = p->id_isar3; 1699385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR4] = p->id_isar4; 1709385SAndreas.Sandberg@arm.com miscRegs[MISCREG_ID_ISAR5] = p->id_isar5; 1719385SAndreas.Sandberg@arm.com 1729385SAndreas.Sandberg@arm.com 1739385SAndreas.Sandberg@arm.com miscRegs[MISCREG_FPSID] = p->fpsid; 1749385SAndreas.Sandberg@arm.com 1758147SAli.Saidi@ARM.com 1767427Sgblack@eecs.umich.edu //XXX We need to initialize the rest of the state. 1777427Sgblack@eecs.umich.edu} 1787427Sgblack@eecs.umich.edu 1797405SAli.Saidi@ARM.comMiscReg 18010035Sandreas.hansson@arm.comISA::readMiscRegNoEffect(int misc_reg) const 1817405SAli.Saidi@ARM.com{ 1827405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 1837614Sminkyu.jeong@arm.com 1847614Sminkyu.jeong@arm.com int flat_idx; 1857614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 1867614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 1877614Sminkyu.jeong@arm.com else 1887614Sminkyu.jeong@arm.com flat_idx = misc_reg; 1897614Sminkyu.jeong@arm.com MiscReg val = miscRegs[flat_idx]; 1907614Sminkyu.jeong@arm.com 1917614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Reading From misc reg %d (%d) : %#x\n", 1927614Sminkyu.jeong@arm.com misc_reg, flat_idx, val); 1937614Sminkyu.jeong@arm.com return val; 1947405SAli.Saidi@ARM.com} 1957405SAli.Saidi@ARM.com 1967405SAli.Saidi@ARM.com 1977405SAli.Saidi@ARM.comMiscReg 1987405SAli.Saidi@ARM.comISA::readMiscReg(int misc_reg, ThreadContext *tc) 1997405SAli.Saidi@ARM.com{ 2009050Schander.sudanthi@arm.com ArmSystem *arm_sys; 2019050Schander.sudanthi@arm.com 2027405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 2037405SAli.Saidi@ARM.com CPSR cpsr = miscRegs[misc_reg]; 2047720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 2057720Sgblack@eecs.umich.edu cpsr.j = pc.jazelle() ? 1 : 0; 2067720Sgblack@eecs.umich.edu cpsr.t = pc.thumb() ? 1 : 0; 2077405SAli.Saidi@ARM.com return cpsr; 2087405SAli.Saidi@ARM.com } 2097757SAli.Saidi@ARM.com if (misc_reg >= MISCREG_CP15_UNIMP_START) 2107405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s read.\n", 2117405SAli.Saidi@ARM.com miscRegName[misc_reg]); 2127757SAli.Saidi@ARM.com 2137405SAli.Saidi@ARM.com switch (misc_reg) { 2148284SAli.Saidi@ARM.com case MISCREG_MPIDR: 2159050Schander.sudanthi@arm.com arm_sys = dynamic_cast<ArmSystem*>(tc->getSystemPtr()); 2169050Schander.sudanthi@arm.com assert(arm_sys); 2178873SAli.Saidi@ARM.com 2189050Schander.sudanthi@arm.com if (arm_sys->multiProc) { 2199050Schander.sudanthi@arm.com return 0x80000000 | // multiprocessor extensions available 2209050Schander.sudanthi@arm.com tc->cpuId(); 2219050Schander.sudanthi@arm.com } else { 2229050Schander.sudanthi@arm.com return 0x80000000 | // multiprocessor extensions available 2239050Schander.sudanthi@arm.com 0x40000000 | // in up system 2249050Schander.sudanthi@arm.com tc->cpuId(); 2259050Schander.sudanthi@arm.com } 2268284SAli.Saidi@ARM.com break; 2277405SAli.Saidi@ARM.com case MISCREG_CLIDR: 2287731SAli.Saidi@ARM.com warn_once("The clidr register always reports 0 caches.\n"); 2298468Swade.walker@arm.com warn_once("clidr LoUIS field of 0b001 to match current " 2308468Swade.walker@arm.com "ARM implementations.\n"); 2318468Swade.walker@arm.com return 0x00200000; 2327405SAli.Saidi@ARM.com case MISCREG_CCSIDR: 2337731SAli.Saidi@ARM.com warn_once("The ccsidr register isn't implemented and " 2347405SAli.Saidi@ARM.com "always reads as 0.\n"); 2357405SAli.Saidi@ARM.com break; 2367583SAli.Saidi@arm.com case MISCREG_CTR: 2379130Satgutier@umich.edu { 2389130Satgutier@umich.edu //all caches have the same line size in gem5 2399130Satgutier@umich.edu //4 byte words in ARM 2409130Satgutier@umich.edu unsigned lineSizeWords = 2419814Sandreas.hansson@arm.com tc->getSystemPtr()->cacheLineSize() / 4; 2429130Satgutier@umich.edu unsigned log2LineSizeWords = 0; 2439130Satgutier@umich.edu 2449130Satgutier@umich.edu while (lineSizeWords >>= 1) { 2459130Satgutier@umich.edu ++log2LineSizeWords; 2469130Satgutier@umich.edu } 2479130Satgutier@umich.edu 2489130Satgutier@umich.edu CTR ctr = 0; 2499130Satgutier@umich.edu //log2 of minimun i-cache line size (words) 2509130Satgutier@umich.edu ctr.iCacheLineSize = log2LineSizeWords; 2519130Satgutier@umich.edu //b11 - gem5 uses pipt 2529130Satgutier@umich.edu ctr.l1IndexPolicy = 0x3; 2539130Satgutier@umich.edu //log2 of minimum d-cache line size (words) 2549130Satgutier@umich.edu ctr.dCacheLineSize = log2LineSizeWords; 2559130Satgutier@umich.edu //log2 of max reservation size (words) 2569130Satgutier@umich.edu ctr.erg = log2LineSizeWords; 2579130Satgutier@umich.edu //log2 of max writeback size (words) 2589130Satgutier@umich.edu ctr.cwg = log2LineSizeWords; 2599130Satgutier@umich.edu //b100 - gem5 format is ARMv7 2609130Satgutier@umich.edu ctr.format = 0x4; 2619130Satgutier@umich.edu 2629130Satgutier@umich.edu return ctr; 2639130Satgutier@umich.edu } 2647583SAli.Saidi@arm.com case MISCREG_ACTLR: 2657583SAli.Saidi@arm.com warn("Not doing anything for miscreg ACTLR\n"); 2667583SAli.Saidi@arm.com break; 2677583SAli.Saidi@arm.com case MISCREG_PMCR: 2687583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 2697583SAli.Saidi@arm.com case MISCREG_PMSELR: 2708299Schander.sudanthi@arm.com warn("Not doing anything for read to miscreg %s\n", 2717583SAli.Saidi@arm.com miscRegName[misc_reg]); 2727583SAli.Saidi@arm.com break; 2738302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 2748302SAli.Saidi@ARM.com panic("shouldn't be reading this register seperately\n"); 2757783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 2767783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrQcMask; 2777783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 2787783SGiacomo.Gabrielli@arm.com return readMiscRegNoEffect(MISCREG_FPSCR) & ~FpscrExcMask; 2798549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 2808868SMatt.Horsnell@arm.com { 2818868SMatt.Horsnell@arm.com // mostly unimplemented, just set NumCPUs field from sim and return 2828868SMatt.Horsnell@arm.com L2CTLR l2ctlr = 0; 2838868SMatt.Horsnell@arm.com // b00:1CPU to b11:4CPUs 2848868SMatt.Horsnell@arm.com l2ctlr.numCPUs = tc->getSystemPtr()->numContexts() - 1; 2858868SMatt.Horsnell@arm.com return l2ctlr; 2868868SMatt.Horsnell@arm.com } 2878868SMatt.Horsnell@arm.com case MISCREG_DBGDIDR: 2888868SMatt.Horsnell@arm.com /* For now just implement the version number. 2898868SMatt.Horsnell@arm.com * Return 0 as we don't support debug architecture yet. 2908868SMatt.Horsnell@arm.com */ 2919130Satgutier@umich.edu return 0; 2928868SMatt.Horsnell@arm.com case MISCREG_DBGDSCR_INT: 2938868SMatt.Horsnell@arm.com return 0; 2947405SAli.Saidi@ARM.com } 2957405SAli.Saidi@ARM.com return readMiscRegNoEffect(misc_reg); 2967405SAli.Saidi@ARM.com} 2977405SAli.Saidi@ARM.com 2987405SAli.Saidi@ARM.comvoid 2997405SAli.Saidi@ARM.comISA::setMiscRegNoEffect(int misc_reg, const MiscReg &val) 3007405SAli.Saidi@ARM.com{ 3017405SAli.Saidi@ARM.com assert(misc_reg < NumMiscRegs); 3027614Sminkyu.jeong@arm.com 3037614Sminkyu.jeong@arm.com int flat_idx; 3047614Sminkyu.jeong@arm.com if (misc_reg == MISCREG_SPSR) 3057614Sminkyu.jeong@arm.com flat_idx = flattenMiscIndex(misc_reg); 3067614Sminkyu.jeong@arm.com else 3077614Sminkyu.jeong@arm.com flat_idx = misc_reg; 3087614Sminkyu.jeong@arm.com miscRegs[flat_idx] = val; 3097614Sminkyu.jeong@arm.com 3107614Sminkyu.jeong@arm.com DPRINTF(MiscRegs, "Writing to misc reg %d (%d) : %#x\n", misc_reg, 3117614Sminkyu.jeong@arm.com flat_idx, val); 3127405SAli.Saidi@ARM.com} 3137405SAli.Saidi@ARM.com 3147405SAli.Saidi@ARM.comvoid 3157405SAli.Saidi@ARM.comISA::setMiscReg(int misc_reg, const MiscReg &val, ThreadContext *tc) 3167405SAli.Saidi@ARM.com{ 3177749SAli.Saidi@ARM.com 3187405SAli.Saidi@ARM.com MiscReg newVal = val; 3198284SAli.Saidi@ARM.com int x; 3208284SAli.Saidi@ARM.com System *sys; 3218284SAli.Saidi@ARM.com ThreadContext *oc; 3228284SAli.Saidi@ARM.com 3237405SAli.Saidi@ARM.com if (misc_reg == MISCREG_CPSR) { 3247405SAli.Saidi@ARM.com updateRegMap(val); 3257749SAli.Saidi@ARM.com 3267749SAli.Saidi@ARM.com 3277749SAli.Saidi@ARM.com CPSR old_cpsr = miscRegs[MISCREG_CPSR]; 3287749SAli.Saidi@ARM.com int old_mode = old_cpsr.mode; 3297405SAli.Saidi@ARM.com CPSR cpsr = val; 3307749SAli.Saidi@ARM.com if (old_mode != cpsr.mode) { 3317749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 3327749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 3337749SAli.Saidi@ARM.com } 3347749SAli.Saidi@ARM.com 3357614Sminkyu.jeong@arm.com DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n", 3367614Sminkyu.jeong@arm.com miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode); 3377720Sgblack@eecs.umich.edu PCState pc = tc->pcState(); 3387720Sgblack@eecs.umich.edu pc.nextThumb(cpsr.t); 3397720Sgblack@eecs.umich.edu pc.nextJazelle(cpsr.j); 3408887Sgeoffrey.blake@arm.com 3418887Sgeoffrey.blake@arm.com // Follow slightly different semantics if a CheckerCPU object 3428887Sgeoffrey.blake@arm.com // is connected 3438887Sgeoffrey.blake@arm.com CheckerCPU *checker = tc->getCheckerCpuPtr(); 3448887Sgeoffrey.blake@arm.com if (checker) { 3458887Sgeoffrey.blake@arm.com tc->pcStateNoRecord(pc); 3468887Sgeoffrey.blake@arm.com } else { 3478887Sgeoffrey.blake@arm.com tc->pcState(pc); 3488887Sgeoffrey.blake@arm.com } 3497408Sgblack@eecs.umich.edu } else if (misc_reg >= MISCREG_CP15_UNIMP_START && 3507405SAli.Saidi@ARM.com misc_reg < MISCREG_CP15_END) { 3517405SAli.Saidi@ARM.com panic("Unimplemented CP15 register %s wrote with %#x.\n", 3527405SAli.Saidi@ARM.com miscRegName[misc_reg], val); 3537408Sgblack@eecs.umich.edu } else { 3547408Sgblack@eecs.umich.edu switch (misc_reg) { 3557408Sgblack@eecs.umich.edu case MISCREG_CPACR: 3567408Sgblack@eecs.umich.edu { 3578206SWilliam.Wang@arm.com 3588206SWilliam.Wang@arm.com const uint32_t ones = (uint32_t)(-1); 3598206SWilliam.Wang@arm.com CPACR cpacrMask = 0; 3608206SWilliam.Wang@arm.com // Only cp10, cp11, and ase are implemented, nothing else should 3618206SWilliam.Wang@arm.com // be writable 3628206SWilliam.Wang@arm.com cpacrMask.cp10 = ones; 3638206SWilliam.Wang@arm.com cpacrMask.cp11 = ones; 3648206SWilliam.Wang@arm.com cpacrMask.asedis = ones; 3658206SWilliam.Wang@arm.com newVal &= cpacrMask; 3668206SWilliam.Wang@arm.com DPRINTF(MiscRegs, "Writing misc reg %s: %#x\n", 3678206SWilliam.Wang@arm.com miscRegName[misc_reg], newVal); 3687408Sgblack@eecs.umich.edu } 3697408Sgblack@eecs.umich.edu break; 3707408Sgblack@eecs.umich.edu case MISCREG_CSSELR: 3717731SAli.Saidi@ARM.com warn_once("The csselr register isn't implemented.\n"); 3728206SWilliam.Wang@arm.com return; 3737408Sgblack@eecs.umich.edu case MISCREG_FPSCR: 3747408Sgblack@eecs.umich.edu { 3757408Sgblack@eecs.umich.edu const uint32_t ones = (uint32_t)(-1); 3767408Sgblack@eecs.umich.edu FPSCR fpscrMask = 0; 3777408Sgblack@eecs.umich.edu fpscrMask.ioc = ones; 3787408Sgblack@eecs.umich.edu fpscrMask.dzc = ones; 3797408Sgblack@eecs.umich.edu fpscrMask.ofc = ones; 3807408Sgblack@eecs.umich.edu fpscrMask.ufc = ones; 3817408Sgblack@eecs.umich.edu fpscrMask.ixc = ones; 3827408Sgblack@eecs.umich.edu fpscrMask.idc = ones; 3837408Sgblack@eecs.umich.edu fpscrMask.len = ones; 3847408Sgblack@eecs.umich.edu fpscrMask.stride = ones; 3857408Sgblack@eecs.umich.edu fpscrMask.rMode = ones; 3867408Sgblack@eecs.umich.edu fpscrMask.fz = ones; 3877408Sgblack@eecs.umich.edu fpscrMask.dn = ones; 3887408Sgblack@eecs.umich.edu fpscrMask.ahp = ones; 3897408Sgblack@eecs.umich.edu fpscrMask.qc = ones; 3907408Sgblack@eecs.umich.edu fpscrMask.v = ones; 3917408Sgblack@eecs.umich.edu fpscrMask.c = ones; 3927408Sgblack@eecs.umich.edu fpscrMask.z = ones; 3937408Sgblack@eecs.umich.edu fpscrMask.n = ones; 3947408Sgblack@eecs.umich.edu newVal = (newVal & (uint32_t)fpscrMask) | 3957408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); 3969377Sgblack@eecs.umich.edu tc->getDecoderPtr()->setContext(newVal); 3977408Sgblack@eecs.umich.edu } 3987408Sgblack@eecs.umich.edu break; 3998302SAli.Saidi@ARM.com case MISCREG_CPSR_Q: 4008302SAli.Saidi@ARM.com { 4018302SAli.Saidi@ARM.com assert(!(newVal & ~CpsrMaskQ)); 4028302SAli.Saidi@ARM.com newVal = miscRegs[MISCREG_CPSR] | newVal; 4038302SAli.Saidi@ARM.com misc_reg = MISCREG_CPSR; 4048302SAli.Saidi@ARM.com } 4058302SAli.Saidi@ARM.com break; 4067783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_QC: 4077783SGiacomo.Gabrielli@arm.com { 4087783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrQcMask); 4097783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 4107783SGiacomo.Gabrielli@arm.com } 4117783SGiacomo.Gabrielli@arm.com break; 4127783SGiacomo.Gabrielli@arm.com case MISCREG_FPSCR_EXC: 4137783SGiacomo.Gabrielli@arm.com { 4147783SGiacomo.Gabrielli@arm.com newVal = miscRegs[MISCREG_FPSCR] | (newVal & FpscrExcMask); 4157783SGiacomo.Gabrielli@arm.com misc_reg = MISCREG_FPSCR; 4167783SGiacomo.Gabrielli@arm.com } 4177783SGiacomo.Gabrielli@arm.com break; 4187408Sgblack@eecs.umich.edu case MISCREG_FPEXC: 4197408Sgblack@eecs.umich.edu { 4208206SWilliam.Wang@arm.com // vfpv3 architecture, section B.6.1 of DDI04068 4218206SWilliam.Wang@arm.com // bit 29 - valid only if fpexc[31] is 0 4227408Sgblack@eecs.umich.edu const uint32_t fpexcMask = 0x60000000; 4237408Sgblack@eecs.umich.edu newVal = (newVal & fpexcMask) | 4247408Sgblack@eecs.umich.edu (miscRegs[MISCREG_FPEXC] & ~fpexcMask); 4257408Sgblack@eecs.umich.edu } 4267408Sgblack@eecs.umich.edu break; 4277408Sgblack@eecs.umich.edu case MISCREG_SCTLR: 4287408Sgblack@eecs.umich.edu { 4297408Sgblack@eecs.umich.edu DPRINTF(MiscRegs, "Writing SCTLR: %#x\n", newVal); 4307408Sgblack@eecs.umich.edu SCTLR sctlr = miscRegs[MISCREG_SCTLR]; 4317408Sgblack@eecs.umich.edu SCTLR new_sctlr = newVal; 4327408Sgblack@eecs.umich.edu new_sctlr.nmfi = (bool)sctlr.nmfi; 4337408Sgblack@eecs.umich.edu miscRegs[MISCREG_SCTLR] = (MiscReg)new_sctlr; 4347749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 4357749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 4368527SAli.Saidi@ARM.com 4378527SAli.Saidi@ARM.com // Check if all CPUs are booted with caches enabled 4388527SAli.Saidi@ARM.com // so we can stop enforcing coherency of some kernel 4398527SAli.Saidi@ARM.com // structures manually. 4408527SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4418527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4428527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4438527SAli.Saidi@ARM.com SCTLR other_sctlr = oc->readMiscRegNoEffect(MISCREG_SCTLR); 4448527SAli.Saidi@ARM.com if (!other_sctlr.c && oc->status() != ThreadContext::Halted) 4458527SAli.Saidi@ARM.com return; 4468527SAli.Saidi@ARM.com } 4478527SAli.Saidi@ARM.com 4488527SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4498527SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4508527SAli.Saidi@ARM.com oc->getDTBPtr()->allCpusCaching(); 4518527SAli.Saidi@ARM.com oc->getITBPtr()->allCpusCaching(); 4528887Sgeoffrey.blake@arm.com 4538887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it. 4548887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4558733Sgeoffrey.blake@arm.com if (checker) { 4568733Sgeoffrey.blake@arm.com checker->getDTBPtr()->allCpusCaching(); 4578733Sgeoffrey.blake@arm.com checker->getITBPtr()->allCpusCaching(); 4588733Sgeoffrey.blake@arm.com } 4598527SAli.Saidi@ARM.com } 4607408Sgblack@eecs.umich.edu return; 4617408Sgblack@eecs.umich.edu } 4629385SAndreas.Sandberg@arm.com 4639385SAndreas.Sandberg@arm.com case MISCREG_MIDR: 4649385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR0: 4659385SAndreas.Sandberg@arm.com case MISCREG_ID_PFR1: 4669385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR0: 4679385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR1: 4689385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR2: 4699385SAndreas.Sandberg@arm.com case MISCREG_ID_MMFR3: 4709385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR0: 4719385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR1: 4729385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR2: 4739385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR3: 4749385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR4: 4759385SAndreas.Sandberg@arm.com case MISCREG_ID_ISAR5: 4769385SAndreas.Sandberg@arm.com 4779385SAndreas.Sandberg@arm.com case MISCREG_MPIDR: 4789385SAndreas.Sandberg@arm.com case MISCREG_FPSID: 4797408Sgblack@eecs.umich.edu case MISCREG_TLBTR: 4807408Sgblack@eecs.umich.edu case MISCREG_MVFR0: 4817408Sgblack@eecs.umich.edu case MISCREG_MVFR1: 4829385SAndreas.Sandberg@arm.com // ID registers are constants. 4837408Sgblack@eecs.umich.edu return; 4849385SAndreas.Sandberg@arm.com 4857408Sgblack@eecs.umich.edu case MISCREG_TLBIALLIS: 4867408Sgblack@eecs.umich.edu case MISCREG_TLBIALL: 4878284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 4888284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 4898284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 4908284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 4918284SAli.Saidi@ARM.com oc->getITBPtr()->flushAll(); 4928284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAll(); 4938887Sgeoffrey.blake@arm.com 4948887Sgeoffrey.blake@arm.com // If CheckerCPU is connected, need to notify it of a flush 4958887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 4968733Sgeoffrey.blake@arm.com if (checker) { 4978733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAll(); 4988733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAll(); 4998733Sgeoffrey.blake@arm.com } 5008284SAli.Saidi@ARM.com } 5017408Sgblack@eecs.umich.edu return; 5027408Sgblack@eecs.umich.edu case MISCREG_ITLBIALL: 5037408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAll(); 5047408Sgblack@eecs.umich.edu return; 5057408Sgblack@eecs.umich.edu case MISCREG_DTLBIALL: 5067408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAll(); 5077408Sgblack@eecs.umich.edu return; 5087408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAIS: 5097408Sgblack@eecs.umich.edu case MISCREG_TLBIMVA: 5108284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 5118284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 5128284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 5138284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 5148284SAli.Saidi@ARM.com oc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5158284SAli.Saidi@ARM.com bits(newVal, 7,0)); 5168284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5178284SAli.Saidi@ARM.com bits(newVal, 7,0)); 5188887Sgeoffrey.blake@arm.com 5198887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 5208733Sgeoffrey.blake@arm.com if (checker) { 5218733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5228733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 5238733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5248733Sgeoffrey.blake@arm.com bits(newVal, 7,0)); 5258733Sgeoffrey.blake@arm.com } 5268284SAli.Saidi@ARM.com } 5277408Sgblack@eecs.umich.edu return; 5287408Sgblack@eecs.umich.edu case MISCREG_TLBIASIDIS: 5297408Sgblack@eecs.umich.edu case MISCREG_TLBIASID: 5308284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 5318284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 5328284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 5338284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 5348284SAli.Saidi@ARM.com oc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5358284SAli.Saidi@ARM.com oc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5368887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 5378733Sgeoffrey.blake@arm.com if (checker) { 5388733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5398733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5408733Sgeoffrey.blake@arm.com } 5418284SAli.Saidi@ARM.com } 5427408Sgblack@eecs.umich.edu return; 5437408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAAIS: 5447408Sgblack@eecs.umich.edu case MISCREG_TLBIMVAA: 5458284SAli.Saidi@ARM.com sys = tc->getSystemPtr(); 5468284SAli.Saidi@ARM.com for (x = 0; x < sys->numContexts(); x++) { 5478284SAli.Saidi@ARM.com oc = sys->getThreadContext(x); 5488284SAli.Saidi@ARM.com assert(oc->getITBPtr() && oc->getDTBPtr()); 5498284SAli.Saidi@ARM.com oc->getITBPtr()->flushMva(mbits(newVal, 31,12)); 5508284SAli.Saidi@ARM.com oc->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 5518887Sgeoffrey.blake@arm.com 5528887Sgeoffrey.blake@arm.com CheckerCPU *checker = oc->getCheckerCpuPtr(); 5538733Sgeoffrey.blake@arm.com if (checker) { 5548733Sgeoffrey.blake@arm.com checker->getITBPtr()->flushMva(mbits(newVal, 31,12)); 5558733Sgeoffrey.blake@arm.com checker->getDTBPtr()->flushMva(mbits(newVal, 31,12)); 5568733Sgeoffrey.blake@arm.com } 5578284SAli.Saidi@ARM.com } 5587408Sgblack@eecs.umich.edu return; 5597408Sgblack@eecs.umich.edu case MISCREG_ITLBIMVA: 5607408Sgblack@eecs.umich.edu tc->getITBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5617408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5627408Sgblack@eecs.umich.edu return; 5637408Sgblack@eecs.umich.edu case MISCREG_DTLBIMVA: 5647408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushMvaAsid(mbits(newVal, 31, 12), 5657408Sgblack@eecs.umich.edu bits(newVal, 7,0)); 5667408Sgblack@eecs.umich.edu return; 5677408Sgblack@eecs.umich.edu case MISCREG_ITLBIASID: 5687408Sgblack@eecs.umich.edu tc->getITBPtr()->flushAsid(bits(newVal, 7,0)); 5697408Sgblack@eecs.umich.edu return; 5707408Sgblack@eecs.umich.edu case MISCREG_DTLBIASID: 5717408Sgblack@eecs.umich.edu tc->getDTBPtr()->flushAsid(bits(newVal, 7,0)); 5727405SAli.Saidi@ARM.com return; 5737583SAli.Saidi@arm.com case MISCREG_ACTLR: 5747583SAli.Saidi@arm.com warn("Not doing anything for write of miscreg ACTLR\n"); 5757583SAli.Saidi@arm.com break; 5767583SAli.Saidi@arm.com case MISCREG_PMCR: 5778059SAli.Saidi@ARM.com { 5788059SAli.Saidi@ARM.com // Performance counters not implemented. Instead, interpret 5798059SAli.Saidi@ARM.com // a reset command to this register to reset the simulator 5808059SAli.Saidi@ARM.com // statistics. 5818059SAli.Saidi@ARM.com // PMCR_E | PMCR_P | PMCR_C 5828059SAli.Saidi@ARM.com const int ResetAndEnableCounters = 0x7; 5838059SAli.Saidi@ARM.com if (newVal == ResetAndEnableCounters) { 5848059SAli.Saidi@ARM.com inform("Resetting all simobject stats\n"); 5858059SAli.Saidi@ARM.com Stats::schedStatEvent(false, true); 5868059SAli.Saidi@ARM.com break; 5878059SAli.Saidi@ARM.com } 5888059SAli.Saidi@ARM.com } 5897583SAli.Saidi@arm.com case MISCREG_PMCCNTR: 5907583SAli.Saidi@arm.com case MISCREG_PMSELR: 5917583SAli.Saidi@arm.com warn("Not doing anything for write to miscreg %s\n", 5927583SAli.Saidi@arm.com miscRegName[misc_reg]); 5937583SAli.Saidi@arm.com break; 5947436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 5957436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 5967436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 5977436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 5987436Sdam.sunwoo@arm.com case MISCREG_V2POWPR: 5997436Sdam.sunwoo@arm.com case MISCREG_V2POWPW: 6007436Sdam.sunwoo@arm.com case MISCREG_V2POWUR: 6017436Sdam.sunwoo@arm.com case MISCREG_V2POWUW: 6027436Sdam.sunwoo@arm.com { 6037436Sdam.sunwoo@arm.com RequestPtr req = new Request; 6047436Sdam.sunwoo@arm.com unsigned flags; 6057436Sdam.sunwoo@arm.com BaseTLB::Mode mode; 6067436Sdam.sunwoo@arm.com Fault fault; 6077436Sdam.sunwoo@arm.com switch(misc_reg) { 6087436Sdam.sunwoo@arm.com case MISCREG_V2PCWPR: 6097436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 6107436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 6117436Sdam.sunwoo@arm.com break; 6127436Sdam.sunwoo@arm.com case MISCREG_V2PCWPW: 6137436Sdam.sunwoo@arm.com flags = TLB::MustBeOne; 6147436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 6157436Sdam.sunwoo@arm.com break; 6167436Sdam.sunwoo@arm.com case MISCREG_V2PCWUR: 6177436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 6187436Sdam.sunwoo@arm.com mode = BaseTLB::Read; 6197436Sdam.sunwoo@arm.com break; 6207436Sdam.sunwoo@arm.com case MISCREG_V2PCWUW: 6217436Sdam.sunwoo@arm.com flags = TLB::MustBeOne | TLB::UserMode; 6227436Sdam.sunwoo@arm.com mode = BaseTLB::Write; 6237436Sdam.sunwoo@arm.com break; 6247442Ssaidi@eecs.umich.edu default: 6257436Sdam.sunwoo@arm.com panic("Security Extensions not implemented!"); 6267436Sdam.sunwoo@arm.com } 6278208SAli.Saidi@ARM.com warn("Translating via MISCREG in atomic mode! Fix Me!\n"); 6288832SAli.Saidi@ARM.com req->setVirt(0, val, 1, flags, tc->pcState().pc(), 6298832SAli.Saidi@ARM.com Request::funcMasterId); 6307436Sdam.sunwoo@arm.com fault = tc->getDTBPtr()->translateAtomic(req, tc, mode); 6317436Sdam.sunwoo@arm.com if (fault == NoFault) { 6327436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 6337436Sdam.sunwoo@arm.com (req->getPaddr() & 0xfffff000) | 6347436Sdam.sunwoo@arm.com (tc->getDTBPtr()->getAttr() ); 6357436Sdam.sunwoo@arm.com DPRINTF(MiscRegs, 6367436Sdam.sunwoo@arm.com "MISCREG: Translated addr 0x%08x: PAR: 0x%08x\n", 6377436Sdam.sunwoo@arm.com val, miscRegs[MISCREG_PAR]); 6387436Sdam.sunwoo@arm.com } 6397436Sdam.sunwoo@arm.com else { 6407436Sdam.sunwoo@arm.com // Set fault bit and FSR 6417436Sdam.sunwoo@arm.com FSR fsr = miscRegs[MISCREG_DFSR]; 6427436Sdam.sunwoo@arm.com miscRegs[MISCREG_PAR] = 6437436Sdam.sunwoo@arm.com (fsr.ext << 6) | 6447436Sdam.sunwoo@arm.com (fsr.fsHigh << 5) | 6457436Sdam.sunwoo@arm.com (fsr.fsLow << 1) | 6467436Sdam.sunwoo@arm.com 0x1; // F bit 6477436Sdam.sunwoo@arm.com } 6487436Sdam.sunwoo@arm.com return; 6497436Sdam.sunwoo@arm.com } 6507749SAli.Saidi@ARM.com case MISCREG_CONTEXTIDR: 6517749SAli.Saidi@ARM.com case MISCREG_PRRR: 6527749SAli.Saidi@ARM.com case MISCREG_NMRR: 6537749SAli.Saidi@ARM.com case MISCREG_DACR: 6547749SAli.Saidi@ARM.com tc->getITBPtr()->invalidateMiscReg(); 6557749SAli.Saidi@ARM.com tc->getDTBPtr()->invalidateMiscReg(); 6567749SAli.Saidi@ARM.com break; 6578549Sdaniel.johnson@arm.com case MISCREG_L2CTLR: 6588549Sdaniel.johnson@arm.com warn("miscreg L2CTLR (%s) written with %#x. ignored...\n", 6598549Sdaniel.johnson@arm.com miscRegName[misc_reg], uint32_t(val)); 6607405SAli.Saidi@ARM.com } 6617405SAli.Saidi@ARM.com } 6627405SAli.Saidi@ARM.com setMiscRegNoEffect(misc_reg, newVal); 6637405SAli.Saidi@ARM.com} 6647405SAli.Saidi@ARM.com 6657405SAli.Saidi@ARM.com} 6669384SAndreas.Sandberg@arm.com 6679384SAndreas.Sandberg@arm.comArmISA::ISA * 6689384SAndreas.Sandberg@arm.comArmISAParams::create() 6699384SAndreas.Sandberg@arm.com{ 6709384SAndreas.Sandberg@arm.com return new ArmISA::ISA(this); 6719384SAndreas.Sandberg@arm.com} 672