interrupts.hh revision 7847:0c6613ad8f18 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2006 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Ali Saidi
41 */
42
43#ifndef __ARCH_ARM_INTERRUPT_HH__
44#define __ARCH_ARM_INTERRUPT_HH__
45
46#include "arch/arm/faults.hh"
47#include "arch/arm/isa_traits.hh"
48#include "arch/arm/miscregs.hh"
49#include "arch/arm/registers.hh"
50#include "cpu/thread_context.hh"
51#include "params/ArmInterrupts.hh"
52#include "sim/sim_object.hh"
53
54namespace ArmISA
55{
56
57class Interrupts : public SimObject
58{
59  private:
60    BaseCPU * cpu;
61
62    bool interrupts[NumInterruptTypes];
63    uint64_t intStatus;
64
65  public:
66
67    void
68    setCPU(BaseCPU * _cpu)
69    {
70        cpu = _cpu;
71    }
72
73    typedef ArmInterruptsParams Params;
74
75    const Params *
76    params() const
77    {
78        return dynamic_cast<const Params *>(_params);
79    }
80
81    Interrupts(Params * p) : SimObject(p), cpu(NULL)
82    {
83        clearAll();
84    }
85
86
87    void
88    post(int int_num, int index)
89    {
90        DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
91
92        if (int_num < 0 || int_num >= NumInterruptTypes)
93            panic("int_num out of bounds\n");
94
95        if (index != 0)
96            panic("No support for other interrupt indexes\n");
97
98        interrupts[int_num] = true;
99        intStatus |= ULL(1) << int_num;
100    }
101
102    void
103    clear(int int_num, int index)
104    {
105        DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
106
107        if (int_num < 0 || int_num >= NumInterruptTypes)
108            panic("int_num out of bounds\n");
109
110        if (index != 0)
111            panic("No support for other interrupt indexes\n");
112
113        interrupts[int_num] = false;
114        intStatus &= ~(ULL(1) << int_num);
115    }
116
117    void
118    clearAll()
119    {
120        DPRINTF(Interrupt, "Interrupts all cleared\n");
121        intStatus = 0;
122        memset(interrupts, 0, sizeof(interrupts));
123    }
124
125    bool
126    checkInterrupts(ThreadContext *tc) const
127    {
128        if (!intStatus)
129            return false;
130
131        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
132
133        return ((interrupts[INT_IRQ] && !cpsr.i) ||
134                (interrupts[INT_FIQ] && !cpsr.f) ||
135                (interrupts[INT_ABT] && !cpsr.a) ||
136                (interrupts[INT_RST]));
137    }
138
139    Fault
140    getInterrupt(ThreadContext *tc)
141    {
142        if (!intStatus)
143            return NoFault;
144
145        CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
146
147        if (interrupts[INT_IRQ] && !cpsr.i)
148            return new Interrupt;
149        if (interrupts[INT_FIQ] && !cpsr.f)
150            return new FastInterrupt;
151        if (interrupts[INT_ABT] && !cpsr.a)
152            return new DataAbort(0, false, 0,
153                    ArmFault::AsynchronousExternalAbort);
154        if (interrupts[INT_RST])
155           return new Reset;
156
157        panic("intStatus and interrupts not in sync\n");
158    }
159
160    void
161    updateIntrInfo(ThreadContext *tc)
162    {
163        ; // nothing to do
164    }
165
166    void
167    serialize(std::ostream &os)
168    {
169        SERIALIZE_ARRAY(interrupts, NumInterruptTypes);
170        SERIALIZE_SCALAR(intStatus);
171    }
172
173    void
174    unserialize(Checkpoint *cp, const std::string &section)
175    {
176        UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes);
177        UNSERIALIZE_SCALAR(intStatus);
178    }
179};
180} // namespace ARM_ISA
181
182#endif // __ARCH_ARM_INTERRUPT_HH__
183