interrupts.hh revision 4009 
1/*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29#ifndef __ARCH_SPARC_INTERRUPT_HH__
30#define __ARCH_SPARC_INTERRUPT_HH__
31
32#include "arch/sparc/faults.hh"
33#include "cpu/thread_context.hh"
34
35namespace SparcISA
36{
37
38enum interrupts_t {
39    trap_level_zero,
40    hstick_match,
41    interrupt_vector,
42    cpu_mondo,
43    dev_mondo,
44    resumable_error,
45    soft_interrupt,
46    num_interrupt_types
47};
48
49class Interrupts
50{
51
52  private:
53
54    bool interrupts[num_interrupt_types];
55    int numPosted;
56
57  public:
58    Interrupts()
59    {
60        for (int i = 0; i < num_interrupt_types; ++i) {
61            interrupts[i] = false;
62        }
63        numPosted = 0;
64    }
65
66    void post(int int_type)
67    {
68        if (int_type < 0 || int_type >= num_interrupt_types)
69            panic("posting unknown interrupt!\n");
70        interrupts[int_type] = true;
71        ++numPosted;
72    }
73
74    void post(int int_num, int index)
75    {
76
77    }
78
79    void clear(int int_num, int index)
80    {
81
82    }
83
84    void clear_all()
85    {
86
87    }
88
89    bool check_interrupts(ThreadContext * tc) const
90    {
91        if (numPosted)
92            return true;
93        else
94            return false;
95    }
96
97    Fault getInterrupt(ThreadContext * tc)
98    {
99        int hpstate = tc->readMiscReg(MISCREG_HPSTATE);
100        int pstate = tc->readMiscReg(MISCREG_PSTATE);
101        bool ie = pstate & PSTATE::ie;
102
103        // THESE ARE IN ORDER OF PRIORITY
104        // since there are early returns, and the highest
105        // priority interrupts should get serviced,
106        // it is v. important that new interrupts are inserted
107        // in the right order of processing
108        if (hpstate & HPSTATE::hpriv) {
109            if (ie) {
110                if (interrupts[hstick_match]) {
111                    if (tc->readMiscReg(MISCREG_HINTP) & 1) {
112                        interrupts[hstick_match] = false;
113                        --numPosted;
114                        return new HstickMatch;
115                    }
116                }
117                if (interrupts[interrupt_vector]) {
118                    interrupts[interrupt_vector] = false;
119                    --numPosted;
120                    //HAVEN'T IMPLed THIS YET
121                    return NoFault;
122                }
123            } else {
124                if (interrupts[hstick_match]) {
125                    return NoFault;
126                }
127
128            }
129        } else {
130            if (interrupts[trap_level_zero]) {
131                if ((pstate & HPSTATE::tlz) && (tc->readMiscReg(MISCREG_TL) == 0)) {
132                    interrupts[trap_level_zero] = false;
133                    --numPosted;
134                    return new TrapLevelZero;
135                }
136            }
137            if (interrupts[hstick_match]) {
138                if (tc->readMiscReg(MISCREG_HINTP) & 1) {
139                    interrupts[hstick_match] = false;
140                    --numPosted;
141                    return new HstickMatch;
142                    }
143            }
144            if (ie) {
145                if (interrupts[cpu_mondo]) {
146                    interrupts[cpu_mondo] = false;
147                    --numPosted;
148                    return new CpuMondo;
149                }
150                if (interrupts[dev_mondo]) {
151                    interrupts[dev_mondo] = false;
152                    --numPosted;
153                    return new DevMondo;
154                }
155                if (interrupts[soft_interrupt]) {
156                    int il = InterruptLevel(tc->readMiscReg(MISCREG_SOFTINT));
157                    // it seems that interrupt vectors are right in
158                    // the middle of interrupt levels with regard to
159                    // priority, so have to check
160                    if ((il < 6) &&
161                        interrupts[interrupt_vector]) {
162                            // may require more details here since there
163                            // may be lots of interrupts embedded in an
164                            // platform interrupt vector
165                            interrupts[interrupt_vector] = false;
166                            --numPosted;
167                            //HAVEN'T IMPLed YET
168                            return NoFault;
169                    } else {
170                        if (il > tc->readMiscReg(MISCREG_PIL)) {
171                            uint64_t si = tc->readMiscReg(MISCREG_SOFTINT);
172                            uint64_t more = si & ~(1 << (il + 1));
173                            if (!InterruptLevel(more)) {
174                                interrupts[soft_interrupt] = false;
175                                --numPosted;
176                            }
177                            return new InterruptLevelN(il);
178                        }
179                    }
180                }
181                if (interrupts[resumable_error]) {
182                    interrupts[resumable_error] = false;
183                    --numPosted;
184                    return new ResumableError;
185                }
186            }
187        }
188        return NoFault;
189    }
190
191    void updateIntrInfo(ThreadContext * tc)
192    {
193
194    }
195
196    void serialize(std::ostream &os)
197    {
198        SERIALIZE_ARRAY(interrupts,num_interrupt_types);
199        SERIALIZE_SCALAR(numPosted);
200    }
201
202    void unserialize(Checkpoint *cp, const std::string &section)
203    {
204        UNSERIALIZE_ARRAY(interrupts,num_interrupt_types);
205        UNSERIALIZE_SCALAR(numPosted);
206    }
207};
208} // namespace SPARC_ISA
209
210#endif // __ARCH_SPARC_INTERRUPT_HH__
211