interrupts.hh revision 8285
13537SN/A/* 27400SAli.Saidi@ARM.com * Copyright (c) 2010 ARM Limited 37400SAli.Saidi@ARM.com * All rights reserved 47400SAli.Saidi@ARM.com * 57400SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67400SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77400SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87400SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97400SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107400SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117400SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127400SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137400SAli.Saidi@ARM.com * 143537SN/A * Copyright (c) 2006 The Regents of The University of Michigan 153537SN/A * All rights reserved. 163537SN/A * 173537SN/A * Redistribution and use in source and binary forms, with or without 183537SN/A * modification, are permitted provided that the following conditions are 193537SN/A * met: redistributions of source code must retain the above copyright 203537SN/A * notice, this list of conditions and the following disclaimer; 213537SN/A * redistributions in binary form must reproduce the above copyright 223537SN/A * notice, this list of conditions and the following disclaimer in the 233537SN/A * documentation and/or other materials provided with the distribution; 243537SN/A * neither the name of the copyright holders nor the names of its 253537SN/A * contributors may be used to endorse or promote products derived from 263537SN/A * this software without specific prior written permission. 273537SN/A * 283537SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 293537SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 303537SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313537SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 323537SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 333537SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 343537SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 353537SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 363537SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 373537SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 383537SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 394103SN/A * 404103SN/A * Authors: Ali Saidi 413537SN/A */ 423537SN/A 436757SAli.Saidi@ARM.com#ifndef __ARCH_ARM_INTERRUPT_HH__ 446757SAli.Saidi@ARM.com#define __ARCH_ARM_INTERRUPT_HH__ 453537SN/A 466757SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 476757SAli.Saidi@ARM.com#include "arch/arm/isa_traits.hh" 487400SAli.Saidi@ARM.com#include "arch/arm/miscregs.hh" 496757SAli.Saidi@ARM.com#include "arch/arm/registers.hh" 503827SN/A#include "cpu/thread_context.hh" 518245Snate@binkert.org#include "debug/Interrupt.hh" 526757SAli.Saidi@ARM.com#include "params/ArmInterrupts.hh" 535647SN/A#include "sim/sim_object.hh" 543827SN/A 556757SAli.Saidi@ARM.comnamespace ArmISA 563537SN/A{ 573894SN/A 585647SN/Aclass Interrupts : public SimObject 594009SN/A{ 605810SN/A private: 615810SN/A BaseCPU * cpu; 624009SN/A 637400SAli.Saidi@ARM.com bool interrupts[NumInterruptTypes]; 644103SN/A uint64_t intStatus; 654009SN/A 664009SN/A public: 675810SN/A 685810SN/A void 695810SN/A setCPU(BaseCPU * _cpu) 705810SN/A { 715810SN/A cpu = _cpu; 725810SN/A } 735810SN/A 746757SAli.Saidi@ARM.com typedef ArmInterruptsParams Params; 755647SN/A 765647SN/A const Params * 775647SN/A params() const 785647SN/A { 795647SN/A return dynamic_cast<const Params *>(_params); 805647SN/A } 815647SN/A 825810SN/A Interrupts(Params * p) : SimObject(p), cpu(NULL) 834009SN/A { 845704SN/A clearAll(); 854009SN/A } 864009SN/A 874009SN/A 885704SN/A void 895704SN/A post(int int_num, int index) 903537SN/A { 917400SAli.Saidi@ARM.com DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 927400SAli.Saidi@ARM.com 937400SAli.Saidi@ARM.com if (int_num < 0 || int_num >= NumInterruptTypes) 947400SAli.Saidi@ARM.com panic("int_num out of bounds\n"); 957400SAli.Saidi@ARM.com 967400SAli.Saidi@ARM.com if (index != 0) 977400SAli.Saidi@ARM.com panic("No support for other interrupt indexes\n"); 987400SAli.Saidi@ARM.com 997400SAli.Saidi@ARM.com interrupts[int_num] = true; 1007400SAli.Saidi@ARM.com intStatus |= ULL(1) << int_num; 1014009SN/A } 1023894SN/A 1035704SN/A void 1045704SN/A clear(int int_num, int index) 1054009SN/A { 1067847Sminkyu.jeong@arm.com DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 1077400SAli.Saidi@ARM.com 1087400SAli.Saidi@ARM.com if (int_num < 0 || int_num >= NumInterruptTypes) 1097400SAli.Saidi@ARM.com panic("int_num out of bounds\n"); 1107400SAli.Saidi@ARM.com 1117400SAli.Saidi@ARM.com if (index != 0) 1127400SAli.Saidi@ARM.com panic("No support for other interrupt indexes\n"); 1137400SAli.Saidi@ARM.com 1147400SAli.Saidi@ARM.com interrupts[int_num] = false; 1157400SAli.Saidi@ARM.com intStatus &= ~(ULL(1) << int_num); 1164009SN/A } 1173827SN/A 1185704SN/A void 1195704SN/A clearAll() 1204009SN/A { 1217400SAli.Saidi@ARM.com DPRINTF(Interrupt, "Interrupts all cleared\n"); 1224103SN/A intStatus = 0; 1237400SAli.Saidi@ARM.com memset(interrupts, 0, sizeof(interrupts)); 1244009SN/A } 1253537SN/A 1265704SN/A bool 1275704SN/A checkInterrupts(ThreadContext *tc) const 1284009SN/A { 1297400SAli.Saidi@ARM.com if (!intStatus) 1307400SAli.Saidi@ARM.com return false; 1317400SAli.Saidi@ARM.com 1327400SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1337400SAli.Saidi@ARM.com 1347400SAli.Saidi@ARM.com return ((interrupts[INT_IRQ] && !cpsr.i) || 1357400SAli.Saidi@ARM.com (interrupts[INT_FIQ] && !cpsr.f) || 1367400SAli.Saidi@ARM.com (interrupts[INT_ABT] && !cpsr.a) || 1377400SAli.Saidi@ARM.com (interrupts[INT_RST])); 1384009SN/A } 1393537SN/A 1408285SPrakash.Ramrakhyani@arm.com /** 1418285SPrakash.Ramrakhyani@arm.com * Check the raw interrupt state. 1428285SPrakash.Ramrakhyani@arm.com * This function is used to check if a wfi operation should sleep. If there 1438285SPrakash.Ramrakhyani@arm.com * is an interrupt pending, even if it's masked, wfi doesn't sleep. 1448285SPrakash.Ramrakhyani@arm.com * @return any interrupts pending 1458285SPrakash.Ramrakhyani@arm.com */ 1468285SPrakash.Ramrakhyani@arm.com bool 1478285SPrakash.Ramrakhyani@arm.com checkRaw() const 1488285SPrakash.Ramrakhyani@arm.com { 1498285SPrakash.Ramrakhyani@arm.com return intStatus; 1508285SPrakash.Ramrakhyani@arm.com } 1518285SPrakash.Ramrakhyani@arm.com 1528285SPrakash.Ramrakhyani@arm.com 1535704SN/A Fault 1545704SN/A getInterrupt(ThreadContext *tc) 1554009SN/A { 1567400SAli.Saidi@ARM.com if (!intStatus) 1577400SAli.Saidi@ARM.com return NoFault; 1587400SAli.Saidi@ARM.com 1597400SAli.Saidi@ARM.com CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 1607400SAli.Saidi@ARM.com 1617400SAli.Saidi@ARM.com if (interrupts[INT_IRQ] && !cpsr.i) 1627400SAli.Saidi@ARM.com return new Interrupt; 1637400SAli.Saidi@ARM.com if (interrupts[INT_FIQ] && !cpsr.f) 1647400SAli.Saidi@ARM.com return new FastInterrupt; 1657400SAli.Saidi@ARM.com if (interrupts[INT_ABT] && !cpsr.a) 1667400SAli.Saidi@ARM.com return new DataAbort(0, false, 0, 1677400SAli.Saidi@ARM.com ArmFault::AsynchronousExternalAbort); 1687400SAli.Saidi@ARM.com if (interrupts[INT_RST]) 1697400SAli.Saidi@ARM.com return new Reset; 1707400SAli.Saidi@ARM.com 1717400SAli.Saidi@ARM.com panic("intStatus and interrupts not in sync\n"); 1724009SN/A } 1733537SN/A 1745704SN/A void 1755704SN/A updateIntrInfo(ThreadContext *tc) 1764009SN/A { 1777400SAli.Saidi@ARM.com ; // nothing to do 1784009SN/A } 1793654SN/A 1805704SN/A void 1815704SN/A serialize(std::ostream &os) 1824009SN/A { 1837400SAli.Saidi@ARM.com SERIALIZE_ARRAY(interrupts, NumInterruptTypes); 1847400SAli.Saidi@ARM.com SERIALIZE_SCALAR(intStatus); 1854009SN/A } 1863537SN/A 1875704SN/A void 1885704SN/A unserialize(Checkpoint *cp, const std::string §ion) 1894009SN/A { 1907400SAli.Saidi@ARM.com UNSERIALIZE_ARRAY(interrupts, NumInterruptTypes); 1917400SAli.Saidi@ARM.com UNSERIALIZE_SCALAR(intStatus); 1924009SN/A } 1934009SN/A}; 1946757SAli.Saidi@ARM.com} // namespace ARM_ISA 1953537SN/A 1966757SAli.Saidi@ARM.com#endif // __ARCH_ARM_INTERRUPT_HH__ 197