interrupts.hh revision 4103
112940Sgabeblack@google.com/* 212940Sgabeblack@google.com * Copyright (c) 2006 The Regents of The University of Michigan 312940Sgabeblack@google.com * All rights reserved. 412940Sgabeblack@google.com * 512940Sgabeblack@google.com * Redistribution and use in source and binary forms, with or without 612940Sgabeblack@google.com * modification, are permitted provided that the following conditions are 712940Sgabeblack@google.com * met: redistributions of source code must retain the above copyright 812940Sgabeblack@google.com * notice, this list of conditions and the following disclaimer; 912940Sgabeblack@google.com * redistributions in binary form must reproduce the above copyright 1012940Sgabeblack@google.com * notice, this list of conditions and the following disclaimer in the 1112940Sgabeblack@google.com * documentation and/or other materials provided with the distribution; 1212940Sgabeblack@google.com * neither the name of the copyright holders nor the names of its 1312940Sgabeblack@google.com * contributors may be used to endorse or promote products derived from 1412940Sgabeblack@google.com * this software without specific prior written permission. 1512940Sgabeblack@google.com * 1612940Sgabeblack@google.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 1712940Sgabeblack@google.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 1812940Sgabeblack@google.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 1912940Sgabeblack@google.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2012940Sgabeblack@google.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 2112940Sgabeblack@google.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 2212940Sgabeblack@google.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2312940Sgabeblack@google.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2412940Sgabeblack@google.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2512940Sgabeblack@google.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 2612940Sgabeblack@google.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2712940Sgabeblack@google.com * 2812940Sgabeblack@google.com * Authors: Ali Saidi 2912940Sgabeblack@google.com * Lisa Hsu 3012940Sgabeblack@google.com */ 3113192Sgabeblack@google.com 3213192Sgabeblack@google.com#ifndef __ARCH_SPARC_INTERRUPT_HH__ 3313192Sgabeblack@google.com#define __ARCH_SPARC_INTERRUPT_HH__ 3412940Sgabeblack@google.com 3512940Sgabeblack@google.com#include "arch/sparc/faults.hh" 3612940Sgabeblack@google.com#include "arch/sparc/isa_traits.hh" 3712940Sgabeblack@google.com#include "cpu/thread_context.hh" 3812940Sgabeblack@google.com 3913192Sgabeblack@google.comnamespace SparcISA 4012940Sgabeblack@google.com{ 4112940Sgabeblack@google.com 4213192Sgabeblack@google.comclass Interrupts 4313192Sgabeblack@google.com{ 4413192Sgabeblack@google.com 4513192Sgabeblack@google.com private: 4613192Sgabeblack@google.com 4713192Sgabeblack@google.com uint64_t interrupts[NumInterruptTypes]; 4813192Sgabeblack@google.com uint64_t intStatus; 4913192Sgabeblack@google.com 5013192Sgabeblack@google.com public: 5112940Sgabeblack@google.com Interrupts() 5212940Sgabeblack@google.com { 5312940Sgabeblack@google.com clear_all(); 5412940Sgabeblack@google.com } 5513192Sgabeblack@google.com 5613192Sgabeblack@google.com int InterruptLevel(uint64_t softint) 5713192Sgabeblack@google.com { 5813192Sgabeblack@google.com if (softint & 0x10000 || softint & 0x1) 5912940Sgabeblack@google.com return 14; 6012940Sgabeblack@google.com 6112946Sgabeblack@google.com int level = 15; 6212946Sgabeblack@google.com while (level > 0 && !(1 << level & softint)) 6312946Sgabeblack@google.com level--; 6413192Sgabeblack@google.com if (1 << level & softint) 6513192Sgabeblack@google.com return level; 6613192Sgabeblack@google.com return 0; 6713192Sgabeblack@google.com } 6813192Sgabeblack@google.com 6912946Sgabeblack@google.com void post(int int_num, int index) 7012946Sgabeblack@google.com { 7112946Sgabeblack@google.com DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index); 7212946Sgabeblack@google.com assert(int_num >= 0 && int_num < NumInterruptTypes); 7312946Sgabeblack@google.com assert(index >= 0 && index < 64); 7413192Sgabeblack@google.com 7513192Sgabeblack@google.com interrupts[int_num] |= ULL(1) << index; 7613192Sgabeblack@google.com intStatus |= ULL(1) << int_num; 7713192Sgabeblack@google.com } 7813192Sgabeblack@google.com 7912946Sgabeblack@google.com void clear(int int_num, int index) 8012946Sgabeblack@google.com { 8112940Sgabeblack@google.com DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index); 8212940Sgabeblack@google.com assert(int_num >= 0 && int_num < NumInterruptTypes); 8312940Sgabeblack@google.com assert(index >= 0 && index < 64); 8413192Sgabeblack@google.com 8512940Sgabeblack@google.com interrupts[int_num] &= ~(ULL(1) << index); 8612940Sgabeblack@google.com if (!interrupts[int_num]) 8712940Sgabeblack@google.com intStatus &= ~(ULL(1) << int_num); 88 } 89 90 void clear_all() 91 { 92 for (int i = 0; i < NumInterruptTypes; ++i) { 93 interrupts[i] = 0; 94 } 95 intStatus = 0; 96 } 97 98 bool check_interrupts(ThreadContext * tc) const 99 { 100 return intStatus; 101 } 102 103 Fault getInterrupt(ThreadContext * tc) 104 { 105 int hpstate = tc->readMiscReg(MISCREG_HPSTATE); 106 int pstate = tc->readMiscReg(MISCREG_PSTATE); 107 bool ie = pstate & PSTATE::ie; 108 109 // THESE ARE IN ORDER OF PRIORITY 110 // since there are early returns, and the highest 111 // priority interrupts should get serviced, 112 // it is v. important that new interrupts are inserted 113 // in the right order of processing 114 if (hpstate & HPSTATE::hpriv) { 115 if (ie) { 116 if (interrupts[IT_HINTP]) { 117 // This will be cleaned by a HINTP write 118 return new HstickMatch; 119 } 120 if (interrupts[IT_INT_VEC]) { 121 // this will be cleared by an ASI read (or write) 122 return new InterruptVector; 123 } 124 } 125 } else { 126 if (interrupts[IT_TRAP_LEVEL_ZERO]) { 127 // this is cleared by deasserting HPSTATE::tlz 128 return new TrapLevelZero; 129 } 130 // HStick matches always happen in priv mode (ie doesn't matter) 131 if (interrupts[IT_HINTP]) { 132 return new HstickMatch; 133 } 134 if (interrupts[IT_INT_VEC]) { 135 // this will be cleared by an ASI read (or write) 136 return new InterruptVector; 137 } 138 if (ie) { 139 if (interrupts[IT_CPU_MONDO]) { 140 return new CpuMondo; 141 } 142 if (interrupts[IT_DEV_MONDO]) { 143 return new DevMondo; 144 } 145 if (interrupts[IT_SOFT_INT]) { 146 return new 147 InterruptLevelN(InterruptLevel(interrupts[IT_SOFT_INT])); 148 } 149 150 if (interrupts[IT_RES_ERROR]) { 151 return new ResumableError; 152 } 153 } // !hpriv && ie 154 } // !hpriv 155 return NoFault; 156 } 157 158 void updateIntrInfo(ThreadContext * tc) 159 { 160 161 } 162 163 uint64_t get_vec(int int_num) 164 { 165 assert(int_num >= 0 && int_num < NumInterruptTypes); 166 return interrupts[int_num]; 167 } 168 169 void serialize(std::ostream &os) 170 { 171 SERIALIZE_ARRAY(interrupts,NumInterruptTypes); 172 SERIALIZE_SCALAR(intStatus); 173 } 174 175 void unserialize(Checkpoint *cp, const std::string §ion) 176 { 177 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes); 178 UNSERIALIZE_SCALAR(intStatus); 179 } 180}; 181} // namespace SPARC_ISA 182 183#endif // __ARCH_SPARC_INTERRUPT_HH__ 184