interrupts.cc revision 11320
1/* 2 * Copyright (c) 2009, 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Ali Saidi 38 */ 39 40#include "arch/arm/interrupts.hh" 41#include "arch/arm/system.hh" 42 43ArmISA::Interrupts * 44ArmInterruptsParams::create() 45{ 46 return new ArmISA::Interrupts(this); 47} 48 49bool 50ArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const 51{ 52 // Table G1-17~19 of ARM V8 ARM 53 InterruptMask mask; 54 bool highest_el_is_64 = ArmSystem::highestELIs64(tc); 55 56 CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 57 SCR scr; 58 HCR hcr; 59 hcr = tc->readMiscReg(MISCREG_HCR); 60 ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el); 61 bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit; 62 63 if (!highest_el_is_64) 64 scr = tc->readMiscReg(MISCREG_SCR); 65 else 66 scr = tc->readMiscReg(MISCREG_SCR_EL3); 67 68 bool is_secure = inSecureState(scr, cpsr); 69 70 switch(int_type) { 71 case INT_FIQ: 72 cpsr_mask_bit = cpsr.f; 73 scr_routing_bit = scr.fiq; 74 scr_fwaw_bit = scr.fw; 75 hcr_mask_override_bit = hcr.fmo; 76 break; 77 case INT_IRQ: 78 cpsr_mask_bit = cpsr.i; 79 scr_routing_bit = scr.irq; 80 scr_fwaw_bit = 1; 81 hcr_mask_override_bit = hcr.imo; 82 break; 83 case INT_ABT: 84 cpsr_mask_bit = cpsr.a; 85 scr_routing_bit = scr.ea; 86 scr_fwaw_bit = scr.aw; 87 hcr_mask_override_bit = hcr.amo; 88 break; 89 default: 90 panic("Unhandled interrupt type!"); 91 } 92 93 if (hcr.tge) 94 hcr_mask_override_bit = 1; 95 96 if (!highest_el_is_64) { 97 // AArch32 98 if (!scr_routing_bit) { 99 // SCR IRQ == 0 100 if (!hcr_mask_override_bit) 101 mask = INT_MASK_M; 102 else { 103 if (!is_secure && (el == EL0 || el == EL1)) 104 mask = INT_MASK_T; 105 else 106 mask = INT_MASK_M; 107 } 108 } else { 109 // SCR IRQ == 1 110 if ((!is_secure) && 111 (hcr_mask_override_bit || 112 (!scr_fwaw_bit && !hcr_mask_override_bit))) 113 mask = INT_MASK_T; 114 else 115 mask = INT_MASK_M; 116 } 117 } else { 118 // AArch64 119 if (!scr_routing_bit) { 120 // SCR IRQ == 0 121 if (!scr.rw) { 122 // SCR RW == 0 123 if (!hcr_mask_override_bit) { 124 if (el == EL3) 125 mask = INT_MASK_P; 126 else 127 mask = INT_MASK_M; 128 } else { 129 if (el == EL3) 130 mask = INT_MASK_T; 131 else if (is_secure || el == EL2) 132 mask = INT_MASK_M; 133 else 134 mask = INT_MASK_T; 135 } 136 } else { 137 // SCR RW == 1 138 if (!hcr_mask_override_bit) { 139 if (el == EL3 || el == EL2) 140 mask = INT_MASK_P; 141 else 142 mask = INT_MASK_M; 143 } else { 144 if (el == EL3) 145 mask = INT_MASK_P; 146 else if (is_secure || el == EL2) 147 mask = INT_MASK_M; 148 else 149 mask = INT_MASK_T; 150 } 151 } 152 } else { 153 // SCR IRQ == 1 154 if (el == EL3) 155 mask = INT_MASK_M; 156 else 157 mask = INT_MASK_T; 158 } 159 } 160 161 return ((mask == INT_MASK_T) || 162 ((mask == INT_MASK_M) && !cpsr_mask_bit)) && 163 (mask != INT_MASK_P); 164} 165 166