interrupts.cc revision 11793 
16145Snate@binkert.org/*
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356145Snate@binkert.org * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
366145Snate@binkert.org *
376145Snate@binkert.org * Authors: Ali Saidi
386145Snate@binkert.org */
396145Snate@binkert.org
406145Snate@binkert.org#include "arch/arm/interrupts.hh"
416145Snate@binkert.org
427002Snate@binkert.org#include "arch/arm/system.hh"
437002Snate@binkert.org
446154Snate@binkert.orgArmISA::Interrupts *
456154Snate@binkert.orgArmInterruptsParams::create()
466145Snate@binkert.org{
476145Snate@binkert.org    return new ArmISA::Interrupts(this);
486145Snate@binkert.org}
496145Snate@binkert.org
506145Snate@binkert.orgbool
516145Snate@binkert.orgArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const
526891SBrad.Beckmann@amd.com{
536145Snate@binkert.org    // Table G1-17~19 of ARM V8 ARM
546145Snate@binkert.org    InterruptMask mask;
556145Snate@binkert.org    bool highest_el_is_64 = ArmSystem::highestELIs64(tc);
566145Snate@binkert.org
576145Snate@binkert.org    CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
586285Snate@binkert.org    SCR scr;
596285Snate@binkert.org    HCR hcr;
606145Snate@binkert.org    hcr = tc->readMiscReg(MISCREG_HCR);
617002Snate@binkert.org    ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el);
626145Snate@binkert.org    bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit;
636145Snate@binkert.org
646145Snate@binkert.org    if (!highest_el_is_64)
656145Snate@binkert.org        scr = tc->readMiscReg(MISCREG_SCR);
666145Snate@binkert.org    else
676145Snate@binkert.org        scr = tc->readMiscReg(MISCREG_SCR_EL3);
686145Snate@binkert.org
696145Snate@binkert.org    bool is_secure = inSecureState(tc);
706145Snate@binkert.org
716145Snate@binkert.org    switch(int_type) {
726145Snate@binkert.org      case INT_FIQ:
736145Snate@binkert.org        cpsr_mask_bit = cpsr.f;
746145Snate@binkert.org        scr_routing_bit = scr.fiq;
757002Snate@binkert.org        scr_fwaw_bit = scr.fw;
766145Snate@binkert.org        hcr_mask_override_bit = hcr.fmo;
776145Snate@binkert.org        break;
786145Snate@binkert.org      case INT_IRQ:
796145Snate@binkert.org        cpsr_mask_bit = cpsr.i;
806145Snate@binkert.org        scr_routing_bit = scr.irq;
817002Snate@binkert.org        scr_fwaw_bit = 1;
826145Snate@binkert.org        hcr_mask_override_bit = hcr.imo;
836145Snate@binkert.org        break;
847002Snate@binkert.org      case INT_ABT:
856145Snate@binkert.org        cpsr_mask_bit = cpsr.a;
866145Snate@binkert.org        scr_routing_bit = scr.ea;
876145Snate@binkert.org        scr_fwaw_bit = scr.aw;
886145Snate@binkert.org        hcr_mask_override_bit = hcr.amo;
89        break;
90      default:
91        panic("Unhandled interrupt type!");
92    }
93
94    if (hcr.tge)
95        hcr_mask_override_bit = 1;
96
97    if (!highest_el_is_64) {
98        // AArch32
99        if (!scr_routing_bit) {
100            // SCR IRQ == 0
101            if (!hcr_mask_override_bit)
102                mask = INT_MASK_M;
103            else {
104                if (!is_secure && (el == EL0 || el == EL1))
105                    mask = INT_MASK_T;
106                else
107                    mask = INT_MASK_M;
108            }
109        } else {
110            // SCR IRQ == 1
111            if ((!is_secure) &&
112                (hcr_mask_override_bit ||
113                    (!scr_fwaw_bit && !hcr_mask_override_bit)))
114                mask = INT_MASK_T;
115            else
116                mask = INT_MASK_M;
117        }
118    } else {
119        // AArch64
120        if (!scr_routing_bit) {
121            // SCR IRQ == 0
122            if (!scr.rw) {
123                // SCR RW == 0
124                if (!hcr_mask_override_bit) {
125                    if (el == EL3)
126                        mask = INT_MASK_P;
127                    else
128                        mask = INT_MASK_M;
129                } else {
130                    if (el == EL3)
131                        mask = INT_MASK_T;
132                    else if (is_secure || el == EL2)
133                        mask = INT_MASK_M;
134                    else
135                        mask = INT_MASK_T;
136                }
137            } else {
138                // SCR RW == 1
139                if (!hcr_mask_override_bit) {
140                    if (el == EL3 || el == EL2)
141                        mask = INT_MASK_P;
142                    else
143                        mask = INT_MASK_M;
144                } else {
145                    if (el == EL3)
146                        mask = INT_MASK_P;
147                    else if (is_secure || el == EL2)
148                        mask = INT_MASK_M;
149                    else
150                        mask = INT_MASK_T;
151                }
152            }
153        } else {
154            // SCR IRQ == 1
155            if (el == EL3)
156                mask = INT_MASK_M;
157            else
158                mask = INT_MASK_T;
159        }
160    }
161
162    return ((mask == INT_MASK_T) ||
163            ((mask == INT_MASK_M) && !cpsr_mask_bit)) &&
164            (mask != INT_MASK_P);
165}
166
167