interrupts.cc revision 10037
16757SAli.Saidi@ARM.com/* 210037SARM gem5 Developers * Copyright (c) 2009, 2012-2013 ARM Limited 36757SAli.Saidi@ARM.com * All rights reserved. 46757SAli.Saidi@ARM.com * 57400SAli.Saidi@ARM.com * The license below extends only to copyright in the software and shall 67400SAli.Saidi@ARM.com * not be construed as granting a license to any other intellectual 77400SAli.Saidi@ARM.com * property including but not limited to intellectual property relating 87400SAli.Saidi@ARM.com * to a hardware implementation of the functionality of the software 97400SAli.Saidi@ARM.com * licensed hereunder. You may use the software subject to the license 107400SAli.Saidi@ARM.com * terms below provided that you ensure that this notice is replicated 117400SAli.Saidi@ARM.com * unmodified and in its entirety in all distributions of the software, 127400SAli.Saidi@ARM.com * modified or unmodified, in source code or in binary form. 137400SAli.Saidi@ARM.com * 146757SAli.Saidi@ARM.com * Redistribution and use in source and binary forms, with or without 156757SAli.Saidi@ARM.com * modification, are permitted provided that the following conditions are 166757SAli.Saidi@ARM.com * met: redistributions of source code must retain the above copyright 176757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer; 186757SAli.Saidi@ARM.com * redistributions in binary form must reproduce the above copyright 196757SAli.Saidi@ARM.com * notice, this list of conditions and the following disclaimer in the 206757SAli.Saidi@ARM.com * documentation and/or other materials provided with the distribution; 216757SAli.Saidi@ARM.com * neither the name of the copyright holders nor the names of its 226757SAli.Saidi@ARM.com * contributors may be used to endorse or promote products derived from 236757SAli.Saidi@ARM.com * this software without specific prior written permission. 246757SAli.Saidi@ARM.com * 256757SAli.Saidi@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 266757SAli.Saidi@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 276757SAli.Saidi@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 286757SAli.Saidi@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 296757SAli.Saidi@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 306757SAli.Saidi@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 316757SAli.Saidi@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 326757SAli.Saidi@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 336757SAli.Saidi@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 346757SAli.Saidi@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 356757SAli.Saidi@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 366757SAli.Saidi@ARM.com * 376757SAli.Saidi@ARM.com * Authors: Ali Saidi 386757SAli.Saidi@ARM.com */ 396757SAli.Saidi@ARM.com 406757SAli.Saidi@ARM.com#include "arch/arm/interrupts.hh" 4110037SARM gem5 Developers#include "arch/arm/system.hh" 426757SAli.Saidi@ARM.com 436757SAli.Saidi@ARM.comArmISA::Interrupts * 446757SAli.Saidi@ARM.comArmInterruptsParams::create() 456757SAli.Saidi@ARM.com{ 466757SAli.Saidi@ARM.com return new ArmISA::Interrupts(this); 476757SAli.Saidi@ARM.com} 4810037SARM gem5 Developers 4910037SARM gem5 Developersbool 5010037SARM gem5 DevelopersArmISA::Interrupts::takeInt(ThreadContext *tc, InterruptTypes int_type) const 5110037SARM gem5 Developers{ 5210037SARM gem5 Developers // Table G1-17~19 of ARM V8 ARM 5310037SARM gem5 Developers InterruptMask mask; 5410037SARM gem5 Developers bool highest_el_is_64 = ArmSystem::highestELIs64(tc); 5510037SARM gem5 Developers 5610037SARM gem5 Developers CPSR cpsr = tc->readMiscReg(MISCREG_CPSR); 5710037SARM gem5 Developers SCR scr; 5810037SARM gem5 Developers HCR hcr; 5910037SARM gem5 Developers hcr = tc->readMiscReg(MISCREG_HCR); 6010037SARM gem5 Developers ExceptionLevel el = (ExceptionLevel) ((uint32_t) cpsr.el); 6110037SARM gem5 Developers bool cpsr_mask_bit, scr_routing_bit, scr_fwaw_bit, hcr_mask_override_bit; 6210037SARM gem5 Developers 6310037SARM gem5 Developers if (!highest_el_is_64) 6410037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR); 6510037SARM gem5 Developers else 6610037SARM gem5 Developers scr = tc->readMiscReg(MISCREG_SCR_EL3); 6710037SARM gem5 Developers 6810037SARM gem5 Developers bool is_secure = inSecureState(scr, cpsr); 6910037SARM gem5 Developers 7010037SARM gem5 Developers switch(int_type) { 7110037SARM gem5 Developers case INT_FIQ: 7210037SARM gem5 Developers cpsr_mask_bit = cpsr.f; 7310037SARM gem5 Developers scr_routing_bit = scr.fiq; 7410037SARM gem5 Developers scr_fwaw_bit = scr.fw; 7510037SARM gem5 Developers hcr_mask_override_bit = hcr.fmo; 7610037SARM gem5 Developers break; 7710037SARM gem5 Developers case INT_IRQ: 7810037SARM gem5 Developers cpsr_mask_bit = cpsr.i; 7910037SARM gem5 Developers scr_routing_bit = scr.irq; 8010037SARM gem5 Developers scr_fwaw_bit = 1; 8110037SARM gem5 Developers hcr_mask_override_bit = hcr.imo; 8210037SARM gem5 Developers break; 8310037SARM gem5 Developers case INT_ABT: 8410037SARM gem5 Developers cpsr_mask_bit = cpsr.a; 8510037SARM gem5 Developers scr_routing_bit = scr.ea; 8610037SARM gem5 Developers scr_fwaw_bit = scr.aw; 8710037SARM gem5 Developers hcr_mask_override_bit = hcr.amo; 8810037SARM gem5 Developers break; 8910037SARM gem5 Developers default: 9010037SARM gem5 Developers panic("Unhandled interrupt type!"); 9110037SARM gem5 Developers } 9210037SARM gem5 Developers 9310037SARM gem5 Developers if (hcr.tge) 9410037SARM gem5 Developers hcr_mask_override_bit = 1; 9510037SARM gem5 Developers 9610037SARM gem5 Developers if (!highest_el_is_64) { 9710037SARM gem5 Developers // AArch32 9810037SARM gem5 Developers if (!scr_routing_bit) { 9910037SARM gem5 Developers // SCR IRQ == 0 10010037SARM gem5 Developers if (!hcr_mask_override_bit) 10110037SARM gem5 Developers mask = INT_MASK_M; 10210037SARM gem5 Developers else { 10310037SARM gem5 Developers if (!is_secure && (el == EL0 || el == EL1)) 10410037SARM gem5 Developers mask = INT_MASK_T; 10510037SARM gem5 Developers else 10610037SARM gem5 Developers mask = INT_MASK_M; 10710037SARM gem5 Developers } 10810037SARM gem5 Developers } else { 10910037SARM gem5 Developers // SCR IRQ == 1 11010037SARM gem5 Developers if ((!is_secure) && 11110037SARM gem5 Developers (hcr_mask_override_bit || 11210037SARM gem5 Developers (!scr_fwaw_bit && !hcr_mask_override_bit))) 11310037SARM gem5 Developers mask = INT_MASK_T; 11410037SARM gem5 Developers else 11510037SARM gem5 Developers mask = INT_MASK_M; 11610037SARM gem5 Developers } 11710037SARM gem5 Developers } else { 11810037SARM gem5 Developers // AArch64 11910037SARM gem5 Developers if (!scr_routing_bit) { 12010037SARM gem5 Developers // SCR IRQ == 0 12110037SARM gem5 Developers if (!scr.rw) { 12210037SARM gem5 Developers // SCR RW == 0 12310037SARM gem5 Developers if (!hcr_mask_override_bit) { 12410037SARM gem5 Developers if (el == EL3) 12510037SARM gem5 Developers mask = INT_MASK_P; 12610037SARM gem5 Developers else 12710037SARM gem5 Developers mask = INT_MASK_M; 12810037SARM gem5 Developers } else { 12910037SARM gem5 Developers if (el == EL3) 13010037SARM gem5 Developers mask = INT_MASK_T; 13110037SARM gem5 Developers else if (is_secure || el == EL2) 13210037SARM gem5 Developers mask = INT_MASK_M; 13310037SARM gem5 Developers else 13410037SARM gem5 Developers mask = INT_MASK_T; 13510037SARM gem5 Developers } 13610037SARM gem5 Developers } else { 13710037SARM gem5 Developers // SCR RW == 1 13810037SARM gem5 Developers if (!hcr_mask_override_bit) { 13910037SARM gem5 Developers if (el == EL3 || el == EL2) 14010037SARM gem5 Developers mask = INT_MASK_P; 14110037SARM gem5 Developers else 14210037SARM gem5 Developers mask = INT_MASK_M; 14310037SARM gem5 Developers } else { 14410037SARM gem5 Developers if (el == EL3) 14510037SARM gem5 Developers mask = INT_MASK_P; 14610037SARM gem5 Developers else if (is_secure || el == EL2) 14710037SARM gem5 Developers mask = INT_MASK_M; 14810037SARM gem5 Developers else 14910037SARM gem5 Developers mask = INT_MASK_T; 15010037SARM gem5 Developers } 15110037SARM gem5 Developers } 15210037SARM gem5 Developers } else { 15310037SARM gem5 Developers // SCR IRQ == 1 15410037SARM gem5 Developers if (el == EL3) 15510037SARM gem5 Developers mask = INT_MASK_M; 15610037SARM gem5 Developers else 15710037SARM gem5 Developers mask = INT_MASK_T; 15810037SARM gem5 Developers } 15910037SARM gem5 Developers } 16010037SARM gem5 Developers 16110037SARM gem5 Developers return ((mask == INT_MASK_T) || 16210037SARM gem5 Developers ((mask == INT_MASK_M) && !cpsr_mask_bit)) && 16310037SARM gem5 Developers (mask != INT_MASK_P); 16410037SARM gem5 Developers} 16510037SARM gem5 Developers 166