vfp.hh revision 7376:3b781776b2d9 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_VFP_HH__
41#define __ARCH_ARM_INSTS_VFP_HH__
42
43#include "arch/arm/insts/misc.hh"
44
45enum VfpMicroMode {
46    VfpNotAMicroop,
47    VfpMicroop,
48    VfpFirstMicroop,
49    VfpLastMicroop
50};
51
52template<class T>
53static inline void
54setVfpMicroFlags(VfpMicroMode mode, T &flags)
55{
56    switch (mode) {
57      case VfpMicroop:
58        flags[StaticInst::IsMicroop] = true;
59        break;
60      case VfpFirstMicroop:
61        flags[StaticInst::IsMicroop] =
62            flags[StaticInst::IsFirstMicroop] = true;
63        break;
64      case VfpLastMicroop:
65        flags[StaticInst::IsMicroop] =
66            flags[StaticInst::IsLastMicroop] = true;
67        break;
68      case VfpNotAMicroop:
69        break;
70    }
71    if (mode == VfpMicroop || mode == VfpFirstMicroop) {
72        flags[StaticInst::IsDelayedCommit] = true;
73    }
74}
75
76class VfpMacroOp : public PredMacroOp
77{
78  public:
79    static bool
80    inScalarBank(IntRegIndex idx)
81    {
82        return (idx % 32) < 8;
83    }
84
85  protected:
86    bool wide;
87
88    VfpMacroOp(const char *mnem, ExtMachInst _machInst,
89            OpClass __opClass, bool _wide) :
90        PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
91    {}
92
93    IntRegIndex
94    addStride(IntRegIndex idx, unsigned stride)
95    {
96        if (wide) {
97            stride *= 2;
98        }
99        unsigned offset = idx % 8;
100        idx = (IntRegIndex)(idx - offset);
101        offset += stride;
102        idx = (IntRegIndex)(idx + (offset % 8));
103        return idx;
104    }
105
106    void
107    nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
108    {
109        unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
110        assert(!inScalarBank(dest));
111        dest = addStride(dest, stride);
112        op1 = addStride(op1, stride);
113        if (!inScalarBank(op2)) {
114            op2 = addStride(op2, stride);
115        }
116    }
117
118    void
119    nextIdxs(IntRegIndex &dest, IntRegIndex &op1)
120    {
121        unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
122        assert(!inScalarBank(dest));
123        dest = addStride(dest, stride);
124        if (!inScalarBank(op1)) {
125            op1 = addStride(op1, stride);
126        }
127    }
128
129    void
130    nextIdxs(IntRegIndex &dest)
131    {
132        unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
133        assert(!inScalarBank(dest));
134        dest = addStride(dest, stride);
135    }
136};
137
138class VfpRegRegOp : public RegRegOp
139{
140  protected:
141    VfpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
142                IntRegIndex _dest, IntRegIndex _op1,
143                VfpMicroMode mode = VfpNotAMicroop) :
144        RegRegOp(mnem, _machInst, __opClass, _dest, _op1)
145    {
146        setVfpMicroFlags(mode, flags);
147    }
148};
149
150class VfpRegImmOp : public RegImmOp
151{
152  protected:
153    VfpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
154                IntRegIndex _dest, uint64_t _imm,
155                VfpMicroMode mode = VfpNotAMicroop) :
156        RegImmOp(mnem, _machInst, __opClass, _dest, _imm)
157    {
158        setVfpMicroFlags(mode, flags);
159    }
160};
161
162class VfpRegRegImmOp : public RegRegImmOp
163{
164  protected:
165    VfpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
166                   IntRegIndex _dest, IntRegIndex _op1,
167                   uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
168        RegRegImmOp(mnem, _machInst, __opClass, _dest, _op1, _imm)
169    {
170        setVfpMicroFlags(mode, flags);
171    }
172};
173
174class VfpRegRegRegOp : public RegRegRegOp
175{
176  protected:
177    VfpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
178                   IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
179                   VfpMicroMode mode = VfpNotAMicroop) :
180        RegRegRegOp(mnem, _machInst, __opClass, _dest, _op1, _op2)
181    {
182        setVfpMicroFlags(mode, flags);
183    }
184};
185
186#endif //__ARCH_ARM_INSTS_VFP_HH__
187