static_inst.hh revision 8809:bb10807da889 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "arch/arm/utility.hh"
47#include "base/trace.hh"
48#include "cpu/static_inst.hh"
49#include "sim/byteswap.hh"
50#include "sim/full_system.hh"
51
52namespace ArmISA
53{
54
55class ArmStaticInst : public StaticInst
56{
57  protected:
58    int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
59                         uint32_t type, uint32_t cfval) const;
60    int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
61                        uint32_t type, uint32_t cfval) const;
62
63    bool shift_carry_imm(uint32_t base, uint32_t shamt,
64                         uint32_t type, uint32_t cfval) const;
65    bool shift_carry_rs(uint32_t base, uint32_t shamt,
66                        uint32_t type, uint32_t cfval) const;
67
68    template<int width>
69    static inline bool
70    saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
71    {
72        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
73        if (bits(midRes, width) != bits(midRes, width - 1)) {
74            if (midRes > 0)
75                res = (LL(1) << (width - 1)) - 1;
76            else
77                res = -(LL(1) << (width - 1));
78            return true;
79        } else {
80            res = midRes;
81            return false;
82        }
83    }
84
85    static inline bool
86    satInt(int32_t &res, int64_t op, int width)
87    {
88        width--;
89        if (op >= (LL(1) << width)) {
90            res = (LL(1) << width) - 1;
91            return true;
92        } else if (op < -(LL(1) << width)) {
93            res = -(LL(1) << width);
94            return true;
95        } else {
96            res = op;
97            return false;
98        }
99    }
100
101    template<int width>
102    static inline bool
103    uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
104    {
105        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
106        if (midRes >= (LL(1) << width)) {
107            res = (LL(1) << width) - 1;
108            return true;
109        } else if (midRes < 0) {
110            res = 0;
111            return true;
112        } else {
113            res = midRes;
114            return false;
115        }
116    }
117
118    static inline bool
119    uSatInt(int32_t &res, int64_t op, int width)
120    {
121        if (op >= (LL(1) << width)) {
122            res = (LL(1) << width) - 1;
123            return true;
124        } else if (op < 0) {
125            res = 0;
126            return true;
127        } else {
128            res = op;
129            return false;
130        }
131    }
132
133    // Constructor
134    ArmStaticInst(const char *mnem, ExtMachInst _machInst,
135                  OpClass __opClass)
136        : StaticInst(mnem, _machInst, __opClass)
137    {
138    }
139
140    /// Print a register name for disassembly given the unique
141    /// dependence tag number (FP or int).
142    void printReg(std::ostream &os, int reg) const;
143    void printMnemonic(std::ostream &os,
144                       const std::string &suffix = "",
145                       bool withPred = true) const;
146    void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
147                        const std::string &prefix, const Addr addr,
148                        const std::string &suffix) const;
149    void printShiftOperand(std::ostream &os, IntRegIndex rm,
150                           bool immShift, uint32_t shiftAmt,
151                           IntRegIndex rs, ArmShiftType type) const;
152
153
154    void printDataInst(std::ostream &os, bool withImm) const;
155    void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
156                       IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
157                       IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
158                       uint32_t imm) const;
159
160    void
161    advancePC(PCState &pcState) const
162    {
163        pcState.advance();
164    }
165
166    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
167
168    static inline uint32_t
169    cpsrWriteByInstr(CPSR cpsr, uint32_t val,
170            uint8_t byteMask, bool affectState, bool nmfi)
171    {
172        bool privileged = (cpsr.mode != MODE_USER);
173
174        uint32_t bitMask = 0;
175
176        if (bits(byteMask, 3)) {
177            unsigned lowIdx = affectState ? 24 : 27;
178            bitMask = bitMask | mask(31, lowIdx);
179        }
180        if (bits(byteMask, 2)) {
181            bitMask = bitMask | mask(19, 16);
182        }
183        if (bits(byteMask, 1)) {
184            unsigned highIdx = affectState ? 15 : 9;
185            unsigned lowIdx = privileged ? 8 : 9;
186            bitMask = bitMask | mask(highIdx, lowIdx);
187        }
188        if (bits(byteMask, 0)) {
189            if (privileged) {
190                bitMask = bitMask | mask(7, 6);
191                if (!badMode((OperatingMode)(val & mask(5)))) {
192                    bitMask = bitMask | mask(5);
193                } else {
194                    warn_once("Ignoring write of bad mode to CPSR.\n");
195                }
196            }
197            if (affectState)
198                bitMask = bitMask | (1 << 5);
199        }
200
201        bool cpsr_f = cpsr.f;
202        uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
203        if (nmfi && !cpsr_f)
204            new_cpsr &= ~(1 << 6);
205        return new_cpsr;
206    }
207
208    static inline uint32_t
209    spsrWriteByInstr(uint32_t spsr, uint32_t val,
210            uint8_t byteMask, bool affectState)
211    {
212        uint32_t bitMask = 0;
213
214        if (bits(byteMask, 3))
215            bitMask = bitMask | mask(31, 24);
216        if (bits(byteMask, 2))
217            bitMask = bitMask | mask(19, 16);
218        if (bits(byteMask, 1))
219            bitMask = bitMask | mask(15, 8);
220        if (bits(byteMask, 0))
221            bitMask = bitMask | mask(7, 0);
222
223        return ((spsr & ~bitMask) | (val & bitMask));
224    }
225
226    template<class XC>
227    static inline Addr
228    readPC(XC *xc)
229    {
230        return xc->pcState().instPC();
231    }
232
233    template<class XC>
234    static inline void
235    setNextPC(XC *xc, Addr val)
236    {
237        PCState pc = xc->pcState();
238        pc.instNPC(val);
239        xc->pcState(pc);
240    }
241
242    template<class T>
243    static inline T
244    cSwap(T val, bool big)
245    {
246        if (big) {
247            return gtobe(val);
248        } else {
249            return gtole(val);
250        }
251    }
252
253    template<class T, class E>
254    static inline T
255    cSwap(T val, bool big)
256    {
257        const unsigned count = sizeof(T) / sizeof(E);
258        union {
259            T tVal;
260            E eVals[count];
261        } conv;
262        conv.tVal = htog(val);
263        if (big) {
264            for (unsigned i = 0; i < count; i++) {
265                conv.eVals[i] = gtobe(conv.eVals[i]);
266            }
267        } else {
268            for (unsigned i = 0; i < count; i++) {
269                conv.eVals[i] = gtole(conv.eVals[i]);
270            }
271        }
272        return gtoh(conv.tVal);
273    }
274
275    // Perform an interworking branch.
276    template<class XC>
277    static inline void
278    setIWNextPC(XC *xc, Addr val)
279    {
280        PCState pc = xc->pcState();
281        pc.instIWNPC(val);
282        xc->pcState(pc);
283    }
284
285    // Perform an interworking branch in ARM mode, a regular branch
286    // otherwise.
287    template<class XC>
288    static inline void
289    setAIWNextPC(XC *xc, Addr val)
290    {
291        PCState pc = xc->pcState();
292        pc.instAIWNPC(val);
293        xc->pcState(pc);
294    }
295
296    inline Fault
297    disabledFault() const
298    {
299        if (FullSystem) {
300            return new UndefinedInstruction();
301        } else {
302            return new UndefinedInstruction(machInst, false, mnemonic, true);
303        }
304    }
305};
306}
307
308#endif //__ARCH_ARM_INSTS_STATICINST_HH__
309