static_inst.hh revision 7640:5286a8a469c5 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "arch/arm/faults.hh"
46#include "base/trace.hh"
47#include "cpu/static_inst.hh"
48
49namespace ArmISA
50{
51
52class ArmStaticInst : public StaticInst
53{
54  protected:
55    int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
56                         uint32_t type, uint32_t cfval) const;
57    int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
58                        uint32_t type, uint32_t cfval) const;
59
60    bool shift_carry_imm(uint32_t base, uint32_t shamt,
61                         uint32_t type, uint32_t cfval) const;
62    bool shift_carry_rs(uint32_t base, uint32_t shamt,
63                        uint32_t type, uint32_t cfval) const;
64
65    template<int width>
66    static inline bool
67    saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
68    {
69        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
70        if (bits(midRes, width) != bits(midRes, width - 1)) {
71            if (midRes > 0)
72                res = (LL(1) << (width - 1)) - 1;
73            else
74                res = -(LL(1) << (width - 1));
75            return true;
76        } else {
77            res = midRes;
78            return false;
79        }
80    }
81
82    static inline bool
83    satInt(int32_t &res, int64_t op, int width)
84    {
85        width--;
86        if (op >= (LL(1) << width)) {
87            res = (LL(1) << width) - 1;
88            return true;
89        } else if (op < -(LL(1) << width)) {
90            res = -(LL(1) << width);
91            return true;
92        } else {
93            res = op;
94            return false;
95        }
96    }
97
98    template<int width>
99    static inline bool
100    uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
101    {
102        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
103        if (midRes >= (LL(1) << width)) {
104            res = (LL(1) << width) - 1;
105            return true;
106        } else if (midRes < 0) {
107            res = 0;
108            return true;
109        } else {
110            res = midRes;
111            return false;
112        }
113    }
114
115    static inline bool
116    uSatInt(int32_t &res, int64_t op, int width)
117    {
118        if (op >= (LL(1) << width)) {
119            res = (LL(1) << width) - 1;
120            return true;
121        } else if (op < 0) {
122            res = 0;
123            return true;
124        } else {
125            res = op;
126            return false;
127        }
128    }
129
130    // Constructor
131    ArmStaticInst(const char *mnem, ExtMachInst _machInst,
132                  OpClass __opClass)
133        : StaticInst(mnem, _machInst, __opClass)
134    {
135    }
136
137    /// Print a register name for disassembly given the unique
138    /// dependence tag number (FP or int).
139    void printReg(std::ostream &os, int reg) const;
140    void printMnemonic(std::ostream &os,
141                       const std::string &suffix = "",
142                       bool withPred = true) const;
143    void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
144                        const std::string &prefix, const Addr addr,
145                        const std::string &suffix) const;
146    void printShiftOperand(std::ostream &os, IntRegIndex rm,
147                           bool immShift, uint32_t shiftAmt,
148                           IntRegIndex rs, ArmShiftType type) const;
149
150
151    void printDataInst(std::ostream &os, bool withImm) const;
152    void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
153                       IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
154                       IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
155                       uint32_t imm) const;
156
157    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
158
159    static inline uint32_t
160    cpsrWriteByInstr(CPSR cpsr, uint32_t val,
161            uint8_t byteMask, bool affectState, bool nmfi)
162    {
163        bool privileged = (cpsr.mode != MODE_USER);
164
165        uint32_t bitMask = 0;
166
167        if (bits(byteMask, 3)) {
168            unsigned lowIdx = affectState ? 24 : 27;
169            bitMask = bitMask | mask(31, lowIdx);
170        }
171        if (bits(byteMask, 2)) {
172            bitMask = bitMask | mask(19, 16);
173        }
174        if (bits(byteMask, 1)) {
175            unsigned highIdx = affectState ? 15 : 9;
176            unsigned lowIdx = privileged ? 8 : 9;
177            bitMask = bitMask | mask(highIdx, lowIdx);
178        }
179        if (bits(byteMask, 0)) {
180            if (privileged) {
181                bitMask = bitMask | mask(7, 6);
182                if (!badMode((OperatingMode)(val & mask(5)))) {
183                    bitMask = bitMask | mask(5);
184                } else {
185                    warn_once("Ignoring write of bad mode to CPSR.\n");
186                }
187            }
188            if (affectState)
189                bitMask = bitMask | (1 << 5);
190        }
191
192        bool cpsr_f = cpsr.f;
193        uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
194        if (nmfi && !cpsr_f)
195            new_cpsr &= ~(1 << 6);
196        return new_cpsr;
197    }
198
199    static inline uint32_t
200    spsrWriteByInstr(uint32_t spsr, uint32_t val,
201            uint8_t byteMask, bool affectState)
202    {
203        uint32_t bitMask = 0;
204
205        if (bits(byteMask, 3))
206            bitMask = bitMask | mask(31, 24);
207        if (bits(byteMask, 2))
208            bitMask = bitMask | mask(19, 16);
209        if (bits(byteMask, 1))
210            bitMask = bitMask | mask(15, 8);
211        if (bits(byteMask, 0))
212            bitMask = bitMask | mask(7, 0);
213
214        return ((spsr & ~bitMask) | (val & bitMask));
215    }
216
217    template<class XC>
218    static inline Addr
219    readPC(XC *xc)
220    {
221        Addr pc = xc->readPC();
222        Addr tBit = pc & (ULL(1) << PcTBitShift);
223        if (tBit)
224            return pc + 4;
225        else
226            return pc + 8;
227    }
228
229    // Perform an regular branch.
230    template<class XC>
231    static inline void
232    setNextPC(XC *xc, Addr val)
233    {
234        Addr npc = xc->readNextPC();
235        if (npc & (ULL(1) << PcTBitShift)) {
236            val &= ~mask(1);
237        } else {
238            val &= ~mask(2);
239        }
240        xc->setNextPC((npc & PcModeMask) |
241                      (val & ~PcModeMask));
242    }
243
244    template<class T>
245    static inline T
246    cSwap(T val, bool big)
247    {
248        if (big) {
249            return gtobe(val);
250        } else {
251            return gtole(val);
252        }
253    }
254
255    template<class T, class E>
256    static inline T
257    cSwap(T val, bool big)
258    {
259        const unsigned count = sizeof(T) / sizeof(E);
260        union {
261            T tVal;
262            E eVals[count];
263        } conv;
264        conv.tVal = htog(val);
265        if (big) {
266            for (unsigned i = 0; i < count; i++) {
267                conv.eVals[i] = gtobe(conv.eVals[i]);
268            }
269        } else {
270            for (unsigned i = 0; i < count; i++) {
271                conv.eVals[i] = gtole(conv.eVals[i]);
272            }
273        }
274        return gtoh(conv.tVal);
275    }
276
277    // Perform an interworking branch.
278    template<class XC>
279    static inline void
280    setIWNextPC(XC *xc, Addr val)
281    {
282        Addr stateBits = xc->readPC() & PcModeMask;
283        Addr jBit = (ULL(1) << PcJBitShift);
284        Addr tBit = (ULL(1) << PcTBitShift);
285        bool thumbEE = (stateBits == (tBit | jBit));
286
287        Addr newPc = (val & ~PcModeMask);
288        if (thumbEE) {
289            if (bits(newPc, 0)) {
290                newPc = newPc & ~mask(1);
291            } else {
292                panic("Bad thumbEE interworking branch address %#x.\n", newPc);
293            }
294        } else {
295            if (bits(newPc, 0)) {
296                stateBits = tBit;
297                newPc = newPc & ~mask(1);
298            } else if (!bits(newPc, 1)) {
299                stateBits = 0;
300            } else {
301                warn("Bad interworking branch address %#x.\n", newPc);
302            }
303        }
304        newPc = newPc | stateBits;
305        xc->setNextPC(newPc);
306    }
307
308    // Perform an interworking branch in ARM mode, a regular branch
309    // otherwise.
310    template<class XC>
311    static inline void
312    setAIWNextPC(XC *xc, Addr val)
313    {
314        Addr stateBits = xc->readPC() & PcModeMask;
315        Addr jBit = (ULL(1) << PcJBitShift);
316        Addr tBit = (ULL(1) << PcTBitShift);
317        if (!jBit && !tBit) {
318            setIWNextPC(xc, val);
319        } else {
320            setNextPC(xc, val);
321        }
322    }
323
324    inline Fault
325    disabledFault() const
326    {
327#if FULL_SYSTEM
328            return new UndefinedInstruction();
329#else
330            return new UndefinedInstruction(machInst, false, mnemonic, true);
331#endif
332    }
333};
334}
335
336#endif //__ARCH_ARM_INSTS_STATICINST_HH__
337