static_inst.hh revision 7400:f6c9b27c4dbe
12623SN/A/* 22623SN/A * Copyright (c) 2010 ARM Limited 32623SN/A * All rights reserved 42623SN/A * 52623SN/A * The license below extends only to copyright in the software and shall 62623SN/A * not be construed as granting a license to any other intellectual 72623SN/A * property including but not limited to intellectual property relating 82623SN/A * to a hardware implementation of the functionality of the software 92623SN/A * licensed hereunder. You may use the software subject to the license 102623SN/A * terms below provided that you ensure that this notice is replicated 112623SN/A * unmodified and in its entirety in all distributions of the software, 122623SN/A * modified or unmodified, in source code or in binary form. 132623SN/A * 142623SN/A * Copyright (c) 2007-2008 The Florida State University 152623SN/A * All rights reserved. 162623SN/A * 172623SN/A * Redistribution and use in source and binary forms, with or without 182623SN/A * modification, are permitted provided that the following conditions are 192623SN/A * met: redistributions of source code must retain the above copyright 202623SN/A * notice, this list of conditions and the following disclaimer; 212623SN/A * redistributions in binary form must reproduce the above copyright 222623SN/A * notice, this list of conditions and the following disclaimer in the 232623SN/A * documentation and/or other materials provided with the distribution; 242623SN/A * neither the name of the copyright holders nor the names of its 252623SN/A * contributors may be used to endorse or promote products derived from 262623SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292623SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302623SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 313170Sstever@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322623SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332623SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342623SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352623SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362623SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372901Ssaidi@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382623SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392623SN/A * 402623SN/A * Authors: Stephen Hines 412623SN/A */ 422856Srdreslin@umich.edu#ifndef __ARCH_ARM_INSTS_STATICINST_HH__ 432856Srdreslin@umich.edu#define __ARCH_ARM_INSTS_STATICINST_HH__ 442856Srdreslin@umich.edu 452856Srdreslin@umich.edu#include "base/trace.hh" 462856Srdreslin@umich.edu#include "cpu/static_inst.hh" 472856Srdreslin@umich.edu 482856Srdreslin@umich.edunamespace ArmISA 492856Srdreslin@umich.edu{ 502856Srdreslin@umich.educlass ArmStaticInst : public StaticInst 512856Srdreslin@umich.edu{ 522623SN/A protected: 532623SN/A int32_t shift_rm_imm(uint32_t base, uint32_t shamt, 542623SN/A uint32_t type, uint32_t cfval) const; 552623SN/A int32_t shift_rm_rs(uint32_t base, uint32_t shamt, 562623SN/A uint32_t type, uint32_t cfval) const; 572623SN/A 582680Sktlim@umich.edu bool shift_carry_imm(uint32_t base, uint32_t shamt, 592680Sktlim@umich.edu uint32_t type, uint32_t cfval) const; 602623SN/A bool shift_carry_rs(uint32_t base, uint32_t shamt, 612623SN/A uint32_t type, uint32_t cfval) const; 622680Sktlim@umich.edu 632623SN/A template<int width> 642623SN/A static bool 652623SN/A saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false) 662623SN/A { 672623SN/A int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 682630SN/A if (bits(midRes, width) != bits(midRes, width - 1)) { 692623SN/A if (midRes > 0) 702623SN/A res = (LL(1) << (width - 1)) - 1; 712623SN/A else 722623SN/A res = -(LL(1) << (width - 1)); 732623SN/A return true; 742623SN/A } else { 752630SN/A res = midRes; 762623SN/A return false; 773184Srdreslin@umich.edu } 783184Srdreslin@umich.edu } 792623SN/A 802623SN/A static bool 812623SN/A satInt(int32_t &res, int64_t op, int width) 822623SN/A { 832623SN/A width--; 842631SN/A if (op >= (LL(1) << width)) { 852631SN/A res = (LL(1) << width) - 1; 862631SN/A return true; 872623SN/A } else if (op < -(LL(1) << width)) { 882623SN/A res = -(LL(1) << width); 892623SN/A return true; 902948Ssaidi@eecs.umich.edu } else { 912948Ssaidi@eecs.umich.edu res = op; 922948Ssaidi@eecs.umich.edu return false; 932948Ssaidi@eecs.umich.edu } 942948Ssaidi@eecs.umich.edu } 952948Ssaidi@eecs.umich.edu 962948Ssaidi@eecs.umich.edu template<int width> 972948Ssaidi@eecs.umich.edu static bool 982623SN/A uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false) 993170Sstever@eecs.umich.edu { 1003170Sstever@eecs.umich.edu int64_t midRes = sub ? (op1 - op2) : (op1 + op2); 1012623SN/A if (midRes >= (LL(1) << width)) { 1022623SN/A res = (LL(1) << width) - 1; 1032623SN/A return true; 1042839Sktlim@umich.edu } else if (midRes < 0) { 1052867Sktlim@umich.edu res = 0; 1063222Sktlim@umich.edu return true; 1072901Ssaidi@eecs.umich.edu } else { 1082623SN/A res = midRes; 1092623SN/A return false; 1102623SN/A } 1112623SN/A } 1122623SN/A 1132623SN/A static bool 1142623SN/A uSatInt(int32_t &res, int64_t op, int width) 1152623SN/A { 1162623SN/A if (op >= (LL(1) << width)) { 1172623SN/A res = (LL(1) << width) - 1; 1182915Sktlim@umich.edu return true; 1192915Sktlim@umich.edu } else if (op < 0) { 1202623SN/A res = 0; 1212623SN/A return true; 1222623SN/A } else { 1232623SN/A res = op; 1242623SN/A return false; 1252623SN/A } 1262915Sktlim@umich.edu } 1272915Sktlim@umich.edu 1282623SN/A // Constructor 1292798Sktlim@umich.edu ArmStaticInst(const char *mnem, ExtMachInst _machInst, 1302798Sktlim@umich.edu OpClass __opClass) 1312901Ssaidi@eecs.umich.edu : StaticInst(mnem, _machInst, __opClass) 1322839Sktlim@umich.edu { 1332798Sktlim@umich.edu } 1342839Sktlim@umich.edu 1352798Sktlim@umich.edu /// Print a register name for disassembly given the unique 1362798Sktlim@umich.edu /// dependence tag number (FP or int). 1372901Ssaidi@eecs.umich.edu void printReg(std::ostream &os, int reg) const; 1382901Ssaidi@eecs.umich.edu void printMnemonic(std::ostream &os, 1392798Sktlim@umich.edu const std::string &suffix = "", 1402839Sktlim@umich.edu bool withPred = true) const; 1412839Sktlim@umich.edu void printMemSymbol(std::ostream &os, const SymbolTable *symtab, 1422901Ssaidi@eecs.umich.edu const std::string &prefix, const Addr addr, 1432798Sktlim@umich.edu const std::string &suffix) const; 1442623SN/A void printShiftOperand(std::ostream &os, IntRegIndex rm, 1452623SN/A bool immShift, uint32_t shiftAmt, 1462623SN/A IntRegIndex rs, ArmShiftType type) const; 1472798Sktlim@umich.edu 1482623SN/A 1492798Sktlim@umich.edu void printDataInst(std::ostream &os, bool withImm) const; 1503201Shsul@eecs.umich.edu void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s, 1513201Shsul@eecs.umich.edu IntRegIndex rd, IntRegIndex rn, IntRegIndex rm, 1522867Sktlim@umich.edu IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type, 1532867Sktlim@umich.edu uint32_t imm) const; 1542915Sktlim@umich.edu 1552915Sktlim@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1562915Sktlim@umich.edu 1572867Sktlim@umich.edu static uint32_t 1582867Sktlim@umich.edu cpsrWriteByInstr(CPSR cpsr, uint32_t val, 1592867Sktlim@umich.edu uint8_t byteMask, bool affectState, bool nmfi) 1602867Sktlim@umich.edu { 1612867Sktlim@umich.edu bool privileged = (cpsr.mode != MODE_USER); 1622867Sktlim@umich.edu 1632623SN/A uint32_t bitMask = 0; 1642798Sktlim@umich.edu 1652901Ssaidi@eecs.umich.edu if (bits(byteMask, 3)) { 1663222Sktlim@umich.edu unsigned lowIdx = affectState ? 24 : 27; 1672798Sktlim@umich.edu bitMask = bitMask | mask(31, lowIdx); 1682798Sktlim@umich.edu } 1692798Sktlim@umich.edu if (bits(byteMask, 2)) { 1702798Sktlim@umich.edu bitMask = bitMask | mask(19, 16); 1712798Sktlim@umich.edu } 1722798Sktlim@umich.edu if (bits(byteMask, 1)) { 1732798Sktlim@umich.edu unsigned highIdx = affectState ? 15 : 9; 1743222Sktlim@umich.edu unsigned lowIdx = privileged ? 8 : 9; 1752867Sktlim@umich.edu bitMask = bitMask | mask(highIdx, lowIdx); 1762867Sktlim@umich.edu } 1772867Sktlim@umich.edu if (bits(byteMask, 0)) { 1782867Sktlim@umich.edu if (privileged) { 1792867Sktlim@umich.edu bitMask = bitMask | mask(7, 6); 1802623SN/A if (!badMode((OperatingMode)(val & mask(5)))) { 1812623SN/A bitMask = bitMask | mask(5); 1822623SN/A } else { 1832623SN/A warn_once("Ignoring write of bad mode to CPSR.\n"); 1842623SN/A } 1852623SN/A } 1862623SN/A if (affectState) 1872623SN/A bitMask = bitMask | (1 << 5); 1882680Sktlim@umich.edu } 1892623SN/A 1902680Sktlim@umich.edu bool cpsr_f = cpsr.f; 1912680Sktlim@umich.edu uint32_t new_cpsr = ((uint32_t)cpsr & ~bitMask) | (val & bitMask); 1922680Sktlim@umich.edu if (nmfi && !cpsr_f) 1932623SN/A new_cpsr &= ~(1 << 6); 1942623SN/A return new_cpsr; 1952623SN/A } 1962623SN/A 1973201Shsul@eecs.umich.edu static uint32_t 1983201Shsul@eecs.umich.edu spsrWriteByInstr(uint32_t spsr, uint32_t val, 1993201Shsul@eecs.umich.edu uint8_t byteMask, bool affectState) 2003201Shsul@eecs.umich.edu { 2013227Sktlim@umich.edu uint32_t bitMask = 0; 2023222Sktlim@umich.edu 2033222Sktlim@umich.edu if (bits(byteMask, 3)) 2043227Sktlim@umich.edu bitMask = bitMask | mask(31, 24); 2053222Sktlim@umich.edu if (bits(byteMask, 2)) 2063222Sktlim@umich.edu bitMask = bitMask | mask(19, 16); 2073222Sktlim@umich.edu if (bits(byteMask, 1)) 2083222Sktlim@umich.edu bitMask = bitMask | mask(15, 8); 2093222Sktlim@umich.edu if (bits(byteMask, 0)) 2103222Sktlim@umich.edu bitMask = bitMask | mask(7, 0); 2113222Sktlim@umich.edu 2123227Sktlim@umich.edu return ((spsr & ~bitMask) | (val & bitMask)); 2133222Sktlim@umich.edu } 2143222Sktlim@umich.edu 2153222Sktlim@umich.edu template<class XC> 2163222Sktlim@umich.edu static Addr 2173222Sktlim@umich.edu readPC(XC *xc) 2182623SN/A { 2192623SN/A Addr pc = xc->readPC(); 2202623SN/A Addr tBit = pc & (ULL(1) << PcTBitShift); 2212623SN/A if (tBit) 2222623SN/A return pc + 4; 2232623SN/A else 2242623SN/A return pc + 8; 2252683Sktlim@umich.edu } 2262623SN/A 2272623SN/A // Perform an regular branch. 2282623SN/A template<class XC> 2292623SN/A static void 2302623SN/A setNextPC(XC *xc, Addr val) 2312623SN/A { 2322867Sktlim@umich.edu Addr npc = xc->readNextPC(); 2332867Sktlim@umich.edu if (npc & (ULL(1) << PcTBitShift)) { 2342867Sktlim@umich.edu val &= ~mask(1); 2352623SN/A } else { 2362623SN/A val &= ~mask(2); 2372623SN/A } 2382623SN/A xc->setNextPC((npc & PcModeMask) | 2392623SN/A (val & ~PcModeMask)); 2402623SN/A } 2412623SN/A 2422683Sktlim@umich.edu template<class T> 2432623SN/A static T 2442644Sstever@eecs.umich.edu cSwap(T val, bool big) 2452623SN/A { 2462644Sstever@eecs.umich.edu if (big) { 2472644Sstever@eecs.umich.edu return gtobe(val); 2482623SN/A } else { 2492623SN/A return gtole(val); 2502623SN/A } 2512623SN/A } 2522623SN/A 2532623SN/A // Perform an interworking branch. 2542623SN/A template<class XC> 2552623SN/A static void 2562623SN/A setIWNextPC(XC *xc, Addr val) 2572623SN/A { 2583169Sstever@eecs.umich.edu Addr stateBits = xc->readPC() & PcModeMask; 2593169Sstever@eecs.umich.edu Addr jBit = (ULL(1) << PcJBitShift); 2603170Sstever@eecs.umich.edu Addr tBit = (ULL(1) << PcTBitShift); 2612623SN/A bool thumbEE = (stateBits == (tBit | jBit)); 2622623SN/A 2633169Sstever@eecs.umich.edu Addr newPc = (val & ~PcModeMask); 2642623SN/A if (thumbEE) { 2652623SN/A if (bits(newPc, 0)) { 2662623SN/A newPc = newPc & ~mask(1); 2673169Sstever@eecs.umich.edu } else { 2682623SN/A panic("Bad thumbEE interworking branch address %#x.\n", newPc); 2692623SN/A } 2702623SN/A } else { 2713169Sstever@eecs.umich.edu if (bits(newPc, 0)) { 2723169Sstever@eecs.umich.edu stateBits = tBit; 2733169Sstever@eecs.umich.edu newPc = newPc & ~mask(1); 2742623SN/A } else if (!bits(newPc, 1)) { 2753169Sstever@eecs.umich.edu stateBits = 0; 2762623SN/A } else { 2773169Sstever@eecs.umich.edu warn("Bad interworking branch address %#x.\n", newPc); 2782623SN/A } 2792623SN/A } 2803169Sstever@eecs.umich.edu newPc = newPc | stateBits; 2812623SN/A xc->setNextPC(newPc); 2822623SN/A } 2832623SN/A 2842623SN/A // Perform an interworking branch in ARM mode, a regular branch 2852623SN/A // otherwise. 2863172Sstever@eecs.umich.edu template<class XC> 2872623SN/A static void 2882623SN/A setAIWNextPC(XC *xc, Addr val) 2892623SN/A { 2902623SN/A Addr stateBits = xc->readPC() & PcModeMask; 2912623SN/A Addr jBit = (ULL(1) << PcJBitShift); 2922623SN/A Addr tBit = (ULL(1) << PcTBitShift); 2932623SN/A if (!jBit && !tBit) { 2942623SN/A setIWNextPC(xc, val); 2952623SN/A } else { 2962623SN/A setNextPC(xc, val); 2972623SN/A } 2982623SN/A } 2992623SN/A}; 3002623SN/A} 3012623SN/A 3022623SN/A#endif //__ARCH_ARM_INSTS_STATICINST_HH__ 3032623SN/A