static_inst.hh revision 7219:0c995c5f8245 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_STATICINST_HH__
43#define __ARCH_ARM_INSTS_STATICINST_HH__
44
45#include "base/trace.hh"
46#include "cpu/static_inst.hh"
47
48namespace ArmISA
49{
50class ArmStaticInst : public StaticInst
51{
52  protected:
53    int32_t shift_rm_imm(uint32_t base, uint32_t shamt,
54                         uint32_t type, uint32_t cfval) const;
55    int32_t shift_rm_rs(uint32_t base, uint32_t shamt,
56                        uint32_t type, uint32_t cfval) const;
57
58    bool shift_carry_imm(uint32_t base, uint32_t shamt,
59                         uint32_t type, uint32_t cfval) const;
60    bool shift_carry_rs(uint32_t base, uint32_t shamt,
61                        uint32_t type, uint32_t cfval) const;
62
63    template<int width>
64    static bool
65    saturateOp(int32_t &res, int64_t op1, int64_t op2, bool sub=false)
66    {
67        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
68        if (bits(midRes, width) != bits(midRes, width - 1)) {
69            if (midRes > 0)
70                res = (1LL << (width - 1)) - 1;
71            else
72                res = -(1LL << (width - 1));
73            return true;
74        } else {
75            res = midRes;
76            return false;
77        }
78    }
79
80    template<int width>
81    static bool
82    uSaturateOp(uint32_t &res, int64_t op1, int64_t op2, bool sub=false)
83    {
84        int64_t midRes = sub ? (op1 - op2) : (op1 + op2);
85        if (midRes >= (1 << width)) {
86            res = (1 << width) - 1;
87            return true;
88        } else if (midRes < 0) {
89            res = 0;
90            return true;
91        } else {
92            res = midRes;
93            return false;
94        }
95    }
96
97    // Constructor
98    ArmStaticInst(const char *mnem, ExtMachInst _machInst,
99                  OpClass __opClass)
100        : StaticInst(mnem, _machInst, __opClass)
101    {
102    }
103
104    /// Print a register name for disassembly given the unique
105    /// dependence tag number (FP or int).
106    void printReg(std::ostream &os, int reg) const;
107    void printMnemonic(std::ostream &os,
108                       const std::string &suffix = "",
109                       bool withPred = true) const;
110    void printMemSymbol(std::ostream &os, const SymbolTable *symtab,
111                        const std::string &prefix, const Addr addr,
112                        const std::string &suffix) const;
113    void printShiftOperand(std::ostream &os, IntRegIndex rm,
114                           bool immShift, uint32_t shiftAmt,
115                           IntRegIndex rs, ArmShiftType type) const;
116
117
118    void printDataInst(std::ostream &os, bool withImm) const;
119    void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
120                       IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
121                       IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
122                       uint32_t imm) const;
123
124    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125
126    static uint32_t
127    cpsrWriteByInstr(CPSR cpsr, uint32_t val,
128            uint8_t byteMask, bool affectState)
129    {
130        bool privileged = (cpsr.mode != MODE_USER);
131
132        uint32_t bitMask = 0;
133
134        if (bits(byteMask, 3)) {
135            unsigned lowIdx = affectState ? 24 : 27;
136            bitMask = bitMask | mask(31, lowIdx);
137        }
138        if (bits(byteMask, 2)) {
139            bitMask = bitMask | mask(19, 16);
140        }
141        if (bits(byteMask, 1)) {
142            unsigned highIdx = affectState ? 15 : 9;
143            unsigned lowIdx = privileged ? 8 : 9;
144            bitMask = bitMask | mask(highIdx, lowIdx);
145        }
146        if (bits(byteMask, 0)) {
147            if (privileged) {
148                bitMask = bitMask | mask(7, 6);
149                bitMask = bitMask | mask(5);
150            }
151            if (affectState)
152                bitMask = bitMask | (1 << 5);
153        }
154
155        return ((uint32_t)cpsr & ~bitMask) | (val & bitMask);
156    }
157
158    static uint32_t
159    spsrWriteByInstr(uint32_t spsr, uint32_t val,
160            uint8_t byteMask, bool affectState)
161    {
162        uint32_t bitMask = 0;
163
164        if (bits(byteMask, 3))
165            bitMask = bitMask | mask(31, 24);
166        if (bits(byteMask, 2))
167            bitMask = bitMask | mask(19, 16);
168        if (bits(byteMask, 1))
169            bitMask = bitMask | mask(15, 8);
170        if (bits(byteMask, 0))
171            bitMask = bitMask | mask(7, 0);
172
173        return ((spsr & ~bitMask) | (val & bitMask));
174    }
175
176    template<class XC>
177    static Addr
178    readPC(XC *xc)
179    {
180        Addr pc = xc->readPC();
181        Addr tBit = pc & (ULL(1) << PcTBitShift);
182        if (tBit)
183            return pc + 4;
184        else
185            return pc + 8;
186    }
187
188    // Perform an regular branch.
189    template<class XC>
190    static void
191    setNextPC(XC *xc, Addr val)
192    {
193        xc->setNextPC((xc->readNextPC() & PcModeMask) |
194                      (val & ~PcModeMask));
195    }
196
197    // Perform an interworking branch.
198    template<class XC>
199    static void
200    setIWNextPC(XC *xc, Addr val)
201    {
202        Addr stateBits = xc->readPC() & PcModeMask;
203        Addr jBit = (ULL(1) << PcJBitShift);
204        Addr tBit = (ULL(1) << PcTBitShift);
205        bool thumbEE = (stateBits == (tBit | jBit));
206
207        Addr newPc = (val & ~PcModeMask);
208        if (thumbEE) {
209            if (bits(newPc, 0)) {
210                warn("Bad thumbEE interworking branch address %#x.\n", newPc);
211            } else {
212                newPc = newPc & ~mask(1);
213            }
214        } else {
215            if (bits(newPc, 0)) {
216                stateBits = tBit;
217                newPc = newPc & ~mask(1);
218            } else if (!bits(newPc, 1)) {
219                stateBits = 0;
220            } else {
221                warn("Bad interworking branch address %#x.\n", newPc);
222            }
223        }
224        newPc = newPc | stateBits;
225        xc->setNextPC(newPc);
226    }
227
228    // Perform an interworking branch in ARM mode, a regular branch
229    // otherwise.
230    template<class XC>
231    static void
232    setAIWNextPC(XC *xc, Addr val)
233    {
234        Addr stateBits = xc->readPC() & PcModeMask;
235        Addr jBit = (ULL(1) << PcJBitShift);
236        Addr tBit = (ULL(1) << PcTBitShift);
237        if (!jBit && !tBit) {
238            setIWNextPC(xc, val);
239        } else {
240            setNextPC(xc, val);
241        }
242    }
243};
244}
245
246#endif //__ARCH_ARM_INSTS_STATICINST_HH__
247