static_inst.cc revision 9913
17094Sgblack@eecs.umich.edu/* 27094Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47094Sgblack@eecs.umich.edu * All rights reserved 57094Sgblack@eecs.umich.edu * 67094Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 77094Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 87094Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 97094Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 107094Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 117094Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 127094Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 137094Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 147094Sgblack@eecs.umich.edu * 157094Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 166253Sgblack@eecs.umich.edu * All rights reserved. 176253Sgblack@eecs.umich.edu * 186253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 196253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 206253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 216253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 226253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 236253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 246253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 256253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 266253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 276253Sgblack@eecs.umich.edu * this software without specific prior written permission. 286253Sgblack@eecs.umich.edu * 296253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406253Sgblack@eecs.umich.edu * 416253Sgblack@eecs.umich.edu * Authors: Stephen Hines 426253Sgblack@eecs.umich.edu */ 436253Sgblack@eecs.umich.edu 448229Snate@binkert.org#include "arch/arm/insts/static_inst.hh" 456759SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 468229Snate@binkert.org#include "base/loader/symtab.hh" 476255Sgblack@eecs.umich.edu#include "base/condcodes.hh" 486712Snate@binkert.org#include "base/cprintf.hh" 499913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 506253Sgblack@eecs.umich.edu 516253Sgblack@eecs.umich.edunamespace ArmISA 526253Sgblack@eecs.umich.edu{ 536254Sgblack@eecs.umich.edu// Shift Rm by an immediate value 546254Sgblack@eecs.umich.eduint32_t 557148Sgblack@eecs.umich.eduArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt, 567094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 576254Sgblack@eecs.umich.edu{ 586255Sgblack@eecs.umich.edu assert(shamt < 32); 596255Sgblack@eecs.umich.edu ArmShiftType shiftType; 606255Sgblack@eecs.umich.edu shiftType = (ArmShiftType)type; 616254Sgblack@eecs.umich.edu 626254Sgblack@eecs.umich.edu switch (shiftType) 636254Sgblack@eecs.umich.edu { 646255Sgblack@eecs.umich.edu case LSL: 656255Sgblack@eecs.umich.edu return base << shamt; 666255Sgblack@eecs.umich.edu case LSR: 676255Sgblack@eecs.umich.edu if (shamt == 0) 686255Sgblack@eecs.umich.edu return 0; 696255Sgblack@eecs.umich.edu else 706255Sgblack@eecs.umich.edu return base >> shamt; 716255Sgblack@eecs.umich.edu case ASR: 726255Sgblack@eecs.umich.edu if (shamt == 0) 737182Sgblack@eecs.umich.edu return (base >> 31) | -((base & (1 << 31)) >> 31); 746255Sgblack@eecs.umich.edu else 757182Sgblack@eecs.umich.edu return (base >> shamt) | -((base & (1 << 31)) >> shamt); 766255Sgblack@eecs.umich.edu case ROR: 776255Sgblack@eecs.umich.edu if (shamt == 0) 786255Sgblack@eecs.umich.edu return (cfval << 31) | (base >> 1); // RRX 796255Sgblack@eecs.umich.edu else 806255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 816255Sgblack@eecs.umich.edu default: 826712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 836255Sgblack@eecs.umich.edu exit(1); 846255Sgblack@eecs.umich.edu break; 856254Sgblack@eecs.umich.edu } 866254Sgblack@eecs.umich.edu return 0; 876254Sgblack@eecs.umich.edu} 886254Sgblack@eecs.umich.edu 896254Sgblack@eecs.umich.edu// Shift Rm by Rs 906254Sgblack@eecs.umich.eduint32_t 917148Sgblack@eecs.umich.eduArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt, 927094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 936254Sgblack@eecs.umich.edu{ 946254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 956254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 966254Sgblack@eecs.umich.edu 976254Sgblack@eecs.umich.edu switch (shiftType) 986254Sgblack@eecs.umich.edu { 996255Sgblack@eecs.umich.edu case LSL: 1006255Sgblack@eecs.umich.edu if (shamt >= 32) 1016255Sgblack@eecs.umich.edu return 0; 1026255Sgblack@eecs.umich.edu else 1036255Sgblack@eecs.umich.edu return base << shamt; 1046255Sgblack@eecs.umich.edu case LSR: 1056255Sgblack@eecs.umich.edu if (shamt >= 32) 1066255Sgblack@eecs.umich.edu return 0; 1076255Sgblack@eecs.umich.edu else 1086255Sgblack@eecs.umich.edu return base >> shamt; 1096255Sgblack@eecs.umich.edu case ASR: 1106255Sgblack@eecs.umich.edu if (shamt >= 32) 1117182Sgblack@eecs.umich.edu return (base >> 31) | -((base & (1 << 31)) >> 31); 1126255Sgblack@eecs.umich.edu else 1137182Sgblack@eecs.umich.edu return (base >> shamt) | -((base & (1 << 31)) >> shamt); 1146255Sgblack@eecs.umich.edu case ROR: 1156255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1166255Sgblack@eecs.umich.edu if (shamt == 0) 1176255Sgblack@eecs.umich.edu return base; 1186255Sgblack@eecs.umich.edu else 1196255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 1206255Sgblack@eecs.umich.edu default: 1216712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 1226255Sgblack@eecs.umich.edu exit(1); 1236255Sgblack@eecs.umich.edu break; 1246254Sgblack@eecs.umich.edu } 1256254Sgblack@eecs.umich.edu return 0; 1266254Sgblack@eecs.umich.edu} 1276254Sgblack@eecs.umich.edu 1286254Sgblack@eecs.umich.edu 1296254Sgblack@eecs.umich.edu// Generate C for a shift by immediate 1306255Sgblack@eecs.umich.edubool 1317148Sgblack@eecs.umich.eduArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt, 1327094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1336254Sgblack@eecs.umich.edu{ 1346254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1356254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1366254Sgblack@eecs.umich.edu 1376254Sgblack@eecs.umich.edu switch (shiftType) 1386254Sgblack@eecs.umich.edu { 1396255Sgblack@eecs.umich.edu case LSL: 1406255Sgblack@eecs.umich.edu if (shamt == 0) 1416255Sgblack@eecs.umich.edu return cfval; 1426255Sgblack@eecs.umich.edu else 1436254Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1446255Sgblack@eecs.umich.edu case LSR: 1456255Sgblack@eecs.umich.edu if (shamt == 0) 1466255Sgblack@eecs.umich.edu return (base >> 31); 1476255Sgblack@eecs.umich.edu else 1486255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1496255Sgblack@eecs.umich.edu case ASR: 1506255Sgblack@eecs.umich.edu if (shamt == 0) 1516255Sgblack@eecs.umich.edu return (base >> 31); 1526255Sgblack@eecs.umich.edu else 1536255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1546255Sgblack@eecs.umich.edu case ROR: 1556255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1566255Sgblack@eecs.umich.edu if (shamt == 0) 1576255Sgblack@eecs.umich.edu return (base & 1); // RRX 1586255Sgblack@eecs.umich.edu else 1596255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1606255Sgblack@eecs.umich.edu default: 1616712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 1626255Sgblack@eecs.umich.edu exit(1); 1636255Sgblack@eecs.umich.edu break; 1646254Sgblack@eecs.umich.edu } 1656254Sgblack@eecs.umich.edu return 0; 1666254Sgblack@eecs.umich.edu} 1676254Sgblack@eecs.umich.edu 1686254Sgblack@eecs.umich.edu 1696254Sgblack@eecs.umich.edu// Generate C for a shift by Rs 1706255Sgblack@eecs.umich.edubool 1717148Sgblack@eecs.umich.eduArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, 1727094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1736254Sgblack@eecs.umich.edu{ 1746254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1756254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1766254Sgblack@eecs.umich.edu 1776255Sgblack@eecs.umich.edu if (shamt == 0) 1786255Sgblack@eecs.umich.edu return cfval; 1796255Sgblack@eecs.umich.edu 1806254Sgblack@eecs.umich.edu switch (shiftType) 1816254Sgblack@eecs.umich.edu { 1826255Sgblack@eecs.umich.edu case LSL: 1836255Sgblack@eecs.umich.edu if (shamt > 32) 1846255Sgblack@eecs.umich.edu return 0; 1856255Sgblack@eecs.umich.edu else 1866255Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1876255Sgblack@eecs.umich.edu case LSR: 1886255Sgblack@eecs.umich.edu if (shamt > 32) 1896255Sgblack@eecs.umich.edu return 0; 1906255Sgblack@eecs.umich.edu else 1916255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1926255Sgblack@eecs.umich.edu case ASR: 1936255Sgblack@eecs.umich.edu if (shamt > 32) 1946255Sgblack@eecs.umich.edu shamt = 32; 1956255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1966255Sgblack@eecs.umich.edu case ROR: 1976255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1986255Sgblack@eecs.umich.edu if (shamt == 0) 1996255Sgblack@eecs.umich.edu shamt = 32; 2006255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2016255Sgblack@eecs.umich.edu default: 2026712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 2036255Sgblack@eecs.umich.edu exit(1); 2046255Sgblack@eecs.umich.edu break; 2056254Sgblack@eecs.umich.edu } 2066254Sgblack@eecs.umich.edu return 0; 2076254Sgblack@eecs.umich.edu} 2086254Sgblack@eecs.umich.edu 2096254Sgblack@eecs.umich.edu 2106254Sgblack@eecs.umich.eduvoid 2117148Sgblack@eecs.umich.eduArmStaticInst::printReg(std::ostream &os, int reg) const 2126253Sgblack@eecs.umich.edu{ 2139913Ssteve.reinhardt@amd.com RegIndex rel_reg; 2149913Ssteve.reinhardt@amd.com 2159913Ssteve.reinhardt@amd.com switch (regIdxToClass(reg, &rel_reg)) { 2169913Ssteve.reinhardt@amd.com case IntRegClass: 2179913Ssteve.reinhardt@amd.com switch (rel_reg) { 2186261Sgblack@eecs.umich.edu case PCReg: 2196261Sgblack@eecs.umich.edu ccprintf(os, "pc"); 2206261Sgblack@eecs.umich.edu break; 2216261Sgblack@eecs.umich.edu case StackPointerReg: 2226261Sgblack@eecs.umich.edu ccprintf(os, "sp"); 2236261Sgblack@eecs.umich.edu break; 2246261Sgblack@eecs.umich.edu case FramePointerReg: 2256261Sgblack@eecs.umich.edu ccprintf(os, "fp"); 2266261Sgblack@eecs.umich.edu break; 2276261Sgblack@eecs.umich.edu case ReturnAddressReg: 2286261Sgblack@eecs.umich.edu ccprintf(os, "lr"); 2296261Sgblack@eecs.umich.edu break; 2306261Sgblack@eecs.umich.edu default: 2316261Sgblack@eecs.umich.edu ccprintf(os, "r%d", reg); 2326261Sgblack@eecs.umich.edu break; 2336261Sgblack@eecs.umich.edu } 2349913Ssteve.reinhardt@amd.com break; 2359913Ssteve.reinhardt@amd.com case FloatRegClass: 2369913Ssteve.reinhardt@amd.com ccprintf(os, "f%d", rel_reg); 2379913Ssteve.reinhardt@amd.com break; 2389913Ssteve.reinhardt@amd.com case MiscRegClass: 2399913Ssteve.reinhardt@amd.com assert(rel_reg < NUM_MISCREGS); 2409913Ssteve.reinhardt@amd.com ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]); 2419913Ssteve.reinhardt@amd.com break; 2426253Sgblack@eecs.umich.edu } 2436253Sgblack@eecs.umich.edu} 2446253Sgblack@eecs.umich.edu 2456262Sgblack@eecs.umich.eduvoid 2467148Sgblack@eecs.umich.eduArmStaticInst::printMnemonic(std::ostream &os, 2476262Sgblack@eecs.umich.edu const std::string &suffix, 2486262Sgblack@eecs.umich.edu bool withPred) const 2496262Sgblack@eecs.umich.edu{ 2506262Sgblack@eecs.umich.edu os << " " << mnemonic; 2516262Sgblack@eecs.umich.edu if (withPred) { 2526262Sgblack@eecs.umich.edu unsigned condCode = machInst.condCode; 2536262Sgblack@eecs.umich.edu switch (condCode) { 2546262Sgblack@eecs.umich.edu case COND_EQ: 2556262Sgblack@eecs.umich.edu os << "eq"; 2566262Sgblack@eecs.umich.edu break; 2576262Sgblack@eecs.umich.edu case COND_NE: 2586262Sgblack@eecs.umich.edu os << "ne"; 2596262Sgblack@eecs.umich.edu break; 2606262Sgblack@eecs.umich.edu case COND_CS: 2616262Sgblack@eecs.umich.edu os << "cs"; 2626262Sgblack@eecs.umich.edu break; 2636262Sgblack@eecs.umich.edu case COND_CC: 2646262Sgblack@eecs.umich.edu os << "cc"; 2656262Sgblack@eecs.umich.edu break; 2666262Sgblack@eecs.umich.edu case COND_MI: 2676262Sgblack@eecs.umich.edu os << "mi"; 2686262Sgblack@eecs.umich.edu break; 2696262Sgblack@eecs.umich.edu case COND_PL: 2706262Sgblack@eecs.umich.edu os << "pl"; 2716262Sgblack@eecs.umich.edu break; 2726262Sgblack@eecs.umich.edu case COND_VS: 2736262Sgblack@eecs.umich.edu os << "vs"; 2746262Sgblack@eecs.umich.edu break; 2756262Sgblack@eecs.umich.edu case COND_VC: 2766262Sgblack@eecs.umich.edu os << "vc"; 2776262Sgblack@eecs.umich.edu break; 2786262Sgblack@eecs.umich.edu case COND_HI: 2796262Sgblack@eecs.umich.edu os << "hi"; 2806262Sgblack@eecs.umich.edu break; 2816262Sgblack@eecs.umich.edu case COND_LS: 2826262Sgblack@eecs.umich.edu os << "ls"; 2836262Sgblack@eecs.umich.edu break; 2846262Sgblack@eecs.umich.edu case COND_GE: 2856262Sgblack@eecs.umich.edu os << "ge"; 2866262Sgblack@eecs.umich.edu break; 2876262Sgblack@eecs.umich.edu case COND_LT: 2886262Sgblack@eecs.umich.edu os << "lt"; 2896262Sgblack@eecs.umich.edu break; 2906262Sgblack@eecs.umich.edu case COND_GT: 2916262Sgblack@eecs.umich.edu os << "gt"; 2926262Sgblack@eecs.umich.edu break; 2936262Sgblack@eecs.umich.edu case COND_LE: 2946262Sgblack@eecs.umich.edu os << "le"; 2956262Sgblack@eecs.umich.edu break; 2966262Sgblack@eecs.umich.edu case COND_AL: 2976262Sgblack@eecs.umich.edu // This one is implicit. 2986262Sgblack@eecs.umich.edu break; 2997111Sgblack@eecs.umich.edu case COND_UC: 3007111Sgblack@eecs.umich.edu // Unconditional. 3016262Sgblack@eecs.umich.edu break; 3026262Sgblack@eecs.umich.edu default: 3036262Sgblack@eecs.umich.edu panic("Unrecognized condition code %d.\n", condCode); 3046262Sgblack@eecs.umich.edu } 3057122Sgblack@eecs.umich.edu os << suffix; 3067122Sgblack@eecs.umich.edu if (machInst.bigThumb) 3077122Sgblack@eecs.umich.edu os << ".w"; 3087122Sgblack@eecs.umich.edu os << " "; 3096262Sgblack@eecs.umich.edu } 3106262Sgblack@eecs.umich.edu} 3116262Sgblack@eecs.umich.edu 3126263Sgblack@eecs.umich.eduvoid 3137148Sgblack@eecs.umich.eduArmStaticInst::printMemSymbol(std::ostream &os, 3146263Sgblack@eecs.umich.edu const SymbolTable *symtab, 3156263Sgblack@eecs.umich.edu const std::string &prefix, 3166263Sgblack@eecs.umich.edu const Addr addr, 3176263Sgblack@eecs.umich.edu const std::string &suffix) const 3186263Sgblack@eecs.umich.edu{ 3196263Sgblack@eecs.umich.edu Addr symbolAddr; 3206263Sgblack@eecs.umich.edu std::string symbol; 3216263Sgblack@eecs.umich.edu if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) { 3226263Sgblack@eecs.umich.edu ccprintf(os, "%s%s", prefix, symbol); 3236263Sgblack@eecs.umich.edu if (symbolAddr != addr) 3246263Sgblack@eecs.umich.edu ccprintf(os, "+%d", addr - symbolAddr); 3256263Sgblack@eecs.umich.edu ccprintf(os, suffix); 3266263Sgblack@eecs.umich.edu } 3276263Sgblack@eecs.umich.edu} 3286263Sgblack@eecs.umich.edu 3296264Sgblack@eecs.umich.eduvoid 3307148Sgblack@eecs.umich.eduArmStaticInst::printShiftOperand(std::ostream &os, 3317142Sgblack@eecs.umich.edu IntRegIndex rm, 3327142Sgblack@eecs.umich.edu bool immShift, 3337142Sgblack@eecs.umich.edu uint32_t shiftAmt, 3347142Sgblack@eecs.umich.edu IntRegIndex rs, 3357142Sgblack@eecs.umich.edu ArmShiftType type) const 3366264Sgblack@eecs.umich.edu{ 3377142Sgblack@eecs.umich.edu bool firstOp = false; 3386264Sgblack@eecs.umich.edu 3397142Sgblack@eecs.umich.edu if (rm != INTREG_ZERO) { 3407142Sgblack@eecs.umich.edu printReg(os, rm); 3417142Sgblack@eecs.umich.edu } 3427142Sgblack@eecs.umich.edu 3436306Sgblack@eecs.umich.edu bool done = false; 3446264Sgblack@eecs.umich.edu 3456306Sgblack@eecs.umich.edu if ((type == LSR || type == ASR) && immShift && shiftAmt == 0) 3466306Sgblack@eecs.umich.edu shiftAmt = 32; 3476264Sgblack@eecs.umich.edu 3486306Sgblack@eecs.umich.edu switch (type) { 3496306Sgblack@eecs.umich.edu case LSL: 3506306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 3516306Sgblack@eecs.umich.edu done = true; 3526264Sgblack@eecs.umich.edu break; 3536306Sgblack@eecs.umich.edu } 3547142Sgblack@eecs.umich.edu if (!firstOp) 3557142Sgblack@eecs.umich.edu os << ", "; 3567142Sgblack@eecs.umich.edu os << "LSL"; 3576306Sgblack@eecs.umich.edu break; 3586306Sgblack@eecs.umich.edu case LSR: 3597142Sgblack@eecs.umich.edu if (!firstOp) 3607142Sgblack@eecs.umich.edu os << ", "; 3617142Sgblack@eecs.umich.edu os << "LSR"; 3626306Sgblack@eecs.umich.edu break; 3636306Sgblack@eecs.umich.edu case ASR: 3647142Sgblack@eecs.umich.edu if (!firstOp) 3657142Sgblack@eecs.umich.edu os << ", "; 3667142Sgblack@eecs.umich.edu os << "ASR"; 3676306Sgblack@eecs.umich.edu break; 3686306Sgblack@eecs.umich.edu case ROR: 3696306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 3707142Sgblack@eecs.umich.edu if (!firstOp) 3717142Sgblack@eecs.umich.edu os << ", "; 3727142Sgblack@eecs.umich.edu os << "RRX"; 3736306Sgblack@eecs.umich.edu done = true; 3746264Sgblack@eecs.umich.edu break; 3756264Sgblack@eecs.umich.edu } 3767142Sgblack@eecs.umich.edu if (!firstOp) 3777142Sgblack@eecs.umich.edu os << ", "; 3787142Sgblack@eecs.umich.edu os << "ROR"; 3796306Sgblack@eecs.umich.edu break; 3806306Sgblack@eecs.umich.edu default: 3816306Sgblack@eecs.umich.edu panic("Tried to disassemble unrecognized shift type.\n"); 3826306Sgblack@eecs.umich.edu } 3836306Sgblack@eecs.umich.edu if (!done) { 3847142Sgblack@eecs.umich.edu if (!firstOp) 3857142Sgblack@eecs.umich.edu os << " "; 3866306Sgblack@eecs.umich.edu if (immShift) 3876306Sgblack@eecs.umich.edu os << "#" << shiftAmt; 3886306Sgblack@eecs.umich.edu else 3897142Sgblack@eecs.umich.edu printReg(os, rs); 3906264Sgblack@eecs.umich.edu } 3916264Sgblack@eecs.umich.edu} 3926264Sgblack@eecs.umich.edu 3936264Sgblack@eecs.umich.eduvoid 3947148Sgblack@eecs.umich.eduArmStaticInst::printDataInst(std::ostream &os, bool withImm, 3957142Sgblack@eecs.umich.edu bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, 3967142Sgblack@eecs.umich.edu IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, 3977142Sgblack@eecs.umich.edu ArmShiftType type, uint32_t imm) const 3986264Sgblack@eecs.umich.edu{ 3997142Sgblack@eecs.umich.edu printMnemonic(os, s ? "s" : ""); 4006264Sgblack@eecs.umich.edu bool firstOp = true; 4016264Sgblack@eecs.umich.edu 4026264Sgblack@eecs.umich.edu // Destination 4037142Sgblack@eecs.umich.edu if (rd != INTREG_ZERO) { 4046264Sgblack@eecs.umich.edu firstOp = false; 4057142Sgblack@eecs.umich.edu printReg(os, rd); 4066264Sgblack@eecs.umich.edu } 4076264Sgblack@eecs.umich.edu 4086264Sgblack@eecs.umich.edu // Source 1. 4097142Sgblack@eecs.umich.edu if (rn != INTREG_ZERO) { 4106264Sgblack@eecs.umich.edu if (!firstOp) 4116264Sgblack@eecs.umich.edu os << ", "; 4126264Sgblack@eecs.umich.edu firstOp = false; 4137142Sgblack@eecs.umich.edu printReg(os, rn); 4146264Sgblack@eecs.umich.edu } 4156264Sgblack@eecs.umich.edu 4166264Sgblack@eecs.umich.edu if (!firstOp) 4176264Sgblack@eecs.umich.edu os << ", "; 4186306Sgblack@eecs.umich.edu if (withImm) { 4197142Sgblack@eecs.umich.edu ccprintf(os, "#%d", imm); 4206306Sgblack@eecs.umich.edu } else { 4217142Sgblack@eecs.umich.edu printShiftOperand(os, rm, immShift, shiftAmt, rs, type); 4226306Sgblack@eecs.umich.edu } 4236264Sgblack@eecs.umich.edu} 4246264Sgblack@eecs.umich.edu 4256254Sgblack@eecs.umich.edustd::string 4267148Sgblack@eecs.umich.eduArmStaticInst::generateDisassembly(Addr pc, 4276254Sgblack@eecs.umich.edu const SymbolTable *symtab) const 4286253Sgblack@eecs.umich.edu{ 4296253Sgblack@eecs.umich.edu std::stringstream ss; 4306262Sgblack@eecs.umich.edu printMnemonic(ss); 4316253Sgblack@eecs.umich.edu return ss.str(); 4326253Sgblack@eecs.umich.edu} 4336253Sgblack@eecs.umich.edu} 434