static_inst.cc revision 7142
17094Sgblack@eecs.umich.edu/* 27094Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37094Sgblack@eecs.umich.edu * All rights reserved 47094Sgblack@eecs.umich.edu * 57094Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67094Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77094Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87094Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97094Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107094Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117094Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127094Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137094Sgblack@eecs.umich.edu * 147094Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu 436759SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 446253Sgblack@eecs.umich.edu#include "arch/arm/insts/static_inst.hh" 456255Sgblack@eecs.umich.edu#include "base/condcodes.hh" 466712Snate@binkert.org#include "base/cprintf.hh" 476263Sgblack@eecs.umich.edu#include "base/loader/symtab.hh" 486253Sgblack@eecs.umich.edu 496253Sgblack@eecs.umich.edunamespace ArmISA 506253Sgblack@eecs.umich.edu{ 516254Sgblack@eecs.umich.edu// Shift Rm by an immediate value 526254Sgblack@eecs.umich.eduint32_t 537094Sgblack@eecs.umich.eduArmStaticInstBase::shift_rm_imm(uint32_t base, uint32_t shamt, 547094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 556254Sgblack@eecs.umich.edu{ 566255Sgblack@eecs.umich.edu assert(shamt < 32); 576255Sgblack@eecs.umich.edu ArmShiftType shiftType; 586255Sgblack@eecs.umich.edu shiftType = (ArmShiftType)type; 596254Sgblack@eecs.umich.edu 606254Sgblack@eecs.umich.edu switch (shiftType) 616254Sgblack@eecs.umich.edu { 626255Sgblack@eecs.umich.edu case LSL: 636255Sgblack@eecs.umich.edu return base << shamt; 646255Sgblack@eecs.umich.edu case LSR: 656255Sgblack@eecs.umich.edu if (shamt == 0) 666255Sgblack@eecs.umich.edu return 0; 676255Sgblack@eecs.umich.edu else 686255Sgblack@eecs.umich.edu return base >> shamt; 696255Sgblack@eecs.umich.edu case ASR: 706255Sgblack@eecs.umich.edu if (shamt == 0) 716255Sgblack@eecs.umich.edu return (int32_t)base >> 31; 726255Sgblack@eecs.umich.edu else 736255Sgblack@eecs.umich.edu return (int32_t)base >> shamt; 746255Sgblack@eecs.umich.edu case ROR: 756255Sgblack@eecs.umich.edu if (shamt == 0) 766255Sgblack@eecs.umich.edu return (cfval << 31) | (base >> 1); // RRX 776255Sgblack@eecs.umich.edu else 786255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 796255Sgblack@eecs.umich.edu default: 806712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 816255Sgblack@eecs.umich.edu exit(1); 826255Sgblack@eecs.umich.edu break; 836254Sgblack@eecs.umich.edu } 846254Sgblack@eecs.umich.edu return 0; 856254Sgblack@eecs.umich.edu} 866254Sgblack@eecs.umich.edu 876254Sgblack@eecs.umich.edu// Shift Rm by Rs 886254Sgblack@eecs.umich.eduint32_t 897094Sgblack@eecs.umich.eduArmStaticInstBase::shift_rm_rs(uint32_t base, uint32_t shamt, 907094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 916254Sgblack@eecs.umich.edu{ 926254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 936254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 946254Sgblack@eecs.umich.edu 956254Sgblack@eecs.umich.edu switch (shiftType) 966254Sgblack@eecs.umich.edu { 976255Sgblack@eecs.umich.edu case LSL: 986255Sgblack@eecs.umich.edu if (shamt >= 32) 996255Sgblack@eecs.umich.edu return 0; 1006255Sgblack@eecs.umich.edu else 1016255Sgblack@eecs.umich.edu return base << shamt; 1026255Sgblack@eecs.umich.edu case LSR: 1036255Sgblack@eecs.umich.edu if (shamt >= 32) 1046255Sgblack@eecs.umich.edu return 0; 1056255Sgblack@eecs.umich.edu else 1066255Sgblack@eecs.umich.edu return base >> shamt; 1076255Sgblack@eecs.umich.edu case ASR: 1086255Sgblack@eecs.umich.edu if (shamt >= 32) 1096255Sgblack@eecs.umich.edu return (int32_t)base >> 31; 1106255Sgblack@eecs.umich.edu else 1116255Sgblack@eecs.umich.edu return (int32_t)base >> shamt; 1126255Sgblack@eecs.umich.edu case ROR: 1136255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1146255Sgblack@eecs.umich.edu if (shamt == 0) 1156255Sgblack@eecs.umich.edu return base; 1166255Sgblack@eecs.umich.edu else 1176255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 1186255Sgblack@eecs.umich.edu default: 1196712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 1206255Sgblack@eecs.umich.edu exit(1); 1216255Sgblack@eecs.umich.edu break; 1226254Sgblack@eecs.umich.edu } 1236254Sgblack@eecs.umich.edu return 0; 1246254Sgblack@eecs.umich.edu} 1256254Sgblack@eecs.umich.edu 1266254Sgblack@eecs.umich.edu 1276254Sgblack@eecs.umich.edu// Generate C for a shift by immediate 1286255Sgblack@eecs.umich.edubool 1297094Sgblack@eecs.umich.eduArmStaticInstBase::shift_carry_imm(uint32_t base, uint32_t shamt, 1307094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1316254Sgblack@eecs.umich.edu{ 1326254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1336254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1346254Sgblack@eecs.umich.edu 1356254Sgblack@eecs.umich.edu switch (shiftType) 1366254Sgblack@eecs.umich.edu { 1376255Sgblack@eecs.umich.edu case LSL: 1386255Sgblack@eecs.umich.edu if (shamt == 0) 1396255Sgblack@eecs.umich.edu return cfval; 1406255Sgblack@eecs.umich.edu else 1416254Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1426255Sgblack@eecs.umich.edu case LSR: 1436255Sgblack@eecs.umich.edu if (shamt == 0) 1446255Sgblack@eecs.umich.edu return (base >> 31); 1456255Sgblack@eecs.umich.edu else 1466255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1476255Sgblack@eecs.umich.edu case ASR: 1486255Sgblack@eecs.umich.edu if (shamt == 0) 1496255Sgblack@eecs.umich.edu return (base >> 31); 1506255Sgblack@eecs.umich.edu else 1516255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1526255Sgblack@eecs.umich.edu case ROR: 1536255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1546255Sgblack@eecs.umich.edu if (shamt == 0) 1556255Sgblack@eecs.umich.edu return (base & 1); // RRX 1566255Sgblack@eecs.umich.edu else 1576255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1586255Sgblack@eecs.umich.edu default: 1596712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 1606255Sgblack@eecs.umich.edu exit(1); 1616255Sgblack@eecs.umich.edu break; 1626254Sgblack@eecs.umich.edu } 1636254Sgblack@eecs.umich.edu return 0; 1646254Sgblack@eecs.umich.edu} 1656254Sgblack@eecs.umich.edu 1666254Sgblack@eecs.umich.edu 1676254Sgblack@eecs.umich.edu// Generate C for a shift by Rs 1686255Sgblack@eecs.umich.edubool 1697094Sgblack@eecs.umich.eduArmStaticInstBase::shift_carry_rs(uint32_t base, uint32_t shamt, 1707094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1716254Sgblack@eecs.umich.edu{ 1726254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1736254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1746254Sgblack@eecs.umich.edu 1756255Sgblack@eecs.umich.edu if (shamt == 0) 1766255Sgblack@eecs.umich.edu return cfval; 1776255Sgblack@eecs.umich.edu 1786254Sgblack@eecs.umich.edu switch (shiftType) 1796254Sgblack@eecs.umich.edu { 1806255Sgblack@eecs.umich.edu case LSL: 1816255Sgblack@eecs.umich.edu if (shamt > 32) 1826255Sgblack@eecs.umich.edu return 0; 1836255Sgblack@eecs.umich.edu else 1846255Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1856255Sgblack@eecs.umich.edu case LSR: 1866255Sgblack@eecs.umich.edu if (shamt > 32) 1876255Sgblack@eecs.umich.edu return 0; 1886255Sgblack@eecs.umich.edu else 1896255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1906255Sgblack@eecs.umich.edu case ASR: 1916255Sgblack@eecs.umich.edu if (shamt > 32) 1926255Sgblack@eecs.umich.edu shamt = 32; 1936255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1946255Sgblack@eecs.umich.edu case ROR: 1956255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1966255Sgblack@eecs.umich.edu if (shamt == 0) 1976255Sgblack@eecs.umich.edu shamt = 32; 1986255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1996255Sgblack@eecs.umich.edu default: 2006712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 2016255Sgblack@eecs.umich.edu exit(1); 2026255Sgblack@eecs.umich.edu break; 2036254Sgblack@eecs.umich.edu } 2046254Sgblack@eecs.umich.edu return 0; 2056254Sgblack@eecs.umich.edu} 2066254Sgblack@eecs.umich.edu 2076254Sgblack@eecs.umich.edu 2086254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for an addition operation 2096255Sgblack@eecs.umich.edubool 2107094Sgblack@eecs.umich.eduArmStaticInstBase::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const 2116254Sgblack@eecs.umich.edu{ 2126255Sgblack@eecs.umich.edu return findCarry(32, result, lhs, rhs); 2136254Sgblack@eecs.umich.edu} 2146254Sgblack@eecs.umich.edu 2156254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for a subtraction operation 2166255Sgblack@eecs.umich.edubool 2177094Sgblack@eecs.umich.eduArmStaticInstBase::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const 2186254Sgblack@eecs.umich.edu{ 2196255Sgblack@eecs.umich.edu return findCarry(32, result, lhs, ~rhs); 2206254Sgblack@eecs.umich.edu} 2216254Sgblack@eecs.umich.edu 2226255Sgblack@eecs.umich.edubool 2237094Sgblack@eecs.umich.eduArmStaticInstBase::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2246254Sgblack@eecs.umich.edu{ 2256255Sgblack@eecs.umich.edu return findOverflow(32, result, lhs, rhs); 2266254Sgblack@eecs.umich.edu} 2276254Sgblack@eecs.umich.edu 2286255Sgblack@eecs.umich.edubool 2297094Sgblack@eecs.umich.eduArmStaticInstBase::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2306254Sgblack@eecs.umich.edu{ 2316255Sgblack@eecs.umich.edu return findOverflow(32, result, lhs, ~rhs); 2326254Sgblack@eecs.umich.edu} 2336254Sgblack@eecs.umich.edu 2346254Sgblack@eecs.umich.eduvoid 2357094Sgblack@eecs.umich.eduArmStaticInstBase::printReg(std::ostream &os, int reg) const 2366253Sgblack@eecs.umich.edu{ 2376253Sgblack@eecs.umich.edu if (reg < FP_Base_DepTag) { 2386261Sgblack@eecs.umich.edu switch (reg) { 2396261Sgblack@eecs.umich.edu case PCReg: 2406261Sgblack@eecs.umich.edu ccprintf(os, "pc"); 2416261Sgblack@eecs.umich.edu break; 2426261Sgblack@eecs.umich.edu case StackPointerReg: 2436261Sgblack@eecs.umich.edu ccprintf(os, "sp"); 2446261Sgblack@eecs.umich.edu break; 2456261Sgblack@eecs.umich.edu case FramePointerReg: 2466261Sgblack@eecs.umich.edu ccprintf(os, "fp"); 2476261Sgblack@eecs.umich.edu break; 2486261Sgblack@eecs.umich.edu case ReturnAddressReg: 2496261Sgblack@eecs.umich.edu ccprintf(os, "lr"); 2506261Sgblack@eecs.umich.edu break; 2516261Sgblack@eecs.umich.edu default: 2526261Sgblack@eecs.umich.edu ccprintf(os, "r%d", reg); 2536261Sgblack@eecs.umich.edu break; 2546261Sgblack@eecs.umich.edu } 2556261Sgblack@eecs.umich.edu } else if (reg < Ctrl_Base_DepTag) { 2566253Sgblack@eecs.umich.edu ccprintf(os, "f%d", reg - FP_Base_DepTag); 2576261Sgblack@eecs.umich.edu } else { 2586261Sgblack@eecs.umich.edu reg -= Ctrl_Base_DepTag; 2596261Sgblack@eecs.umich.edu assert(reg < NUM_MISCREGS); 2606261Sgblack@eecs.umich.edu ccprintf(os, "%s", ArmISA::miscRegName[reg]); 2616253Sgblack@eecs.umich.edu } 2626253Sgblack@eecs.umich.edu} 2636253Sgblack@eecs.umich.edu 2646262Sgblack@eecs.umich.eduvoid 2657094Sgblack@eecs.umich.eduArmStaticInstBase::printMnemonic(std::ostream &os, 2666262Sgblack@eecs.umich.edu const std::string &suffix, 2676262Sgblack@eecs.umich.edu bool withPred) const 2686262Sgblack@eecs.umich.edu{ 2696262Sgblack@eecs.umich.edu os << " " << mnemonic; 2706262Sgblack@eecs.umich.edu if (withPred) { 2716262Sgblack@eecs.umich.edu unsigned condCode = machInst.condCode; 2726262Sgblack@eecs.umich.edu switch (condCode) { 2736262Sgblack@eecs.umich.edu case COND_EQ: 2746262Sgblack@eecs.umich.edu os << "eq"; 2756262Sgblack@eecs.umich.edu break; 2766262Sgblack@eecs.umich.edu case COND_NE: 2776262Sgblack@eecs.umich.edu os << "ne"; 2786262Sgblack@eecs.umich.edu break; 2796262Sgblack@eecs.umich.edu case COND_CS: 2806262Sgblack@eecs.umich.edu os << "cs"; 2816262Sgblack@eecs.umich.edu break; 2826262Sgblack@eecs.umich.edu case COND_CC: 2836262Sgblack@eecs.umich.edu os << "cc"; 2846262Sgblack@eecs.umich.edu break; 2856262Sgblack@eecs.umich.edu case COND_MI: 2866262Sgblack@eecs.umich.edu os << "mi"; 2876262Sgblack@eecs.umich.edu break; 2886262Sgblack@eecs.umich.edu case COND_PL: 2896262Sgblack@eecs.umich.edu os << "pl"; 2906262Sgblack@eecs.umich.edu break; 2916262Sgblack@eecs.umich.edu case COND_VS: 2926262Sgblack@eecs.umich.edu os << "vs"; 2936262Sgblack@eecs.umich.edu break; 2946262Sgblack@eecs.umich.edu case COND_VC: 2956262Sgblack@eecs.umich.edu os << "vc"; 2966262Sgblack@eecs.umich.edu break; 2976262Sgblack@eecs.umich.edu case COND_HI: 2986262Sgblack@eecs.umich.edu os << "hi"; 2996262Sgblack@eecs.umich.edu break; 3006262Sgblack@eecs.umich.edu case COND_LS: 3016262Sgblack@eecs.umich.edu os << "ls"; 3026262Sgblack@eecs.umich.edu break; 3036262Sgblack@eecs.umich.edu case COND_GE: 3046262Sgblack@eecs.umich.edu os << "ge"; 3056262Sgblack@eecs.umich.edu break; 3066262Sgblack@eecs.umich.edu case COND_LT: 3076262Sgblack@eecs.umich.edu os << "lt"; 3086262Sgblack@eecs.umich.edu break; 3096262Sgblack@eecs.umich.edu case COND_GT: 3106262Sgblack@eecs.umich.edu os << "gt"; 3116262Sgblack@eecs.umich.edu break; 3126262Sgblack@eecs.umich.edu case COND_LE: 3136262Sgblack@eecs.umich.edu os << "le"; 3146262Sgblack@eecs.umich.edu break; 3156262Sgblack@eecs.umich.edu case COND_AL: 3166262Sgblack@eecs.umich.edu // This one is implicit. 3176262Sgblack@eecs.umich.edu break; 3187111Sgblack@eecs.umich.edu case COND_UC: 3197111Sgblack@eecs.umich.edu // Unconditional. 3206262Sgblack@eecs.umich.edu break; 3216262Sgblack@eecs.umich.edu default: 3226262Sgblack@eecs.umich.edu panic("Unrecognized condition code %d.\n", condCode); 3236262Sgblack@eecs.umich.edu } 3247122Sgblack@eecs.umich.edu os << suffix; 3257122Sgblack@eecs.umich.edu if (machInst.bigThumb) 3267122Sgblack@eecs.umich.edu os << ".w"; 3277122Sgblack@eecs.umich.edu os << " "; 3286262Sgblack@eecs.umich.edu } 3296262Sgblack@eecs.umich.edu} 3306262Sgblack@eecs.umich.edu 3316263Sgblack@eecs.umich.eduvoid 3327094Sgblack@eecs.umich.eduArmStaticInstBase::printMemSymbol(std::ostream &os, 3336263Sgblack@eecs.umich.edu const SymbolTable *symtab, 3346263Sgblack@eecs.umich.edu const std::string &prefix, 3356263Sgblack@eecs.umich.edu const Addr addr, 3366263Sgblack@eecs.umich.edu const std::string &suffix) const 3376263Sgblack@eecs.umich.edu{ 3386263Sgblack@eecs.umich.edu Addr symbolAddr; 3396263Sgblack@eecs.umich.edu std::string symbol; 3406263Sgblack@eecs.umich.edu if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) { 3416263Sgblack@eecs.umich.edu ccprintf(os, "%s%s", prefix, symbol); 3426263Sgblack@eecs.umich.edu if (symbolAddr != addr) 3436263Sgblack@eecs.umich.edu ccprintf(os, "+%d", addr - symbolAddr); 3446263Sgblack@eecs.umich.edu ccprintf(os, suffix); 3456263Sgblack@eecs.umich.edu } 3466263Sgblack@eecs.umich.edu} 3476263Sgblack@eecs.umich.edu 3486264Sgblack@eecs.umich.eduvoid 3497142Sgblack@eecs.umich.eduArmStaticInstBase::printShiftOperand(std::ostream &os, 3507142Sgblack@eecs.umich.edu IntRegIndex rm, 3517142Sgblack@eecs.umich.edu bool immShift, 3527142Sgblack@eecs.umich.edu uint32_t shiftAmt, 3537142Sgblack@eecs.umich.edu IntRegIndex rs, 3547142Sgblack@eecs.umich.edu ArmShiftType type) const 3556264Sgblack@eecs.umich.edu{ 3567142Sgblack@eecs.umich.edu bool firstOp = false; 3576264Sgblack@eecs.umich.edu 3587142Sgblack@eecs.umich.edu if (rm != INTREG_ZERO) { 3597142Sgblack@eecs.umich.edu printReg(os, rm); 3607142Sgblack@eecs.umich.edu } 3617142Sgblack@eecs.umich.edu 3626306Sgblack@eecs.umich.edu bool done = false; 3636264Sgblack@eecs.umich.edu 3646306Sgblack@eecs.umich.edu if ((type == LSR || type == ASR) && immShift && shiftAmt == 0) 3656306Sgblack@eecs.umich.edu shiftAmt = 32; 3666264Sgblack@eecs.umich.edu 3676306Sgblack@eecs.umich.edu switch (type) { 3686306Sgblack@eecs.umich.edu case LSL: 3696306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 3706306Sgblack@eecs.umich.edu done = true; 3716264Sgblack@eecs.umich.edu break; 3726306Sgblack@eecs.umich.edu } 3737142Sgblack@eecs.umich.edu if (!firstOp) 3747142Sgblack@eecs.umich.edu os << ", "; 3757142Sgblack@eecs.umich.edu os << "LSL"; 3766306Sgblack@eecs.umich.edu break; 3776306Sgblack@eecs.umich.edu case LSR: 3787142Sgblack@eecs.umich.edu if (!firstOp) 3797142Sgblack@eecs.umich.edu os << ", "; 3807142Sgblack@eecs.umich.edu os << "LSR"; 3816306Sgblack@eecs.umich.edu break; 3826306Sgblack@eecs.umich.edu case ASR: 3837142Sgblack@eecs.umich.edu if (!firstOp) 3847142Sgblack@eecs.umich.edu os << ", "; 3857142Sgblack@eecs.umich.edu os << "ASR"; 3866306Sgblack@eecs.umich.edu break; 3876306Sgblack@eecs.umich.edu case ROR: 3886306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 3897142Sgblack@eecs.umich.edu if (!firstOp) 3907142Sgblack@eecs.umich.edu os << ", "; 3917142Sgblack@eecs.umich.edu os << "RRX"; 3926306Sgblack@eecs.umich.edu done = true; 3936264Sgblack@eecs.umich.edu break; 3946264Sgblack@eecs.umich.edu } 3957142Sgblack@eecs.umich.edu if (!firstOp) 3967142Sgblack@eecs.umich.edu os << ", "; 3977142Sgblack@eecs.umich.edu os << "ROR"; 3986306Sgblack@eecs.umich.edu break; 3996306Sgblack@eecs.umich.edu default: 4006306Sgblack@eecs.umich.edu panic("Tried to disassemble unrecognized shift type.\n"); 4016306Sgblack@eecs.umich.edu } 4026306Sgblack@eecs.umich.edu if (!done) { 4037142Sgblack@eecs.umich.edu if (!firstOp) 4047142Sgblack@eecs.umich.edu os << " "; 4056306Sgblack@eecs.umich.edu if (immShift) 4066306Sgblack@eecs.umich.edu os << "#" << shiftAmt; 4076306Sgblack@eecs.umich.edu else 4087142Sgblack@eecs.umich.edu printReg(os, rs); 4096264Sgblack@eecs.umich.edu } 4106264Sgblack@eecs.umich.edu} 4116264Sgblack@eecs.umich.edu 4126264Sgblack@eecs.umich.eduvoid 4137142Sgblack@eecs.umich.eduArmStaticInstBase::printDataInst(std::ostream &os, bool withImm, 4147142Sgblack@eecs.umich.edu bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, 4157142Sgblack@eecs.umich.edu IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, 4167142Sgblack@eecs.umich.edu ArmShiftType type, uint32_t imm) const 4176264Sgblack@eecs.umich.edu{ 4187142Sgblack@eecs.umich.edu printMnemonic(os, s ? "s" : ""); 4196264Sgblack@eecs.umich.edu bool firstOp = true; 4206264Sgblack@eecs.umich.edu 4216264Sgblack@eecs.umich.edu // Destination 4227142Sgblack@eecs.umich.edu if (rd != INTREG_ZERO) { 4236264Sgblack@eecs.umich.edu firstOp = false; 4247142Sgblack@eecs.umich.edu printReg(os, rd); 4256264Sgblack@eecs.umich.edu } 4266264Sgblack@eecs.umich.edu 4276264Sgblack@eecs.umich.edu // Source 1. 4287142Sgblack@eecs.umich.edu if (rn != INTREG_ZERO) { 4296264Sgblack@eecs.umich.edu if (!firstOp) 4306264Sgblack@eecs.umich.edu os << ", "; 4316264Sgblack@eecs.umich.edu firstOp = false; 4327142Sgblack@eecs.umich.edu printReg(os, rn); 4336264Sgblack@eecs.umich.edu } 4346264Sgblack@eecs.umich.edu 4356264Sgblack@eecs.umich.edu if (!firstOp) 4366264Sgblack@eecs.umich.edu os << ", "; 4376306Sgblack@eecs.umich.edu if (withImm) { 4387142Sgblack@eecs.umich.edu ccprintf(os, "#%d", imm); 4396306Sgblack@eecs.umich.edu } else { 4407142Sgblack@eecs.umich.edu printShiftOperand(os, rm, immShift, shiftAmt, rs, type); 4416306Sgblack@eecs.umich.edu } 4426264Sgblack@eecs.umich.edu} 4436264Sgblack@eecs.umich.edu 4446254Sgblack@eecs.umich.edustd::string 4457094Sgblack@eecs.umich.eduArmStaticInstBase::generateDisassembly(Addr pc, 4466254Sgblack@eecs.umich.edu const SymbolTable *symtab) const 4476253Sgblack@eecs.umich.edu{ 4486253Sgblack@eecs.umich.edu std::stringstream ss; 4496262Sgblack@eecs.umich.edu printMnemonic(ss); 4506253Sgblack@eecs.umich.edu return ss.str(); 4516253Sgblack@eecs.umich.edu} 4526253Sgblack@eecs.umich.edu} 453