static_inst.cc revision 6255
16253Sgblack@eecs.umich.edu/* Copyright (c) 2007-2008 The Florida State University 26253Sgblack@eecs.umich.edu * All rights reserved. 36253Sgblack@eecs.umich.edu * 46253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 56253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 66253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 76253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 86253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 96253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 106253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 116253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 126253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 136253Sgblack@eecs.umich.edu * this software without specific prior written permission. 146253Sgblack@eecs.umich.edu * 156253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266253Sgblack@eecs.umich.edu * 276253Sgblack@eecs.umich.edu * Authors: Stephen Hines 286253Sgblack@eecs.umich.edu */ 296253Sgblack@eecs.umich.edu 306253Sgblack@eecs.umich.edu#include "arch/arm/insts/static_inst.hh" 316255Sgblack@eecs.umich.edu#include "base/condcodes.hh" 326253Sgblack@eecs.umich.edu 336253Sgblack@eecs.umich.edunamespace ArmISA 346253Sgblack@eecs.umich.edu{ 356254Sgblack@eecs.umich.edu// Shift Rm by an immediate value 366254Sgblack@eecs.umich.eduint32_t 376254Sgblack@eecs.umich.eduArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt, 386254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 396254Sgblack@eecs.umich.edu{ 406255Sgblack@eecs.umich.edu assert(shamt < 32); 416255Sgblack@eecs.umich.edu ArmShiftType shiftType; 426255Sgblack@eecs.umich.edu shiftType = (ArmShiftType)type; 436254Sgblack@eecs.umich.edu 446254Sgblack@eecs.umich.edu switch (shiftType) 456254Sgblack@eecs.umich.edu { 466255Sgblack@eecs.umich.edu case LSL: 476255Sgblack@eecs.umich.edu return base << shamt; 486255Sgblack@eecs.umich.edu case LSR: 496255Sgblack@eecs.umich.edu if (shamt == 0) 506255Sgblack@eecs.umich.edu return 0; 516255Sgblack@eecs.umich.edu else 526255Sgblack@eecs.umich.edu return base >> shamt; 536255Sgblack@eecs.umich.edu case ASR: 546255Sgblack@eecs.umich.edu if (shamt == 0) 556255Sgblack@eecs.umich.edu return (int32_t)base >> 31; 566255Sgblack@eecs.umich.edu else 576255Sgblack@eecs.umich.edu return (int32_t)base >> shamt; 586255Sgblack@eecs.umich.edu case ROR: 596255Sgblack@eecs.umich.edu if (shamt == 0) 606255Sgblack@eecs.umich.edu return (cfval << 31) | (base >> 1); // RRX 616255Sgblack@eecs.umich.edu else 626255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 636255Sgblack@eecs.umich.edu default: 646255Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 656255Sgblack@eecs.umich.edu exit(1); 666255Sgblack@eecs.umich.edu break; 676254Sgblack@eecs.umich.edu } 686254Sgblack@eecs.umich.edu return 0; 696254Sgblack@eecs.umich.edu} 706254Sgblack@eecs.umich.edu 716254Sgblack@eecs.umich.edu// Shift Rm by Rs 726254Sgblack@eecs.umich.eduint32_t 736254Sgblack@eecs.umich.eduArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt, 746254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 756254Sgblack@eecs.umich.edu{ 766254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 776254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 786254Sgblack@eecs.umich.edu 796254Sgblack@eecs.umich.edu switch (shiftType) 806254Sgblack@eecs.umich.edu { 816255Sgblack@eecs.umich.edu case LSL: 826255Sgblack@eecs.umich.edu if (shamt >= 32) 836255Sgblack@eecs.umich.edu return 0; 846255Sgblack@eecs.umich.edu else 856255Sgblack@eecs.umich.edu return base << shamt; 866255Sgblack@eecs.umich.edu case LSR: 876255Sgblack@eecs.umich.edu if (shamt >= 32) 886255Sgblack@eecs.umich.edu return 0; 896255Sgblack@eecs.umich.edu else 906255Sgblack@eecs.umich.edu return base >> shamt; 916255Sgblack@eecs.umich.edu case ASR: 926255Sgblack@eecs.umich.edu if (shamt >= 32) 936255Sgblack@eecs.umich.edu return (int32_t)base >> 31; 946255Sgblack@eecs.umich.edu else 956255Sgblack@eecs.umich.edu return (int32_t)base >> shamt; 966255Sgblack@eecs.umich.edu case ROR: 976255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 986255Sgblack@eecs.umich.edu if (shamt == 0) 996255Sgblack@eecs.umich.edu return base; 1006255Sgblack@eecs.umich.edu else 1016255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 1026255Sgblack@eecs.umich.edu default: 1036255Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 1046255Sgblack@eecs.umich.edu exit(1); 1056255Sgblack@eecs.umich.edu break; 1066254Sgblack@eecs.umich.edu } 1076254Sgblack@eecs.umich.edu return 0; 1086254Sgblack@eecs.umich.edu} 1096254Sgblack@eecs.umich.edu 1106254Sgblack@eecs.umich.edu 1116254Sgblack@eecs.umich.edu// Generate C for a shift by immediate 1126255Sgblack@eecs.umich.edubool 1136254Sgblack@eecs.umich.eduArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt, 1146254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1156254Sgblack@eecs.umich.edu{ 1166254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1176254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1186254Sgblack@eecs.umich.edu 1196254Sgblack@eecs.umich.edu switch (shiftType) 1206254Sgblack@eecs.umich.edu { 1216255Sgblack@eecs.umich.edu case LSL: 1226255Sgblack@eecs.umich.edu if (shamt == 0) 1236255Sgblack@eecs.umich.edu return cfval; 1246255Sgblack@eecs.umich.edu else 1256254Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1266255Sgblack@eecs.umich.edu case LSR: 1276255Sgblack@eecs.umich.edu if (shamt == 0) 1286255Sgblack@eecs.umich.edu return (base >> 31); 1296255Sgblack@eecs.umich.edu else 1306255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1316255Sgblack@eecs.umich.edu case ASR: 1326255Sgblack@eecs.umich.edu if (shamt == 0) 1336255Sgblack@eecs.umich.edu return (base >> 31); 1346255Sgblack@eecs.umich.edu else 1356255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1366255Sgblack@eecs.umich.edu case ROR: 1376255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1386255Sgblack@eecs.umich.edu if (shamt == 0) 1396255Sgblack@eecs.umich.edu return (base & 1); // RRX 1406255Sgblack@eecs.umich.edu else 1416255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1426255Sgblack@eecs.umich.edu default: 1436255Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 1446255Sgblack@eecs.umich.edu exit(1); 1456255Sgblack@eecs.umich.edu break; 1466254Sgblack@eecs.umich.edu } 1476254Sgblack@eecs.umich.edu return 0; 1486254Sgblack@eecs.umich.edu} 1496254Sgblack@eecs.umich.edu 1506254Sgblack@eecs.umich.edu 1516254Sgblack@eecs.umich.edu// Generate C for a shift by Rs 1526255Sgblack@eecs.umich.edubool 1536254Sgblack@eecs.umich.eduArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, 1546254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1556254Sgblack@eecs.umich.edu{ 1566254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1576254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1586254Sgblack@eecs.umich.edu 1596255Sgblack@eecs.umich.edu if (shamt == 0) 1606255Sgblack@eecs.umich.edu return cfval; 1616255Sgblack@eecs.umich.edu 1626254Sgblack@eecs.umich.edu switch (shiftType) 1636254Sgblack@eecs.umich.edu { 1646255Sgblack@eecs.umich.edu case LSL: 1656255Sgblack@eecs.umich.edu if (shamt > 32) 1666255Sgblack@eecs.umich.edu return 0; 1676255Sgblack@eecs.umich.edu else 1686255Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1696255Sgblack@eecs.umich.edu case LSR: 1706255Sgblack@eecs.umich.edu if (shamt > 32) 1716255Sgblack@eecs.umich.edu return 0; 1726255Sgblack@eecs.umich.edu else 1736255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1746255Sgblack@eecs.umich.edu case ASR: 1756255Sgblack@eecs.umich.edu if (shamt > 32) 1766255Sgblack@eecs.umich.edu shamt = 32; 1776255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1786255Sgblack@eecs.umich.edu case ROR: 1796255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1806255Sgblack@eecs.umich.edu if (shamt == 0) 1816255Sgblack@eecs.umich.edu shamt = 32; 1826255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1836255Sgblack@eecs.umich.edu default: 1846255Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 1856255Sgblack@eecs.umich.edu exit(1); 1866255Sgblack@eecs.umich.edu break; 1876254Sgblack@eecs.umich.edu } 1886254Sgblack@eecs.umich.edu return 0; 1896254Sgblack@eecs.umich.edu} 1906254Sgblack@eecs.umich.edu 1916254Sgblack@eecs.umich.edu 1926254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for an addition operation 1936255Sgblack@eecs.umich.edubool 1946254Sgblack@eecs.umich.eduArmStaticInst::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const 1956254Sgblack@eecs.umich.edu{ 1966255Sgblack@eecs.umich.edu return findCarry(32, result, lhs, rhs); 1976254Sgblack@eecs.umich.edu} 1986254Sgblack@eecs.umich.edu 1996254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for a subtraction operation 2006255Sgblack@eecs.umich.edubool 2016254Sgblack@eecs.umich.eduArmStaticInst::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const 2026254Sgblack@eecs.umich.edu{ 2036255Sgblack@eecs.umich.edu return findCarry(32, result, lhs, ~rhs); 2046254Sgblack@eecs.umich.edu} 2056254Sgblack@eecs.umich.edu 2066255Sgblack@eecs.umich.edubool 2076254Sgblack@eecs.umich.eduArmStaticInst::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2086254Sgblack@eecs.umich.edu{ 2096255Sgblack@eecs.umich.edu return findOverflow(32, result, lhs, rhs); 2106254Sgblack@eecs.umich.edu} 2116254Sgblack@eecs.umich.edu 2126255Sgblack@eecs.umich.edubool 2136254Sgblack@eecs.umich.eduArmStaticInst::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2146254Sgblack@eecs.umich.edu{ 2156255Sgblack@eecs.umich.edu return findOverflow(32, result, lhs, ~rhs); 2166254Sgblack@eecs.umich.edu} 2176254Sgblack@eecs.umich.edu 2186254Sgblack@eecs.umich.eduvoid 2196254Sgblack@eecs.umich.eduArmStaticInst::printReg(std::ostream &os, int reg) const 2206253Sgblack@eecs.umich.edu{ 2216253Sgblack@eecs.umich.edu if (reg < FP_Base_DepTag) { 2226253Sgblack@eecs.umich.edu ccprintf(os, "r%d", reg); 2236253Sgblack@eecs.umich.edu } 2246253Sgblack@eecs.umich.edu else { 2256253Sgblack@eecs.umich.edu ccprintf(os, "f%d", reg - FP_Base_DepTag); 2266253Sgblack@eecs.umich.edu } 2276253Sgblack@eecs.umich.edu} 2286253Sgblack@eecs.umich.edu 2296254Sgblack@eecs.umich.edustd::string 2306254Sgblack@eecs.umich.eduArmStaticInst::generateDisassembly(Addr pc, 2316254Sgblack@eecs.umich.edu const SymbolTable *symtab) const 2326253Sgblack@eecs.umich.edu{ 2336253Sgblack@eecs.umich.edu std::stringstream ss; 2346253Sgblack@eecs.umich.edu 2356253Sgblack@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 2366253Sgblack@eecs.umich.edu 2376253Sgblack@eecs.umich.edu return ss.str(); 2386253Sgblack@eecs.umich.edu} 2396253Sgblack@eecs.umich.edu} 240