static_inst.cc revision 6254
16253Sgblack@eecs.umich.edu/* Copyright (c) 2007-2008 The Florida State University 26253Sgblack@eecs.umich.edu * All rights reserved. 36253Sgblack@eecs.umich.edu * 46253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 56253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 66253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 76253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 86253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 96253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 106253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 116253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 126253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 136253Sgblack@eecs.umich.edu * this software without specific prior written permission. 146253Sgblack@eecs.umich.edu * 156253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 166253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 176253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 186253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 196253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 206253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 216253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 226253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 236253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 246253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 256253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 266253Sgblack@eecs.umich.edu * 276253Sgblack@eecs.umich.edu * Authors: Stephen Hines 286253Sgblack@eecs.umich.edu */ 296253Sgblack@eecs.umich.edu 306253Sgblack@eecs.umich.edu#include "arch/arm/insts/static_inst.hh" 316253Sgblack@eecs.umich.edu 326253Sgblack@eecs.umich.edunamespace ArmISA 336253Sgblack@eecs.umich.edu{ 346254Sgblack@eecs.umich.edustatic int32_t arm_NEG(int32_t val) { return (val >> 31); } 356254Sgblack@eecs.umich.edustatic int32_t arm_POS(int32_t val) { return ((~val) >> 31); } 366254Sgblack@eecs.umich.edu 376254Sgblack@eecs.umich.edu// Shift Rm by an immediate value 386254Sgblack@eecs.umich.eduint32_t 396254Sgblack@eecs.umich.eduArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt, 406254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 416254Sgblack@eecs.umich.edu{ 426254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 436254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 446254Sgblack@eecs.umich.edu 456254Sgblack@eecs.umich.edu switch (shiftType) 466254Sgblack@eecs.umich.edu { 476254Sgblack@eecs.umich.edu case LSL: 486254Sgblack@eecs.umich.edu return (base << shamt); 496254Sgblack@eecs.umich.edu case LSR: 506254Sgblack@eecs.umich.edu if (shamt == 0) 516254Sgblack@eecs.umich.edu return (0); 526254Sgblack@eecs.umich.edu else 536254Sgblack@eecs.umich.edu return (base >> shamt); 546254Sgblack@eecs.umich.edu case ASR: 556254Sgblack@eecs.umich.edu if (shamt == 0) 566254Sgblack@eecs.umich.edu return ((uint32_t) ((int32_t) base >> 31L)); 576254Sgblack@eecs.umich.edu else 586254Sgblack@eecs.umich.edu return ((uint32_t) (((int32_t) base) >> shamt)); 596254Sgblack@eecs.umich.edu case ROR: 606254Sgblack@eecs.umich.edu //shamt = shamt & 0x1f; 616254Sgblack@eecs.umich.edu if (shamt == 0) 626254Sgblack@eecs.umich.edu return (cfval << 31) | (base >> 1); // RRX 636254Sgblack@eecs.umich.edu else 646254Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 656254Sgblack@eecs.umich.edu default: 666254Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 676254Sgblack@eecs.umich.edu exit(1); 686254Sgblack@eecs.umich.edu break; 696254Sgblack@eecs.umich.edu } 706254Sgblack@eecs.umich.edu return 0; 716254Sgblack@eecs.umich.edu} 726254Sgblack@eecs.umich.edu 736254Sgblack@eecs.umich.edu// Shift Rm by Rs 746254Sgblack@eecs.umich.eduint32_t 756254Sgblack@eecs.umich.eduArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt, 766254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 776254Sgblack@eecs.umich.edu{ 786254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 796254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 806254Sgblack@eecs.umich.edu 816254Sgblack@eecs.umich.edu switch (shiftType) 826254Sgblack@eecs.umich.edu { 836254Sgblack@eecs.umich.edu case LSL: 846254Sgblack@eecs.umich.edu if (shamt == 0) 856254Sgblack@eecs.umich.edu return (base); 866254Sgblack@eecs.umich.edu else if (shamt >= 32) 876254Sgblack@eecs.umich.edu return (0); 886254Sgblack@eecs.umich.edu else 896254Sgblack@eecs.umich.edu return (base << shamt); 906254Sgblack@eecs.umich.edu case LSR: 916254Sgblack@eecs.umich.edu if (shamt == 0) 926254Sgblack@eecs.umich.edu return (base); 936254Sgblack@eecs.umich.edu else if (shamt >= 32) 946254Sgblack@eecs.umich.edu return (0); 956254Sgblack@eecs.umich.edu else 966254Sgblack@eecs.umich.edu return (base >> shamt); 976254Sgblack@eecs.umich.edu case ASR: 986254Sgblack@eecs.umich.edu if (shamt == 0) 996254Sgblack@eecs.umich.edu return base; 1006254Sgblack@eecs.umich.edu else if (shamt >= 32) 1016254Sgblack@eecs.umich.edu return ((uint32_t) ((int32_t) base >> 31L)); 1026254Sgblack@eecs.umich.edu else 1036254Sgblack@eecs.umich.edu return ((uint32_t) (((int32_t) base) >> (int) shamt)); 1046254Sgblack@eecs.umich.edu case ROR: 1056254Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1066254Sgblack@eecs.umich.edu if (shamt == 0) 1076254Sgblack@eecs.umich.edu return (base); 1086254Sgblack@eecs.umich.edu else 1096254Sgblack@eecs.umich.edu return ((base << (32 - shamt)) | (base >> shamt)); 1106254Sgblack@eecs.umich.edu default: 1116254Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 1126254Sgblack@eecs.umich.edu exit(1); 1136254Sgblack@eecs.umich.edu break; 1146254Sgblack@eecs.umich.edu } 1156254Sgblack@eecs.umich.edu return 0; 1166254Sgblack@eecs.umich.edu} 1176254Sgblack@eecs.umich.edu 1186254Sgblack@eecs.umich.edu 1196254Sgblack@eecs.umich.edu// Generate C for a shift by immediate 1206254Sgblack@eecs.umich.eduint32_t 1216254Sgblack@eecs.umich.eduArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt, 1226254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1236254Sgblack@eecs.umich.edu{ 1246254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1256254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1266254Sgblack@eecs.umich.edu 1276254Sgblack@eecs.umich.edu switch (shiftType) 1286254Sgblack@eecs.umich.edu { 1296254Sgblack@eecs.umich.edu case LSL: 1306254Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 1316254Sgblack@eecs.umich.edu case LSR: 1326254Sgblack@eecs.umich.edu if (shamt == 0) 1336254Sgblack@eecs.umich.edu return (base >> 31) & 1; 1346254Sgblack@eecs.umich.edu else 1356254Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1366254Sgblack@eecs.umich.edu case ASR: 1376254Sgblack@eecs.umich.edu if (shamt == 0) 1386254Sgblack@eecs.umich.edu return (base >> 31L); 1396254Sgblack@eecs.umich.edu else 1406254Sgblack@eecs.umich.edu return ((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1; 1416254Sgblack@eecs.umich.edu case ROR: 1426254Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1436254Sgblack@eecs.umich.edu if (shamt == 0) 1446254Sgblack@eecs.umich.edu return (base & 1); // RRX 1456254Sgblack@eecs.umich.edu else 1466254Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 1476254Sgblack@eecs.umich.edu default: 1486254Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 1496254Sgblack@eecs.umich.edu exit(1); 1506254Sgblack@eecs.umich.edu break; 1516254Sgblack@eecs.umich.edu 1526254Sgblack@eecs.umich.edu } 1536254Sgblack@eecs.umich.edu return 0; 1546254Sgblack@eecs.umich.edu} 1556254Sgblack@eecs.umich.edu 1566254Sgblack@eecs.umich.edu 1576254Sgblack@eecs.umich.edu// Generate C for a shift by Rs 1586254Sgblack@eecs.umich.eduint32_t 1596254Sgblack@eecs.umich.eduArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, 1606254Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1616254Sgblack@eecs.umich.edu{ 1626254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1636254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1646254Sgblack@eecs.umich.edu 1656254Sgblack@eecs.umich.edu switch (shiftType) 1666254Sgblack@eecs.umich.edu { 1676254Sgblack@eecs.umich.edu case LSL: 1686254Sgblack@eecs.umich.edu if (shamt == 0) 1696254Sgblack@eecs.umich.edu return (!!cfval); 1706254Sgblack@eecs.umich.edu else if (shamt == 32) 1716254Sgblack@eecs.umich.edu return (base & 1); 1726254Sgblack@eecs.umich.edu else if (shamt > 32) 1736254Sgblack@eecs.umich.edu return (0); 1746254Sgblack@eecs.umich.edu else 1756254Sgblack@eecs.umich.edu return ((base >> (32 - shamt)) & 1); 1766254Sgblack@eecs.umich.edu case LSR: 1776254Sgblack@eecs.umich.edu if (shamt == 0) 1786254Sgblack@eecs.umich.edu return (!!cfval); 1796254Sgblack@eecs.umich.edu else if (shamt == 32) 1806254Sgblack@eecs.umich.edu return (base >> 31); 1816254Sgblack@eecs.umich.edu else if (shamt > 32) 1826254Sgblack@eecs.umich.edu return (0); 1836254Sgblack@eecs.umich.edu else 1846254Sgblack@eecs.umich.edu return ((base >> (shamt - 1)) & 1); 1856254Sgblack@eecs.umich.edu case ASR: 1866254Sgblack@eecs.umich.edu if (shamt == 0) 1876254Sgblack@eecs.umich.edu return (!!cfval); 1886254Sgblack@eecs.umich.edu else if (shamt >= 32) 1896254Sgblack@eecs.umich.edu return (base >> 31L); 1906254Sgblack@eecs.umich.edu else 1916254Sgblack@eecs.umich.edu return (((uint32_t) (((int32_t) base) >> (shamt - 1))) & 1); 1926254Sgblack@eecs.umich.edu case ROR: 1936254Sgblack@eecs.umich.edu if (shamt == 0) 1946254Sgblack@eecs.umich.edu return (!!cfval); 1956254Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 1966254Sgblack@eecs.umich.edu if (shamt == 0) 1976254Sgblack@eecs.umich.edu return (base >> 31); // RRX 1986254Sgblack@eecs.umich.edu else 1996254Sgblack@eecs.umich.edu return ((base >> (shamt - 1)) & 1); 2006254Sgblack@eecs.umich.edu default: 2016254Sgblack@eecs.umich.edu fprintf(stderr, "Unhandled shift type\n"); 2026254Sgblack@eecs.umich.edu exit(1); 2036254Sgblack@eecs.umich.edu break; 2046254Sgblack@eecs.umich.edu 2056254Sgblack@eecs.umich.edu } 2066254Sgblack@eecs.umich.edu return 0; 2076254Sgblack@eecs.umich.edu} 2086254Sgblack@eecs.umich.edu 2096254Sgblack@eecs.umich.edu 2106254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for an addition operation 2116254Sgblack@eecs.umich.eduint32_t 2126254Sgblack@eecs.umich.eduArmStaticInst::arm_add_carry(int32_t result, int32_t lhs, int32_t rhs) const 2136254Sgblack@eecs.umich.edu{ 2146254Sgblack@eecs.umich.edu if ((lhs | rhs) >> 30) 2156254Sgblack@eecs.umich.edu return ((arm_NEG(lhs) && arm_NEG(rhs)) || 2166254Sgblack@eecs.umich.edu (arm_NEG(lhs) && arm_POS(result)) || 2176254Sgblack@eecs.umich.edu (arm_NEG(rhs) && arm_POS(result))); 2186254Sgblack@eecs.umich.edu 2196254Sgblack@eecs.umich.edu return 0; 2206254Sgblack@eecs.umich.edu} 2216254Sgblack@eecs.umich.edu 2226254Sgblack@eecs.umich.edu// Generate the appropriate carry bit for a subtraction operation 2236254Sgblack@eecs.umich.eduint32_t 2246254Sgblack@eecs.umich.eduArmStaticInst::arm_sub_carry(int32_t result, int32_t lhs, int32_t rhs) const 2256254Sgblack@eecs.umich.edu{ 2266254Sgblack@eecs.umich.edu if ((lhs >= rhs) || ((rhs | lhs) >> 31)) 2276254Sgblack@eecs.umich.edu return ((arm_NEG(lhs) && arm_POS(rhs)) || 2286254Sgblack@eecs.umich.edu (arm_NEG(lhs) && arm_POS(result)) || 2296254Sgblack@eecs.umich.edu (arm_POS(rhs) && arm_POS(result))); 2306254Sgblack@eecs.umich.edu 2316254Sgblack@eecs.umich.edu return 0; 2326254Sgblack@eecs.umich.edu} 2336254Sgblack@eecs.umich.edu 2346254Sgblack@eecs.umich.eduint32_t 2356254Sgblack@eecs.umich.eduArmStaticInst::arm_add_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2366254Sgblack@eecs.umich.edu{ 2376254Sgblack@eecs.umich.edu if ((lhs | rhs) >> 30) 2386254Sgblack@eecs.umich.edu return ((arm_NEG(lhs) && arm_NEG(rhs) && arm_POS(result)) || 2396254Sgblack@eecs.umich.edu (arm_POS(lhs) && arm_POS(rhs) && arm_NEG(result))); 2406254Sgblack@eecs.umich.edu 2416254Sgblack@eecs.umich.edu return 0; 2426254Sgblack@eecs.umich.edu} 2436254Sgblack@eecs.umich.edu 2446254Sgblack@eecs.umich.eduint32_t 2456254Sgblack@eecs.umich.eduArmStaticInst::arm_sub_overflow(int32_t result, int32_t lhs, int32_t rhs) const 2466254Sgblack@eecs.umich.edu{ 2476254Sgblack@eecs.umich.edu if ((lhs >= rhs) || ((rhs | lhs) >> 31)) 2486254Sgblack@eecs.umich.edu return ((arm_NEG(lhs) && arm_POS(rhs) && arm_POS(result)) || 2496254Sgblack@eecs.umich.edu (arm_POS(lhs) && arm_NEG(rhs) && arm_NEG(result))); 2506254Sgblack@eecs.umich.edu 2516254Sgblack@eecs.umich.edu return 0; 2526254Sgblack@eecs.umich.edu} 2536254Sgblack@eecs.umich.edu 2546254Sgblack@eecs.umich.eduvoid 2556254Sgblack@eecs.umich.eduArmStaticInst::printReg(std::ostream &os, int reg) const 2566253Sgblack@eecs.umich.edu{ 2576253Sgblack@eecs.umich.edu if (reg < FP_Base_DepTag) { 2586253Sgblack@eecs.umich.edu ccprintf(os, "r%d", reg); 2596253Sgblack@eecs.umich.edu } 2606253Sgblack@eecs.umich.edu else { 2616253Sgblack@eecs.umich.edu ccprintf(os, "f%d", reg - FP_Base_DepTag); 2626253Sgblack@eecs.umich.edu } 2636253Sgblack@eecs.umich.edu} 2646253Sgblack@eecs.umich.edu 2656254Sgblack@eecs.umich.edustd::string 2666254Sgblack@eecs.umich.eduArmStaticInst::generateDisassembly(Addr pc, 2676254Sgblack@eecs.umich.edu const SymbolTable *symtab) const 2686253Sgblack@eecs.umich.edu{ 2696253Sgblack@eecs.umich.edu std::stringstream ss; 2706253Sgblack@eecs.umich.edu 2716253Sgblack@eecs.umich.edu ccprintf(ss, "%-10s ", mnemonic); 2726253Sgblack@eecs.umich.edu 2736253Sgblack@eecs.umich.edu return ss.str(); 2746253Sgblack@eecs.umich.edu} 2756253Sgblack@eecs.umich.edu} 276