static_inst.cc revision 11371
17094Sgblack@eecs.umich.edu/* 210338SCurtis.Dunham@arm.com * Copyright (c) 2010-2014 ARM Limited 39913Ssteve.reinhardt@amd.com * Copyright (c) 2013 Advanced Micro Devices, Inc. 47094Sgblack@eecs.umich.edu * All rights reserved 57094Sgblack@eecs.umich.edu * 67094Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 77094Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 87094Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 97094Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 107094Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 117094Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 127094Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 137094Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 147094Sgblack@eecs.umich.edu * 157094Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 166253Sgblack@eecs.umich.edu * All rights reserved. 176253Sgblack@eecs.umich.edu * 186253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 196253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 206253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 216253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 226253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 236253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 246253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 256253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 266253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 276253Sgblack@eecs.umich.edu * this software without specific prior written permission. 286253Sgblack@eecs.umich.edu * 296253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 306253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 316253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 326253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 336253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 346253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 356253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 366253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 376253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 386253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 396253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 406253Sgblack@eecs.umich.edu * 416253Sgblack@eecs.umich.edu * Authors: Stephen Hines 426253Sgblack@eecs.umich.edu */ 436253Sgblack@eecs.umich.edu 448229Snate@binkert.org#include "arch/arm/insts/static_inst.hh" 456759SAli.Saidi@ARM.com#include "arch/arm/faults.hh" 468229Snate@binkert.org#include "base/loader/symtab.hh" 476255Sgblack@eecs.umich.edu#include "base/condcodes.hh" 486712Snate@binkert.org#include "base/cprintf.hh" 499913Ssteve.reinhardt@amd.com#include "cpu/reg_class.hh" 506253Sgblack@eecs.umich.edu 516253Sgblack@eecs.umich.edunamespace ArmISA 526253Sgblack@eecs.umich.edu{ 536254Sgblack@eecs.umich.edu// Shift Rm by an immediate value 546254Sgblack@eecs.umich.eduint32_t 557148Sgblack@eecs.umich.eduArmStaticInst::shift_rm_imm(uint32_t base, uint32_t shamt, 567094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 576254Sgblack@eecs.umich.edu{ 586255Sgblack@eecs.umich.edu assert(shamt < 32); 596255Sgblack@eecs.umich.edu ArmShiftType shiftType; 606255Sgblack@eecs.umich.edu shiftType = (ArmShiftType)type; 616254Sgblack@eecs.umich.edu 626254Sgblack@eecs.umich.edu switch (shiftType) 636254Sgblack@eecs.umich.edu { 646255Sgblack@eecs.umich.edu case LSL: 656255Sgblack@eecs.umich.edu return base << shamt; 666255Sgblack@eecs.umich.edu case LSR: 676255Sgblack@eecs.umich.edu if (shamt == 0) 686255Sgblack@eecs.umich.edu return 0; 696255Sgblack@eecs.umich.edu else 706255Sgblack@eecs.umich.edu return base >> shamt; 716255Sgblack@eecs.umich.edu case ASR: 726255Sgblack@eecs.umich.edu if (shamt == 0) 737182Sgblack@eecs.umich.edu return (base >> 31) | -((base & (1 << 31)) >> 31); 746255Sgblack@eecs.umich.edu else 757182Sgblack@eecs.umich.edu return (base >> shamt) | -((base & (1 << 31)) >> shamt); 766255Sgblack@eecs.umich.edu case ROR: 776255Sgblack@eecs.umich.edu if (shamt == 0) 786255Sgblack@eecs.umich.edu return (cfval << 31) | (base >> 1); // RRX 796255Sgblack@eecs.umich.edu else 806255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 816255Sgblack@eecs.umich.edu default: 826712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 836255Sgblack@eecs.umich.edu exit(1); 846255Sgblack@eecs.umich.edu break; 856254Sgblack@eecs.umich.edu } 866254Sgblack@eecs.umich.edu return 0; 876254Sgblack@eecs.umich.edu} 886254Sgblack@eecs.umich.edu 8910037SARM gem5 Developersint64_t 9010037SARM gem5 DevelopersArmStaticInst::shiftReg64(uint64_t base, uint64_t shiftAmt, 9110037SARM gem5 Developers ArmShiftType type, uint8_t width) const 9210037SARM gem5 Developers{ 9310037SARM gem5 Developers shiftAmt = shiftAmt % width; 9410037SARM gem5 Developers ArmShiftType shiftType; 9510037SARM gem5 Developers shiftType = (ArmShiftType)type; 9610037SARM gem5 Developers 9710037SARM gem5 Developers switch (shiftType) 9810037SARM gem5 Developers { 9910037SARM gem5 Developers case LSL: 10010037SARM gem5 Developers return base << shiftAmt; 10110037SARM gem5 Developers case LSR: 10210037SARM gem5 Developers if (shiftAmt == 0) 10310037SARM gem5 Developers return base; 10410037SARM gem5 Developers else 10510037SARM gem5 Developers return (base & mask(width)) >> shiftAmt; 10610037SARM gem5 Developers case ASR: 10710037SARM gem5 Developers if (shiftAmt == 0) { 10810037SARM gem5 Developers return base; 10910037SARM gem5 Developers } else { 11010037SARM gem5 Developers int sign_bit = bits(base, intWidth - 1); 11110037SARM gem5 Developers base >>= shiftAmt; 11210037SARM gem5 Developers base = sign_bit ? (base | ~mask(intWidth - shiftAmt)) : base; 11310037SARM gem5 Developers return base & mask(intWidth); 11410037SARM gem5 Developers } 11510037SARM gem5 Developers case ROR: 11610037SARM gem5 Developers if (shiftAmt == 0) 11710037SARM gem5 Developers return base; 11810037SARM gem5 Developers else 11910037SARM gem5 Developers return (base << (width - shiftAmt)) | (base >> shiftAmt); 12010037SARM gem5 Developers default: 12110037SARM gem5 Developers ccprintf(std::cerr, "Unhandled shift type\n"); 12210037SARM gem5 Developers exit(1); 12310037SARM gem5 Developers break; 12410037SARM gem5 Developers } 12510037SARM gem5 Developers return 0; 12610037SARM gem5 Developers} 12710037SARM gem5 Developers 12810037SARM gem5 Developersint64_t 12910037SARM gem5 DevelopersArmStaticInst::extendReg64(uint64_t base, ArmExtendType type, 13010037SARM gem5 Developers uint64_t shiftAmt, uint8_t width) const 13110037SARM gem5 Developers{ 13210037SARM gem5 Developers bool sign_extend = false; 13310037SARM gem5 Developers int len = 0; 13410037SARM gem5 Developers switch (type) { 13510037SARM gem5 Developers case UXTB: 13610037SARM gem5 Developers len = 8; 13710037SARM gem5 Developers break; 13810037SARM gem5 Developers case UXTH: 13910037SARM gem5 Developers len = 16; 14010037SARM gem5 Developers break; 14110037SARM gem5 Developers case UXTW: 14210037SARM gem5 Developers len = 32; 14310037SARM gem5 Developers break; 14410037SARM gem5 Developers case UXTX: 14510037SARM gem5 Developers len = 64; 14610037SARM gem5 Developers break; 14710037SARM gem5 Developers case SXTB: 14810037SARM gem5 Developers len = 8; 14910037SARM gem5 Developers sign_extend = true; 15010037SARM gem5 Developers break; 15110037SARM gem5 Developers case SXTH: 15210037SARM gem5 Developers len = 16; 15310037SARM gem5 Developers sign_extend = true; 15410037SARM gem5 Developers break; 15510037SARM gem5 Developers case SXTW: 15610037SARM gem5 Developers len = 32; 15710037SARM gem5 Developers sign_extend = true; 15810037SARM gem5 Developers break; 15910037SARM gem5 Developers case SXTX: 16010037SARM gem5 Developers len = 64; 16110037SARM gem5 Developers sign_extend = true; 16210037SARM gem5 Developers break; 16310037SARM gem5 Developers } 16410037SARM gem5 Developers len = len <= width - shiftAmt ? len : width - shiftAmt; 16510037SARM gem5 Developers uint64_t tmp = (uint64_t) bits(base, len - 1, 0) << shiftAmt; 16610037SARM gem5 Developers if (sign_extend) { 16710037SARM gem5 Developers int sign_bit = bits(tmp, len + shiftAmt - 1); 16810037SARM gem5 Developers tmp = sign_bit ? (tmp | ~mask(len + shiftAmt)) : tmp; 16910037SARM gem5 Developers } 17010037SARM gem5 Developers return tmp & mask(width); 17110037SARM gem5 Developers} 17210037SARM gem5 Developers 1736254Sgblack@eecs.umich.edu// Shift Rm by Rs 1746254Sgblack@eecs.umich.eduint32_t 1757148Sgblack@eecs.umich.eduArmStaticInst::shift_rm_rs(uint32_t base, uint32_t shamt, 1767094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 1776254Sgblack@eecs.umich.edu{ 1786254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 1796254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 1806254Sgblack@eecs.umich.edu 1816254Sgblack@eecs.umich.edu switch (shiftType) 1826254Sgblack@eecs.umich.edu { 1836255Sgblack@eecs.umich.edu case LSL: 1846255Sgblack@eecs.umich.edu if (shamt >= 32) 1856255Sgblack@eecs.umich.edu return 0; 1866255Sgblack@eecs.umich.edu else 1876255Sgblack@eecs.umich.edu return base << shamt; 1886255Sgblack@eecs.umich.edu case LSR: 1896255Sgblack@eecs.umich.edu if (shamt >= 32) 1906255Sgblack@eecs.umich.edu return 0; 1916255Sgblack@eecs.umich.edu else 1926255Sgblack@eecs.umich.edu return base >> shamt; 1936255Sgblack@eecs.umich.edu case ASR: 1946255Sgblack@eecs.umich.edu if (shamt >= 32) 1957182Sgblack@eecs.umich.edu return (base >> 31) | -((base & (1 << 31)) >> 31); 1966255Sgblack@eecs.umich.edu else 1977182Sgblack@eecs.umich.edu return (base >> shamt) | -((base & (1 << 31)) >> shamt); 1986255Sgblack@eecs.umich.edu case ROR: 1996255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 2006255Sgblack@eecs.umich.edu if (shamt == 0) 2016255Sgblack@eecs.umich.edu return base; 2026255Sgblack@eecs.umich.edu else 2036255Sgblack@eecs.umich.edu return (base << (32 - shamt)) | (base >> shamt); 2046255Sgblack@eecs.umich.edu default: 2056712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 2066255Sgblack@eecs.umich.edu exit(1); 2076255Sgblack@eecs.umich.edu break; 2086254Sgblack@eecs.umich.edu } 2096254Sgblack@eecs.umich.edu return 0; 2106254Sgblack@eecs.umich.edu} 2116254Sgblack@eecs.umich.edu 2126254Sgblack@eecs.umich.edu 2136254Sgblack@eecs.umich.edu// Generate C for a shift by immediate 2146255Sgblack@eecs.umich.edubool 2157148Sgblack@eecs.umich.eduArmStaticInst::shift_carry_imm(uint32_t base, uint32_t shamt, 2167094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 2176254Sgblack@eecs.umich.edu{ 2186254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 2196254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 2206254Sgblack@eecs.umich.edu 2216254Sgblack@eecs.umich.edu switch (shiftType) 2226254Sgblack@eecs.umich.edu { 2236255Sgblack@eecs.umich.edu case LSL: 2246255Sgblack@eecs.umich.edu if (shamt == 0) 2256255Sgblack@eecs.umich.edu return cfval; 2266255Sgblack@eecs.umich.edu else 2276254Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 2286255Sgblack@eecs.umich.edu case LSR: 2296255Sgblack@eecs.umich.edu if (shamt == 0) 2306255Sgblack@eecs.umich.edu return (base >> 31); 2316255Sgblack@eecs.umich.edu else 2326255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2336255Sgblack@eecs.umich.edu case ASR: 2346255Sgblack@eecs.umich.edu if (shamt == 0) 2356255Sgblack@eecs.umich.edu return (base >> 31); 2366255Sgblack@eecs.umich.edu else 2376255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2386255Sgblack@eecs.umich.edu case ROR: 2396255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 2406255Sgblack@eecs.umich.edu if (shamt == 0) 2416255Sgblack@eecs.umich.edu return (base & 1); // RRX 2426255Sgblack@eecs.umich.edu else 2436255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2446255Sgblack@eecs.umich.edu default: 2456712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 2466255Sgblack@eecs.umich.edu exit(1); 2476255Sgblack@eecs.umich.edu break; 2486254Sgblack@eecs.umich.edu } 2496254Sgblack@eecs.umich.edu return 0; 2506254Sgblack@eecs.umich.edu} 2516254Sgblack@eecs.umich.edu 2526254Sgblack@eecs.umich.edu 2536254Sgblack@eecs.umich.edu// Generate C for a shift by Rs 2546255Sgblack@eecs.umich.edubool 2557148Sgblack@eecs.umich.eduArmStaticInst::shift_carry_rs(uint32_t base, uint32_t shamt, 2567094Sgblack@eecs.umich.edu uint32_t type, uint32_t cfval) const 2576254Sgblack@eecs.umich.edu{ 2586254Sgblack@eecs.umich.edu enum ArmShiftType shiftType; 2596254Sgblack@eecs.umich.edu shiftType = (enum ArmShiftType) type; 2606254Sgblack@eecs.umich.edu 2616255Sgblack@eecs.umich.edu if (shamt == 0) 2626255Sgblack@eecs.umich.edu return cfval; 2636255Sgblack@eecs.umich.edu 2646254Sgblack@eecs.umich.edu switch (shiftType) 2656254Sgblack@eecs.umich.edu { 2666255Sgblack@eecs.umich.edu case LSL: 2676255Sgblack@eecs.umich.edu if (shamt > 32) 2686255Sgblack@eecs.umich.edu return 0; 2696255Sgblack@eecs.umich.edu else 2706255Sgblack@eecs.umich.edu return (base >> (32 - shamt)) & 1; 2716255Sgblack@eecs.umich.edu case LSR: 2726255Sgblack@eecs.umich.edu if (shamt > 32) 2736255Sgblack@eecs.umich.edu return 0; 2746255Sgblack@eecs.umich.edu else 2756255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2766255Sgblack@eecs.umich.edu case ASR: 2776255Sgblack@eecs.umich.edu if (shamt > 32) 2786255Sgblack@eecs.umich.edu shamt = 32; 2796255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2806255Sgblack@eecs.umich.edu case ROR: 2816255Sgblack@eecs.umich.edu shamt = shamt & 0x1f; 2826255Sgblack@eecs.umich.edu if (shamt == 0) 2836255Sgblack@eecs.umich.edu shamt = 32; 2846255Sgblack@eecs.umich.edu return (base >> (shamt - 1)) & 1; 2856255Sgblack@eecs.umich.edu default: 2866712Snate@binkert.org ccprintf(std::cerr, "Unhandled shift type\n"); 2876255Sgblack@eecs.umich.edu exit(1); 2886255Sgblack@eecs.umich.edu break; 2896254Sgblack@eecs.umich.edu } 2906254Sgblack@eecs.umich.edu return 0; 2916254Sgblack@eecs.umich.edu} 2926254Sgblack@eecs.umich.edu 2936254Sgblack@eecs.umich.edu 2946254Sgblack@eecs.umich.eduvoid 2957148Sgblack@eecs.umich.eduArmStaticInst::printReg(std::ostream &os, int reg) const 2966253Sgblack@eecs.umich.edu{ 2979913Ssteve.reinhardt@amd.com RegIndex rel_reg; 2989913Ssteve.reinhardt@amd.com 2999913Ssteve.reinhardt@amd.com switch (regIdxToClass(reg, &rel_reg)) { 3009913Ssteve.reinhardt@amd.com case IntRegClass: 30110037SARM gem5 Developers if (aarch64) { 30210037SARM gem5 Developers if (reg == INTREG_UREG0) 30310037SARM gem5 Developers ccprintf(os, "ureg0"); 30410037SARM gem5 Developers else if (reg == INTREG_SPX) 30510037SARM gem5 Developers ccprintf(os, "%s%s", (intWidth == 32) ? "w" : "", "sp"); 30610037SARM gem5 Developers else if (reg == INTREG_X31) 30710037SARM gem5 Developers ccprintf(os, "%szr", (intWidth == 32) ? "w" : "x"); 30810037SARM gem5 Developers else 30910037SARM gem5 Developers ccprintf(os, "%s%d", (intWidth == 32) ? "w" : "x", reg); 31010037SARM gem5 Developers } else { 31110037SARM gem5 Developers switch (rel_reg) { 31210037SARM gem5 Developers case PCReg: 31310037SARM gem5 Developers ccprintf(os, "pc"); 31410037SARM gem5 Developers break; 31510037SARM gem5 Developers case StackPointerReg: 31610037SARM gem5 Developers ccprintf(os, "sp"); 31710037SARM gem5 Developers break; 31810037SARM gem5 Developers case FramePointerReg: 31910037SARM gem5 Developers ccprintf(os, "fp"); 32010037SARM gem5 Developers break; 32110037SARM gem5 Developers case ReturnAddressReg: 32210037SARM gem5 Developers ccprintf(os, "lr"); 32310037SARM gem5 Developers break; 32410037SARM gem5 Developers default: 32510037SARM gem5 Developers ccprintf(os, "r%d", reg); 32610037SARM gem5 Developers break; 32710037SARM gem5 Developers } 3286261Sgblack@eecs.umich.edu } 3299913Ssteve.reinhardt@amd.com break; 3309913Ssteve.reinhardt@amd.com case FloatRegClass: 3319913Ssteve.reinhardt@amd.com ccprintf(os, "f%d", rel_reg); 3329913Ssteve.reinhardt@amd.com break; 3339913Ssteve.reinhardt@amd.com case MiscRegClass: 3349913Ssteve.reinhardt@amd.com assert(rel_reg < NUM_MISCREGS); 3359913Ssteve.reinhardt@amd.com ccprintf(os, "%s", ArmISA::miscRegName[rel_reg]); 3369913Ssteve.reinhardt@amd.com break; 3379920Syasuko.eckert@amd.com case CCRegClass: 33810338SCurtis.Dunham@arm.com ccprintf(os, "cc_%s", ArmISA::ccRegName[rel_reg]); 33910338SCurtis.Dunham@arm.com break; 3406253Sgblack@eecs.umich.edu } 3416253Sgblack@eecs.umich.edu} 3426253Sgblack@eecs.umich.edu 3436262Sgblack@eecs.umich.eduvoid 3447148Sgblack@eecs.umich.eduArmStaticInst::printMnemonic(std::ostream &os, 3456262Sgblack@eecs.umich.edu const std::string &suffix, 34610037SARM gem5 Developers bool withPred, 34710037SARM gem5 Developers bool withCond64, 34810037SARM gem5 Developers ConditionCode cond64) const 3496262Sgblack@eecs.umich.edu{ 3506262Sgblack@eecs.umich.edu os << " " << mnemonic; 35110037SARM gem5 Developers if (withPred && !aarch64) { 35210037SARM gem5 Developers printCondition(os, machInst.condCode); 3537122Sgblack@eecs.umich.edu os << suffix; 35410037SARM gem5 Developers } else if (withCond64) { 35510037SARM gem5 Developers os << "."; 35610037SARM gem5 Developers printCondition(os, cond64); 35710037SARM gem5 Developers os << suffix; 35810037SARM gem5 Developers } 35910037SARM gem5 Developers if (machInst.bigThumb) 36010037SARM gem5 Developers os << ".w"; 36110037SARM gem5 Developers os << " "; 36210037SARM gem5 Developers} 36310037SARM gem5 Developers 36410037SARM gem5 Developersvoid 36510037SARM gem5 DevelopersArmStaticInst::printTarget(std::ostream &os, Addr target, 36610037SARM gem5 Developers const SymbolTable *symtab) const 36710037SARM gem5 Developers{ 36810037SARM gem5 Developers Addr symbolAddr; 36910037SARM gem5 Developers std::string symbol; 37010037SARM gem5 Developers 37110037SARM gem5 Developers if (symtab && symtab->findNearestSymbol(target, symbol, symbolAddr)) { 37210037SARM gem5 Developers ccprintf(os, "<%s", symbol); 37310037SARM gem5 Developers if (symbolAddr != target) 37410037SARM gem5 Developers ccprintf(os, "+%d>", target - symbolAddr); 37510037SARM gem5 Developers else 37610037SARM gem5 Developers ccprintf(os, ">"); 37710037SARM gem5 Developers } else { 37810037SARM gem5 Developers ccprintf(os, "%#x", target); 37910037SARM gem5 Developers } 38010037SARM gem5 Developers} 38110037SARM gem5 Developers 38210037SARM gem5 Developersvoid 38310037SARM gem5 DevelopersArmStaticInst::printCondition(std::ostream &os, 38410037SARM gem5 Developers unsigned code, 38510037SARM gem5 Developers bool noImplicit) const 38610037SARM gem5 Developers{ 38710037SARM gem5 Developers switch (code) { 38810037SARM gem5 Developers case COND_EQ: 38910037SARM gem5 Developers os << "eq"; 39010037SARM gem5 Developers break; 39110037SARM gem5 Developers case COND_NE: 39210037SARM gem5 Developers os << "ne"; 39310037SARM gem5 Developers break; 39410037SARM gem5 Developers case COND_CS: 39510037SARM gem5 Developers os << "cs"; 39610037SARM gem5 Developers break; 39710037SARM gem5 Developers case COND_CC: 39810037SARM gem5 Developers os << "cc"; 39910037SARM gem5 Developers break; 40010037SARM gem5 Developers case COND_MI: 40110037SARM gem5 Developers os << "mi"; 40210037SARM gem5 Developers break; 40310037SARM gem5 Developers case COND_PL: 40410037SARM gem5 Developers os << "pl"; 40510037SARM gem5 Developers break; 40610037SARM gem5 Developers case COND_VS: 40710037SARM gem5 Developers os << "vs"; 40810037SARM gem5 Developers break; 40910037SARM gem5 Developers case COND_VC: 41010037SARM gem5 Developers os << "vc"; 41110037SARM gem5 Developers break; 41210037SARM gem5 Developers case COND_HI: 41310037SARM gem5 Developers os << "hi"; 41410037SARM gem5 Developers break; 41510037SARM gem5 Developers case COND_LS: 41610037SARM gem5 Developers os << "ls"; 41710037SARM gem5 Developers break; 41810037SARM gem5 Developers case COND_GE: 41910037SARM gem5 Developers os << "ge"; 42010037SARM gem5 Developers break; 42110037SARM gem5 Developers case COND_LT: 42210037SARM gem5 Developers os << "lt"; 42310037SARM gem5 Developers break; 42410037SARM gem5 Developers case COND_GT: 42510037SARM gem5 Developers os << "gt"; 42610037SARM gem5 Developers break; 42710037SARM gem5 Developers case COND_LE: 42810037SARM gem5 Developers os << "le"; 42910037SARM gem5 Developers break; 43010037SARM gem5 Developers case COND_AL: 43110037SARM gem5 Developers // This one is implicit. 43210037SARM gem5 Developers if (noImplicit) 43310037SARM gem5 Developers os << "al"; 43410037SARM gem5 Developers break; 43510037SARM gem5 Developers case COND_UC: 43610037SARM gem5 Developers // Unconditional. 43710037SARM gem5 Developers if (noImplicit) 43810037SARM gem5 Developers os << "uc"; 43910037SARM gem5 Developers break; 44010037SARM gem5 Developers default: 44110037SARM gem5 Developers panic("Unrecognized condition code %d.\n", code); 4426262Sgblack@eecs.umich.edu } 4436262Sgblack@eecs.umich.edu} 4446262Sgblack@eecs.umich.edu 4456263Sgblack@eecs.umich.eduvoid 4467148Sgblack@eecs.umich.eduArmStaticInst::printMemSymbol(std::ostream &os, 4476263Sgblack@eecs.umich.edu const SymbolTable *symtab, 4486263Sgblack@eecs.umich.edu const std::string &prefix, 4496263Sgblack@eecs.umich.edu const Addr addr, 4506263Sgblack@eecs.umich.edu const std::string &suffix) const 4516263Sgblack@eecs.umich.edu{ 4526263Sgblack@eecs.umich.edu Addr symbolAddr; 4536263Sgblack@eecs.umich.edu std::string symbol; 4546263Sgblack@eecs.umich.edu if (symtab && symtab->findNearestSymbol(addr, symbol, symbolAddr)) { 4556263Sgblack@eecs.umich.edu ccprintf(os, "%s%s", prefix, symbol); 4566263Sgblack@eecs.umich.edu if (symbolAddr != addr) 4576263Sgblack@eecs.umich.edu ccprintf(os, "+%d", addr - symbolAddr); 4586263Sgblack@eecs.umich.edu ccprintf(os, suffix); 4596263Sgblack@eecs.umich.edu } 4606263Sgblack@eecs.umich.edu} 4616263Sgblack@eecs.umich.edu 4626264Sgblack@eecs.umich.eduvoid 4637148Sgblack@eecs.umich.eduArmStaticInst::printShiftOperand(std::ostream &os, 4647142Sgblack@eecs.umich.edu IntRegIndex rm, 4657142Sgblack@eecs.umich.edu bool immShift, 4667142Sgblack@eecs.umich.edu uint32_t shiftAmt, 4677142Sgblack@eecs.umich.edu IntRegIndex rs, 4687142Sgblack@eecs.umich.edu ArmShiftType type) const 4696264Sgblack@eecs.umich.edu{ 4707142Sgblack@eecs.umich.edu bool firstOp = false; 4716264Sgblack@eecs.umich.edu 4727142Sgblack@eecs.umich.edu if (rm != INTREG_ZERO) { 4737142Sgblack@eecs.umich.edu printReg(os, rm); 4747142Sgblack@eecs.umich.edu } 4757142Sgblack@eecs.umich.edu 4766306Sgblack@eecs.umich.edu bool done = false; 4776264Sgblack@eecs.umich.edu 4786306Sgblack@eecs.umich.edu if ((type == LSR || type == ASR) && immShift && shiftAmt == 0) 4796306Sgblack@eecs.umich.edu shiftAmt = 32; 4806264Sgblack@eecs.umich.edu 4816306Sgblack@eecs.umich.edu switch (type) { 4826306Sgblack@eecs.umich.edu case LSL: 4836306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 4846306Sgblack@eecs.umich.edu done = true; 4856264Sgblack@eecs.umich.edu break; 4866306Sgblack@eecs.umich.edu } 4877142Sgblack@eecs.umich.edu if (!firstOp) 4887142Sgblack@eecs.umich.edu os << ", "; 4897142Sgblack@eecs.umich.edu os << "LSL"; 4906306Sgblack@eecs.umich.edu break; 4916306Sgblack@eecs.umich.edu case LSR: 4927142Sgblack@eecs.umich.edu if (!firstOp) 4937142Sgblack@eecs.umich.edu os << ", "; 4947142Sgblack@eecs.umich.edu os << "LSR"; 4956306Sgblack@eecs.umich.edu break; 4966306Sgblack@eecs.umich.edu case ASR: 4977142Sgblack@eecs.umich.edu if (!firstOp) 4987142Sgblack@eecs.umich.edu os << ", "; 4997142Sgblack@eecs.umich.edu os << "ASR"; 5006306Sgblack@eecs.umich.edu break; 5016306Sgblack@eecs.umich.edu case ROR: 5026306Sgblack@eecs.umich.edu if (immShift && shiftAmt == 0) { 5037142Sgblack@eecs.umich.edu if (!firstOp) 5047142Sgblack@eecs.umich.edu os << ", "; 5057142Sgblack@eecs.umich.edu os << "RRX"; 5066306Sgblack@eecs.umich.edu done = true; 5076264Sgblack@eecs.umich.edu break; 5086264Sgblack@eecs.umich.edu } 5097142Sgblack@eecs.umich.edu if (!firstOp) 5107142Sgblack@eecs.umich.edu os << ", "; 5117142Sgblack@eecs.umich.edu os << "ROR"; 5126306Sgblack@eecs.umich.edu break; 5136306Sgblack@eecs.umich.edu default: 5146306Sgblack@eecs.umich.edu panic("Tried to disassemble unrecognized shift type.\n"); 5156306Sgblack@eecs.umich.edu } 5166306Sgblack@eecs.umich.edu if (!done) { 5177142Sgblack@eecs.umich.edu if (!firstOp) 5187142Sgblack@eecs.umich.edu os << " "; 5196306Sgblack@eecs.umich.edu if (immShift) 5206306Sgblack@eecs.umich.edu os << "#" << shiftAmt; 5216306Sgblack@eecs.umich.edu else 5227142Sgblack@eecs.umich.edu printReg(os, rs); 5236264Sgblack@eecs.umich.edu } 5246264Sgblack@eecs.umich.edu} 5256264Sgblack@eecs.umich.edu 5266264Sgblack@eecs.umich.eduvoid 52710037SARM gem5 DevelopersArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os, 52810037SARM gem5 Developers IntRegIndex rm, ArmExtendType type, 52910037SARM gem5 Developers int64_t shiftAmt) const 53010037SARM gem5 Developers{ 53110037SARM gem5 Developers if (!firstOperand) 53210037SARM gem5 Developers ccprintf(os, ", "); 53310037SARM gem5 Developers printReg(os, rm); 53410037SARM gem5 Developers if (type == UXTX && shiftAmt == 0) 53510037SARM gem5 Developers return; 53610037SARM gem5 Developers switch (type) { 53710037SARM gem5 Developers case UXTB: ccprintf(os, ", UXTB"); 53810037SARM gem5 Developers break; 53910037SARM gem5 Developers case UXTH: ccprintf(os, ", UXTH"); 54010037SARM gem5 Developers break; 54110037SARM gem5 Developers case UXTW: ccprintf(os, ", UXTW"); 54210037SARM gem5 Developers break; 54310037SARM gem5 Developers case UXTX: ccprintf(os, ", LSL"); 54410037SARM gem5 Developers break; 54510037SARM gem5 Developers case SXTB: ccprintf(os, ", SXTB"); 54610037SARM gem5 Developers break; 54710037SARM gem5 Developers case SXTH: ccprintf(os, ", SXTH"); 54810037SARM gem5 Developers break; 54910037SARM gem5 Developers case SXTW: ccprintf(os, ", SXTW"); 55010037SARM gem5 Developers break; 55110037SARM gem5 Developers case SXTX: ccprintf(os, ", SXTW"); 55210037SARM gem5 Developers break; 55310037SARM gem5 Developers } 55410037SARM gem5 Developers if (type == UXTX || shiftAmt) 55510037SARM gem5 Developers ccprintf(os, " #%d", shiftAmt); 55610037SARM gem5 Developers} 55710037SARM gem5 Developers 55810037SARM gem5 Developersvoid 5597148Sgblack@eecs.umich.eduArmStaticInst::printDataInst(std::ostream &os, bool withImm, 5607142Sgblack@eecs.umich.edu bool immShift, bool s, IntRegIndex rd, IntRegIndex rn, 5617142Sgblack@eecs.umich.edu IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt, 56211371Snathanael.premillieu@arm.com ArmShiftType type, uint64_t imm) const 5636264Sgblack@eecs.umich.edu{ 5647142Sgblack@eecs.umich.edu printMnemonic(os, s ? "s" : ""); 5656264Sgblack@eecs.umich.edu bool firstOp = true; 5666264Sgblack@eecs.umich.edu 5676264Sgblack@eecs.umich.edu // Destination 5687142Sgblack@eecs.umich.edu if (rd != INTREG_ZERO) { 5696264Sgblack@eecs.umich.edu firstOp = false; 5707142Sgblack@eecs.umich.edu printReg(os, rd); 5716264Sgblack@eecs.umich.edu } 5726264Sgblack@eecs.umich.edu 5736264Sgblack@eecs.umich.edu // Source 1. 5747142Sgblack@eecs.umich.edu if (rn != INTREG_ZERO) { 5756264Sgblack@eecs.umich.edu if (!firstOp) 5766264Sgblack@eecs.umich.edu os << ", "; 5776264Sgblack@eecs.umich.edu firstOp = false; 5787142Sgblack@eecs.umich.edu printReg(os, rn); 5796264Sgblack@eecs.umich.edu } 5806264Sgblack@eecs.umich.edu 5816264Sgblack@eecs.umich.edu if (!firstOp) 5826264Sgblack@eecs.umich.edu os << ", "; 5836306Sgblack@eecs.umich.edu if (withImm) { 58411371Snathanael.premillieu@arm.com ccprintf(os, "#%ld", imm); 5856306Sgblack@eecs.umich.edu } else { 5867142Sgblack@eecs.umich.edu printShiftOperand(os, rm, immShift, shiftAmt, rs, type); 5876306Sgblack@eecs.umich.edu } 5886264Sgblack@eecs.umich.edu} 5896264Sgblack@eecs.umich.edu 5906254Sgblack@eecs.umich.edustd::string 5917148Sgblack@eecs.umich.eduArmStaticInst::generateDisassembly(Addr pc, 5926254Sgblack@eecs.umich.edu const SymbolTable *symtab) const 5936253Sgblack@eecs.umich.edu{ 5946253Sgblack@eecs.umich.edu std::stringstream ss; 5956262Sgblack@eecs.umich.edu printMnemonic(ss); 5966253Sgblack@eecs.umich.edu return ss.str(); 5976253Sgblack@eecs.umich.edu} 5986253Sgblack@eecs.umich.edu} 599