pseudo.hh revision 12530
110611SAndreas.Sandberg@ARM.com/* 212530Sgiacomo.travaglini@arm.com * Copyright (c) 2014,2016,2018 ARM Limited 310611SAndreas.Sandberg@ARM.com * All rights reserved 410611SAndreas.Sandberg@ARM.com * 510611SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 610611SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 710611SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 810611SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 910611SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 1010611SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 1110611SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 1210611SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 1310611SAndreas.Sandberg@ARM.com * 1410696SAndreas.Sandberg@ARM.com * Copyright (c) 2007-2008 The Florida State University 1510696SAndreas.Sandberg@ARM.com * All rights reserved. 1610696SAndreas.Sandberg@ARM.com * 1710611SAndreas.Sandberg@ARM.com * Redistribution and use in source and binary forms, with or without 1810611SAndreas.Sandberg@ARM.com * modification, are permitted provided that the following conditions are 1910611SAndreas.Sandberg@ARM.com * met: redistributions of source code must retain the above copyright 2010611SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer; 2110611SAndreas.Sandberg@ARM.com * redistributions in binary form must reproduce the above copyright 2210611SAndreas.Sandberg@ARM.com * notice, this list of conditions and the following disclaimer in the 2310611SAndreas.Sandberg@ARM.com * documentation and/or other materials provided with the distribution; 2410611SAndreas.Sandberg@ARM.com * neither the name of the copyright holders nor the names of its 2510611SAndreas.Sandberg@ARM.com * contributors may be used to endorse or promote products derived from 2610611SAndreas.Sandberg@ARM.com * this software without specific prior written permission. 2710611SAndreas.Sandberg@ARM.com * 2810611SAndreas.Sandberg@ARM.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910611SAndreas.Sandberg@ARM.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010611SAndreas.Sandberg@ARM.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110611SAndreas.Sandberg@ARM.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210611SAndreas.Sandberg@ARM.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310611SAndreas.Sandberg@ARM.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410611SAndreas.Sandberg@ARM.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510611SAndreas.Sandberg@ARM.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610611SAndreas.Sandberg@ARM.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710611SAndreas.Sandberg@ARM.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810611SAndreas.Sandberg@ARM.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910611SAndreas.Sandberg@ARM.com * 4010611SAndreas.Sandberg@ARM.com * Authors: Andreas Sandberg 4110696SAndreas.Sandberg@ARM.com * Stephen Hines 4210611SAndreas.Sandberg@ARM.com */ 4310611SAndreas.Sandberg@ARM.com 4410611SAndreas.Sandberg@ARM.com#ifndef __ARCH_ARM_INSTS_PSEUDO_HH__ 4510611SAndreas.Sandberg@ARM.com#define __ARCH_ARM_INSTS_PSEUDO_HH__ 4610611SAndreas.Sandberg@ARM.com 4710611SAndreas.Sandberg@ARM.com#include "arch/arm/insts/static_inst.hh" 4810611SAndreas.Sandberg@ARM.com 4910611SAndreas.Sandberg@ARM.comclass DecoderFaultInst : public ArmStaticInst 5010611SAndreas.Sandberg@ARM.com{ 5110611SAndreas.Sandberg@ARM.com protected: 5210611SAndreas.Sandberg@ARM.com DecoderFault faultId; 5310611SAndreas.Sandberg@ARM.com 5410611SAndreas.Sandberg@ARM.com const char *faultName() const; 5510611SAndreas.Sandberg@ARM.com 5610611SAndreas.Sandberg@ARM.com public: 5710611SAndreas.Sandberg@ARM.com DecoderFaultInst(ExtMachInst _machInst); 5810611SAndreas.Sandberg@ARM.com 5910611SAndreas.Sandberg@ARM.com Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; 6010611SAndreas.Sandberg@ARM.com 6110611SAndreas.Sandberg@ARM.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 6210611SAndreas.Sandberg@ARM.com}; 6310611SAndreas.Sandberg@ARM.com 6410696SAndreas.Sandberg@ARM.com/** 6510696SAndreas.Sandberg@ARM.com * Static instruction class for unimplemented instructions that 6610696SAndreas.Sandberg@ARM.com * cause simulator termination. Note that these are recognized 6710696SAndreas.Sandberg@ARM.com * (legal) instructions that the simulator does not support; the 6810696SAndreas.Sandberg@ARM.com * 'Unknown' class is used for unrecognized/illegal instructions. 6910696SAndreas.Sandberg@ARM.com * This is a leaf class. 7010696SAndreas.Sandberg@ARM.com */ 7110696SAndreas.Sandberg@ARM.comclass FailUnimplemented : public ArmStaticInst 7210696SAndreas.Sandberg@ARM.com{ 7310696SAndreas.Sandberg@ARM.com private: 7410696SAndreas.Sandberg@ARM.com /// Full mnemonic for MRC and MCR instructions including the 7510696SAndreas.Sandberg@ARM.com /// coproc. register name 7610696SAndreas.Sandberg@ARM.com std::string fullMnemonic; 7710696SAndreas.Sandberg@ARM.com 7810696SAndreas.Sandberg@ARM.com public: 7910696SAndreas.Sandberg@ARM.com FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst); 8010696SAndreas.Sandberg@ARM.com FailUnimplemented(const char *_mnemonic, ExtMachInst _machInst, 8110696SAndreas.Sandberg@ARM.com const std::string& _fullMnemonic); 8210696SAndreas.Sandberg@ARM.com 8310696SAndreas.Sandberg@ARM.com Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; 8410696SAndreas.Sandberg@ARM.com 8510696SAndreas.Sandberg@ARM.com std::string 8610696SAndreas.Sandberg@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 8710696SAndreas.Sandberg@ARM.com}; 8810696SAndreas.Sandberg@ARM.com 8910696SAndreas.Sandberg@ARM.com/** 9010696SAndreas.Sandberg@ARM.com * Base class for unimplemented instructions that cause a warning 9110696SAndreas.Sandberg@ARM.com * to be printed (but do not terminate simulation). This 9210696SAndreas.Sandberg@ARM.com * implementation is a little screwy in that it will print a 9310696SAndreas.Sandberg@ARM.com * warning for each instance of a particular unimplemented machine 9410696SAndreas.Sandberg@ARM.com * instruction, not just for each unimplemented opcode. Should 9510696SAndreas.Sandberg@ARM.com * probably make the 'warned' flag a static member of the derived 9610696SAndreas.Sandberg@ARM.com * class. 9710696SAndreas.Sandberg@ARM.com */ 9810696SAndreas.Sandberg@ARM.comclass WarnUnimplemented : public ArmStaticInst 9910696SAndreas.Sandberg@ARM.com{ 10010696SAndreas.Sandberg@ARM.com private: 10110696SAndreas.Sandberg@ARM.com /// Have we warned on this instruction yet? 10210696SAndreas.Sandberg@ARM.com mutable bool warned; 10310696SAndreas.Sandberg@ARM.com /// Full mnemonic for MRC and MCR instructions including the 10410696SAndreas.Sandberg@ARM.com /// coproc. register name 10510696SAndreas.Sandberg@ARM.com std::string fullMnemonic; 10610696SAndreas.Sandberg@ARM.com 10710696SAndreas.Sandberg@ARM.com public: 10810696SAndreas.Sandberg@ARM.com WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst); 10910696SAndreas.Sandberg@ARM.com WarnUnimplemented(const char *_mnemonic, ExtMachInst _machInst, 11010696SAndreas.Sandberg@ARM.com const std::string& _fullMnemonic); 11110696SAndreas.Sandberg@ARM.com 11210696SAndreas.Sandberg@ARM.com Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; 11310696SAndreas.Sandberg@ARM.com 11410696SAndreas.Sandberg@ARM.com std::string 11510696SAndreas.Sandberg@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 11610696SAndreas.Sandberg@ARM.com}; 11710696SAndreas.Sandberg@ARM.com 11811572SDylan.Johnson@ARM.com/** 11911572SDylan.Johnson@ARM.com * Certain mrc/mcr instructions act as nops or flush the pipe based on what 12011572SDylan.Johnson@ARM.com * register the instruction is trying to access. This inst/class exists so that 12111572SDylan.Johnson@ARM.com * we can still check for hyp traps, as the normal nop instruction 12211572SDylan.Johnson@ARM.com * does not. 12311572SDylan.Johnson@ARM.com */ 12411572SDylan.Johnson@ARM.comclass McrMrcMiscInst : public ArmStaticInst 12510696SAndreas.Sandberg@ARM.com{ 12612530Sgiacomo.travaglini@arm.com protected: 12711572SDylan.Johnson@ARM.com uint64_t iss; 12811572SDylan.Johnson@ARM.com MiscRegIndex miscReg; 12911572SDylan.Johnson@ARM.com 13010696SAndreas.Sandberg@ARM.com public: 13111572SDylan.Johnson@ARM.com McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, 13211572SDylan.Johnson@ARM.com uint64_t _iss, MiscRegIndex _miscReg); 13310696SAndreas.Sandberg@ARM.com 13410696SAndreas.Sandberg@ARM.com Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; 13510696SAndreas.Sandberg@ARM.com 13610696SAndreas.Sandberg@ARM.com std::string 13710696SAndreas.Sandberg@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 13810696SAndreas.Sandberg@ARM.com 13910696SAndreas.Sandberg@ARM.com}; 14010696SAndreas.Sandberg@ARM.com 14112530Sgiacomo.travaglini@arm.com/** 14212530Sgiacomo.travaglini@arm.com * This class is also used for IMPLEMENTATION DEFINED registers, whose mcr/mrc 14312530Sgiacomo.travaglini@arm.com * behaviour is trappable even for unimplemented registers. 14412530Sgiacomo.travaglini@arm.com */ 14512530Sgiacomo.travaglini@arm.comclass McrMrcImplDefined : public McrMrcMiscInst 14612530Sgiacomo.travaglini@arm.com{ 14712530Sgiacomo.travaglini@arm.com public: 14812530Sgiacomo.travaglini@arm.com McrMrcImplDefined(const char *_mnemonic, ExtMachInst _machInst, 14912530Sgiacomo.travaglini@arm.com uint64_t _iss, MiscRegIndex _miscReg); 15012530Sgiacomo.travaglini@arm.com 15112530Sgiacomo.travaglini@arm.com Fault execute(ExecContext *xc, Trace::InstRecord *traceData) const; 15212530Sgiacomo.travaglini@arm.com 15312530Sgiacomo.travaglini@arm.com std::string 15412530Sgiacomo.travaglini@arm.com generateDisassembly(Addr pc, const SymbolTable *symtab) const; 15512530Sgiacomo.travaglini@arm.com 15612530Sgiacomo.travaglini@arm.com}; 15712530Sgiacomo.travaglini@arm.com 15810611SAndreas.Sandberg@ARM.com#endif 159