pseudo.cc revision 11572:9eac6e12c673
1/* 2 * Copyright (c) 2014,2016 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Andreas Sandberg 41 * Stephen Hines 42 */ 43 44#include "arch/arm/insts/pseudo.hh" 45#include "cpu/exec_context.hh" 46 47DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst) 48 : ArmStaticInst("gem5decoderFault", _machInst, No_OpClass), 49 faultId(static_cast<DecoderFault>( 50 static_cast<uint8_t>(_machInst.decoderFault))) 51{ 52 // Don't call execute() if we're on a speculative path and the 53 // fault is an internal panic fault. 54 flags[IsNonSpeculative] = (faultId == DecoderFault::PANIC); 55} 56 57Fault 58DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const 59{ 60 const PCState pc_state(xc->pcState()); 61 const Addr pc(pc_state.instAddr()); 62 63 switch (faultId) { 64 case DecoderFault::UNALIGNED: 65 if (machInst.aarch64) { 66 return std::make_shared<PCAlignmentFault>(pc); 67 } else { 68 // TODO: We should check if we the receiving end is in 69 // aarch64 mode and raise a PCAlignment fault instead. 70 return std::make_shared<PrefetchAbort>( 71 pc, ArmFault::AlignmentFault); 72 } 73 74 case DecoderFault::PANIC: 75 panic("Internal error in instruction decoder\n"); 76 77 case DecoderFault::OK: 78 panic("Decoder fault instruction without decoder fault.\n"); 79 } 80 81 panic("Unhandled fault type"); 82} 83 84const char * 85DecoderFaultInst::faultName() const 86{ 87 switch (faultId) { 88 case DecoderFault::OK: 89 return "OK"; 90 91 case DecoderFault::UNALIGNED: 92 return "UnalignedInstruction"; 93 94 case DecoderFault::PANIC: 95 return "DecoderPanic"; 96 } 97 98 panic("Unhandled fault type"); 99} 100 101std::string 102DecoderFaultInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 103{ 104 return csprintf("gem5fault %s", faultName()); 105} 106 107 108 109FailUnimplemented::FailUnimplemented(const char *_mnemonic, 110 ExtMachInst _machInst) 111 : ArmStaticInst(_mnemonic, _machInst, No_OpClass) 112{ 113 // don't call execute() (which panics) if we're on a 114 // speculative path 115 flags[IsNonSpeculative] = true; 116} 117 118FailUnimplemented::FailUnimplemented(const char *_mnemonic, 119 ExtMachInst _machInst, 120 const std::string& _fullMnemonic) 121 : ArmStaticInst(_mnemonic, _machInst, No_OpClass), 122 fullMnemonic(_fullMnemonic) 123{ 124 // don't call execute() (which panics) if we're on a 125 // speculative path 126 flags[IsNonSpeculative] = true; 127} 128 129Fault 130FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const 131{ 132 return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic); 133} 134 135std::string 136FailUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const 137{ 138 return csprintf("%-10s (unimplemented)", 139 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); 140} 141 142 143 144WarnUnimplemented::WarnUnimplemented(const char *_mnemonic, 145 ExtMachInst _machInst) 146 : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false) 147{ 148 // don't call execute() (which panics) if we're on a 149 // speculative path 150 flags[IsNonSpeculative] = true; 151} 152 153WarnUnimplemented::WarnUnimplemented(const char *_mnemonic, 154 ExtMachInst _machInst, 155 const std::string& _fullMnemonic) 156 : ArmStaticInst(_mnemonic, _machInst, No_OpClass), warned(false), 157 fullMnemonic(_fullMnemonic) 158{ 159 // don't call execute() (which panics) if we're on a 160 // speculative path 161 flags[IsNonSpeculative] = true; 162} 163 164Fault 165WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const 166{ 167 if (!warned) { 168 warn("\tinstruction '%s' unimplemented\n", 169 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); 170 warned = true; 171 } 172 173 return NoFault; 174} 175 176std::string 177WarnUnimplemented::generateDisassembly(Addr pc, const SymbolTable *symtab) const 178{ 179 return csprintf("%-10s (unimplemented)", 180 fullMnemonic.size() ? fullMnemonic.c_str() : mnemonic); 181} 182 183 184 185McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst, 186 uint64_t _iss, MiscRegIndex _miscReg) 187 : ArmStaticInst(_mnemonic, _machInst, No_OpClass) 188{ 189 flags[IsNonSpeculative] = true; 190 iss = _iss; 191 miscReg = _miscReg; 192} 193 194Fault 195McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const 196{ 197 uint32_t cpsr = xc->readMiscReg(MISCREG_CPSR); 198 uint32_t hcr = xc->readMiscReg(MISCREG_HCR); 199 uint32_t scr = xc->readMiscReg(MISCREG_SCR); 200 uint32_t hdcr = xc->readMiscReg(MISCREG_HDCR); 201 uint32_t hstr = xc->readMiscReg(MISCREG_HSTR); 202 uint32_t hcptr = xc->readMiscReg(MISCREG_HCPTR); 203 204 bool hypTrap = mcrMrc15TrapToHyp(miscReg, hcr, cpsr, scr, hdcr, hstr, 205 hcptr, iss); 206 if (hypTrap) { 207 return std::make_shared<HypervisorTrap>(machInst, iss, 208 EC_TRAPPED_CP15_MCR_MRC); 209 } 210 211 if (miscReg == MISCREG_DCCMVAC) 212 return std::make_shared<FlushPipe>(); 213 else 214 return NoFault; 215} 216 217std::string 218McrMrcMiscInst::generateDisassembly(Addr pc, const SymbolTable *symtab) const 219{ 220 return csprintf("%-10s (pipe flush)", mnemonic); 221} 222