pred_inst.hh revision 7329:ed9a9d20bc27
110249Sstephan.diestelhorst@arm.com/* 210249Sstephan.diestelhorst@arm.com * Copyright (c) 2010 ARM Limited 310249Sstephan.diestelhorst@arm.com * All rights reserved 410249Sstephan.diestelhorst@arm.com * 510249Sstephan.diestelhorst@arm.com * The license below extends only to copyright in the software and shall 610249Sstephan.diestelhorst@arm.com * not be construed as granting a license to any other intellectual 710249Sstephan.diestelhorst@arm.com * property including but not limited to intellectual property relating 810249Sstephan.diestelhorst@arm.com * to a hardware implementation of the functionality of the software 910249Sstephan.diestelhorst@arm.com * licensed hereunder. You may use the software subject to the license 1010249Sstephan.diestelhorst@arm.com * terms below provided that you ensure that this notice is replicated 1110249Sstephan.diestelhorst@arm.com * unmodified and in its entirety in all distributions of the software, 1210249Sstephan.diestelhorst@arm.com * modified or unmodified, in source code or in binary form. 1310249Sstephan.diestelhorst@arm.com * 1410249Sstephan.diestelhorst@arm.com * Copyright (c) 2007-2008 The Florida State University 1510249Sstephan.diestelhorst@arm.com * All rights reserved. 1610249Sstephan.diestelhorst@arm.com * 1710249Sstephan.diestelhorst@arm.com * Redistribution and use in source and binary forms, with or without 1810249Sstephan.diestelhorst@arm.com * modification, are permitted provided that the following conditions are 1910249Sstephan.diestelhorst@arm.com * met: redistributions of source code must retain the above copyright 2010249Sstephan.diestelhorst@arm.com * notice, this list of conditions and the following disclaimer; 2110249Sstephan.diestelhorst@arm.com * redistributions in binary form must reproduce the above copyright 2210249Sstephan.diestelhorst@arm.com * notice, this list of conditions and the following disclaimer in the 2310249Sstephan.diestelhorst@arm.com * documentation and/or other materials provided with the distribution; 2410249Sstephan.diestelhorst@arm.com * neither the name of the copyright holders nor the names of its 2510249Sstephan.diestelhorst@arm.com * contributors may be used to endorse or promote products derived from 2610249Sstephan.diestelhorst@arm.com * this software without specific prior written permission. 2710249Sstephan.diestelhorst@arm.com * 2810249Sstephan.diestelhorst@arm.com * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2910249Sstephan.diestelhorst@arm.com * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 3010249Sstephan.diestelhorst@arm.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 3110249Sstephan.diestelhorst@arm.com * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 3210249Sstephan.diestelhorst@arm.com * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3310249Sstephan.diestelhorst@arm.com * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3410249Sstephan.diestelhorst@arm.com * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3510249Sstephan.diestelhorst@arm.com * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3610249Sstephan.diestelhorst@arm.com * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3710249Sstephan.diestelhorst@arm.com * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3810249Sstephan.diestelhorst@arm.com * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3910249Sstephan.diestelhorst@arm.com * 4010249Sstephan.diestelhorst@arm.com * Authors: Stephen Hines 4110249Sstephan.diestelhorst@arm.com */ 4210249Sstephan.diestelhorst@arm.com#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 4310249Sstephan.diestelhorst@arm.com#define __ARCH_ARM_INSTS_PREDINST_HH__ 4410249Sstephan.diestelhorst@arm.com 4510249Sstephan.diestelhorst@arm.com#include "arch/arm/insts/static_inst.hh" 4610249Sstephan.diestelhorst@arm.com#include "base/trace.hh" 4710249Sstephan.diestelhorst@arm.com 4810249Sstephan.diestelhorst@arm.comnamespace ArmISA 4910249Sstephan.diestelhorst@arm.com{ 5010249Sstephan.diestelhorst@arm.comstatic inline uint32_t 5110249Sstephan.diestelhorst@arm.comrotate_imm(uint32_t immValue, int rotateValue) 5210249Sstephan.diestelhorst@arm.com{ 5310249Sstephan.diestelhorst@arm.com return ((immValue >> (rotateValue & 31)) | 5410249Sstephan.diestelhorst@arm.com (immValue << (32 - (rotateValue & 31)))); 5510249Sstephan.diestelhorst@arm.com} 5610249Sstephan.diestelhorst@arm.com 5710249Sstephan.diestelhorst@arm.comstatic inline uint32_t 5810249Sstephan.diestelhorst@arm.commodified_imm(uint8_t ctrlImm, uint8_t dataImm) 5910249Sstephan.diestelhorst@arm.com{ 6010249Sstephan.diestelhorst@arm.com uint32_t bigData = dataImm; 6110249Sstephan.diestelhorst@arm.com uint32_t bigCtrl = ctrlImm; 6210249Sstephan.diestelhorst@arm.com if (bigCtrl < 4) { 6310249Sstephan.diestelhorst@arm.com switch (bigCtrl) { 6410249Sstephan.diestelhorst@arm.com case 0: 6510249Sstephan.diestelhorst@arm.com return bigData; 6610249Sstephan.diestelhorst@arm.com case 1: 6710249Sstephan.diestelhorst@arm.com return bigData | (bigData << 16); 6810249Sstephan.diestelhorst@arm.com case 2: 6910249Sstephan.diestelhorst@arm.com return (bigData << 8) | (bigData << 24); 7010249Sstephan.diestelhorst@arm.com case 3: 7110249Sstephan.diestelhorst@arm.com return (bigData << 0) | (bigData << 8) | 7210249Sstephan.diestelhorst@arm.com (bigData << 16) | (bigData << 24); 7310249Sstephan.diestelhorst@arm.com } 7410249Sstephan.diestelhorst@arm.com } 7510249Sstephan.diestelhorst@arm.com bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1); 7610249Sstephan.diestelhorst@arm.com bigData |= (1 << 7); 7710249Sstephan.diestelhorst@arm.com return bigData << (32 - bigCtrl); 7810249Sstephan.diestelhorst@arm.com} 7910249Sstephan.diestelhorst@arm.com 8010249Sstephan.diestelhorst@arm.comstatic inline uint64_t 8110249Sstephan.diestelhorst@arm.comsimd_modified_imm(bool op, uint8_t cmode, uint8_t data) 8210249Sstephan.diestelhorst@arm.com{ 8310249Sstephan.diestelhorst@arm.com uint64_t bigData = data; 8410395Sstephan.diestelhorst@arm.com switch (cmode) { 8510395Sstephan.diestelhorst@arm.com case 0x0: 8610395Sstephan.diestelhorst@arm.com case 0x1: 8710249Sstephan.diestelhorst@arm.com bigData = (bigData << 0) | (bigData << 32); 8810249Sstephan.diestelhorst@arm.com break; 8910249Sstephan.diestelhorst@arm.com case 0x2: 9010249Sstephan.diestelhorst@arm.com case 0x3: 9110249Sstephan.diestelhorst@arm.com bigData = (bigData << 8) | (bigData << 40); 9210249Sstephan.diestelhorst@arm.com break; 9310395Sstephan.diestelhorst@arm.com case 0x4: 9410395Sstephan.diestelhorst@arm.com case 0x5: 9510395Sstephan.diestelhorst@arm.com bigData = (bigData << 16) | (bigData << 48); 9610395Sstephan.diestelhorst@arm.com break; 9710395Sstephan.diestelhorst@arm.com case 0x6: 9810395Sstephan.diestelhorst@arm.com case 0x7: 9910395Sstephan.diestelhorst@arm.com bigData = (bigData << 24) | (bigData << 56); 10010395Sstephan.diestelhorst@arm.com break; 10110395Sstephan.diestelhorst@arm.com case 0x8: 10210395Sstephan.diestelhorst@arm.com case 0x9: 10310395Sstephan.diestelhorst@arm.com bigData = (bigData << 0) | (bigData << 16) | 10410249Sstephan.diestelhorst@arm.com (bigData << 32) | (bigData << 48); 10510249Sstephan.diestelhorst@arm.com break; 10610249Sstephan.diestelhorst@arm.com case 0xa: 10710249Sstephan.diestelhorst@arm.com case 0xb: 10810249Sstephan.diestelhorst@arm.com bigData = (bigData << 8) | (bigData << 24) | 10910249Sstephan.diestelhorst@arm.com (bigData << 40) | (bigData << 56); 11010249Sstephan.diestelhorst@arm.com break; 11110249Sstephan.diestelhorst@arm.com case 0xc: 11210249Sstephan.diestelhorst@arm.com bigData = (0xffULL << 0) | (bigData << 8) | 11310249Sstephan.diestelhorst@arm.com (0xffULL << 32) | (bigData << 40); 11410249Sstephan.diestelhorst@arm.com break; 11510249Sstephan.diestelhorst@arm.com case 0xd: 11610249Sstephan.diestelhorst@arm.com bigData = (0xffffULL << 0) | (bigData << 16) | 11710249Sstephan.diestelhorst@arm.com (0xffffULL << 32) | (bigData << 48); 11810249Sstephan.diestelhorst@arm.com break; 11910249Sstephan.diestelhorst@arm.com case 0xe: 12010249Sstephan.diestelhorst@arm.com if (op) { 12110249Sstephan.diestelhorst@arm.com bigData = (bigData << 0) | (bigData << 8) | 12210249Sstephan.diestelhorst@arm.com (bigData << 16) | (bigData << 24) | 12310249Sstephan.diestelhorst@arm.com (bigData << 32) | (bigData << 40) | 12410249Sstephan.diestelhorst@arm.com (bigData << 48) | (bigData << 56); 12510249Sstephan.diestelhorst@arm.com } else { 12610249Sstephan.diestelhorst@arm.com bigData = 0; 12710249Sstephan.diestelhorst@arm.com for (int i = 7; i >= 0; i--) { 12810249Sstephan.diestelhorst@arm.com if (bits(data, i)) { 12910249Sstephan.diestelhorst@arm.com bigData |= (0xFF << (i * 8)); 13010249Sstephan.diestelhorst@arm.com } 13110249Sstephan.diestelhorst@arm.com } 13210249Sstephan.diestelhorst@arm.com } 13310249Sstephan.diestelhorst@arm.com case 0xf: 13410249Sstephan.diestelhorst@arm.com if (!op) { 13510249Sstephan.diestelhorst@arm.com uint64_t bVal = bits(bigData, 6) ? (0x1F) : (0x20); 13610249Sstephan.diestelhorst@arm.com bigData = (bits(bigData, 5, 0) << 19) | 13710249Sstephan.diestelhorst@arm.com (bVal << 25) | (bits(bigData, 7) << 31); 13810249Sstephan.diestelhorst@arm.com bigData |= (bigData << 32); 13910249Sstephan.diestelhorst@arm.com } 14010249Sstephan.diestelhorst@arm.com // Fall through 14110249Sstephan.diestelhorst@arm.com default: 14210249Sstephan.diestelhorst@arm.com panic("Illegal modified SIMD immediate parameters.\n"); 14310249Sstephan.diestelhorst@arm.com } 14410249Sstephan.diestelhorst@arm.com return bigData; 14510249Sstephan.diestelhorst@arm.com} 14610249Sstephan.diestelhorst@arm.com 14710249Sstephan.diestelhorst@arm.comstatic inline uint64_t 14810249Sstephan.diestelhorst@arm.comvfp_modified_imm(uint8_t data, bool wide) 14910249Sstephan.diestelhorst@arm.com{ 15010249Sstephan.diestelhorst@arm.com uint64_t bigData = data; 15110249Sstephan.diestelhorst@arm.com uint64_t repData; 15210249Sstephan.diestelhorst@arm.com if (wide) { 15310249Sstephan.diestelhorst@arm.com repData = bits(data, 6) ? 0xFF : 0; 15410249Sstephan.diestelhorst@arm.com bigData = (bits(bigData, 5, 0) << 48) | 15510249Sstephan.diestelhorst@arm.com (repData << 54) | (bits(~bigData, 6) << 62) | 15610249Sstephan.diestelhorst@arm.com (bits(bigData, 7) << 63); 15710249Sstephan.diestelhorst@arm.com } else { 15810249Sstephan.diestelhorst@arm.com repData = bits(data, 6) ? 0x1F : 0; 15910249Sstephan.diestelhorst@arm.com bigData = (bits(bigData, 5, 0) << 19) | 16010249Sstephan.diestelhorst@arm.com (repData << 25) | (bits(~bigData, 6) << 30) | 16110249Sstephan.diestelhorst@arm.com (bits(bigData, 7) << 31); 16210249Sstephan.diestelhorst@arm.com } 16310249Sstephan.diestelhorst@arm.com return bigData; 16410249Sstephan.diestelhorst@arm.com} 16510249Sstephan.diestelhorst@arm.com 16610249Sstephan.diestelhorst@arm.com 16710249Sstephan.diestelhorst@arm.com/** 16810249Sstephan.diestelhorst@arm.com * Base class for predicated integer operations. 16910249Sstephan.diestelhorst@arm.com */ 17010249Sstephan.diestelhorst@arm.comclass PredOp : public ArmStaticInst 17110249Sstephan.diestelhorst@arm.com{ 17210249Sstephan.diestelhorst@arm.com protected: 17310905Sandreas.sandberg@arm.com 17410249Sstephan.diestelhorst@arm.com ConditionCode condCode; 17510249Sstephan.diestelhorst@arm.com 17610249Sstephan.diestelhorst@arm.com /// Constructor 17710249Sstephan.diestelhorst@arm.com PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 17810249Sstephan.diestelhorst@arm.com ArmStaticInst(mnem, _machInst, __opClass), 17910249Sstephan.diestelhorst@arm.com condCode((ConditionCode)(unsigned)machInst.condCode) 18010249Sstephan.diestelhorst@arm.com { 18110249Sstephan.diestelhorst@arm.com } 18210249Sstephan.diestelhorst@arm.com}; 18310249Sstephan.diestelhorst@arm.com 18410249Sstephan.diestelhorst@arm.com/** 18510905Sandreas.sandberg@arm.com * Base class for predicated immediate operations. 18610905Sandreas.sandberg@arm.com */ 18710905Sandreas.sandberg@arm.comclass PredImmOp : public PredOp 18810249Sstephan.diestelhorst@arm.com{ 18910249Sstephan.diestelhorst@arm.com protected: 19010249Sstephan.diestelhorst@arm.com 19110249Sstephan.diestelhorst@arm.com uint32_t imm; 19210249Sstephan.diestelhorst@arm.com uint32_t rotated_imm; 19310249Sstephan.diestelhorst@arm.com uint32_t rotated_carry; 19410905Sandreas.sandberg@arm.com uint32_t rotate; 19510905Sandreas.sandberg@arm.com 19610905Sandreas.sandberg@arm.com /// Constructor 19710249Sstephan.diestelhorst@arm.com PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 19810249Sstephan.diestelhorst@arm.com PredOp(mnem, _machInst, __opClass), 19910249Sstephan.diestelhorst@arm.com imm(machInst.imm), rotated_imm(0), rotated_carry(0), 20010905Sandreas.sandberg@arm.com rotate(machInst.rotate << 1) 20110249Sstephan.diestelhorst@arm.com { 20210395Sstephan.diestelhorst@arm.com rotated_imm = rotate_imm(imm, rotate); 20310395Sstephan.diestelhorst@arm.com if (rotate != 0) 20410249Sstephan.diestelhorst@arm.com rotated_carry = bits(rotated_imm, 31); 20510249Sstephan.diestelhorst@arm.com } 20610395Sstephan.diestelhorst@arm.com 20710395Sstephan.diestelhorst@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 20810395Sstephan.diestelhorst@arm.com}; 20910395Sstephan.diestelhorst@arm.com 21010395Sstephan.diestelhorst@arm.com/** 21110249Sstephan.diestelhorst@arm.com * Base class for predicated integer operations. 21210249Sstephan.diestelhorst@arm.com */ 21310249Sstephan.diestelhorst@arm.comclass PredIntOp : public PredOp 21410249Sstephan.diestelhorst@arm.com{ 21510905Sandreas.sandberg@arm.com protected: 21610905Sandreas.sandberg@arm.com 21710905Sandreas.sandberg@arm.com uint32_t shift_size; 21810249Sstephan.diestelhorst@arm.com uint32_t shift; 21910249Sstephan.diestelhorst@arm.com 22010249Sstephan.diestelhorst@arm.com /// Constructor 22110249Sstephan.diestelhorst@arm.com PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 22210249Sstephan.diestelhorst@arm.com PredOp(mnem, _machInst, __opClass), 22310249Sstephan.diestelhorst@arm.com shift_size(machInst.shiftSize), shift(machInst.shift) 22410249Sstephan.diestelhorst@arm.com { 22510249Sstephan.diestelhorst@arm.com } 22610249Sstephan.diestelhorst@arm.com 22710249Sstephan.diestelhorst@arm.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 22810249Sstephan.diestelhorst@arm.com}; 22910249Sstephan.diestelhorst@arm.com 23010249Sstephan.diestelhorst@arm.comclass DataImmOp : public PredOp 23110249Sstephan.diestelhorst@arm.com{ 23210249Sstephan.diestelhorst@arm.com protected: 23310249Sstephan.diestelhorst@arm.com IntRegIndex dest, op1; 23410249Sstephan.diestelhorst@arm.com uint32_t imm; 23510249Sstephan.diestelhorst@arm.com // Whether the carry flag should be modified if that's an option for 23610249Sstephan.diestelhorst@arm.com // this instruction. 237 bool rotC; 238 239 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 240 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 241 PredOp(mnem, _machInst, __opClass), 242 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 243 {} 244 245 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 246}; 247 248class DataRegOp : public PredOp 249{ 250 protected: 251 IntRegIndex dest, op1, op2; 252 int32_t shiftAmt; 253 ArmShiftType shiftType; 254 255 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 256 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 257 int32_t _shiftAmt, ArmShiftType _shiftType) : 258 PredOp(mnem, _machInst, __opClass), 259 dest(_dest), op1(_op1), op2(_op2), 260 shiftAmt(_shiftAmt), shiftType(_shiftType) 261 {} 262 263 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 264}; 265 266class DataRegRegOp : public PredOp 267{ 268 protected: 269 IntRegIndex dest, op1, op2, shift; 270 ArmShiftType shiftType; 271 272 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 273 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 274 IntRegIndex _shift, ArmShiftType _shiftType) : 275 PredOp(mnem, _machInst, __opClass), 276 dest(_dest), op1(_op1), op2(_op2), shift(_shift), 277 shiftType(_shiftType) 278 {} 279 280 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 281}; 282 283/** 284 * Base class for predicated macro-operations. 285 */ 286class PredMacroOp : public PredOp 287{ 288 protected: 289 290 uint32_t numMicroops; 291 StaticInstPtr * microOps; 292 293 /// Constructor 294 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 295 PredOp(mnem, _machInst, __opClass), 296 numMicroops(0) 297 { 298 // We rely on the subclasses of this object to handle the 299 // initialization of the micro-operations, since they are 300 // all of variable length 301 flags[IsMacroop] = true; 302 } 303 304 ~PredMacroOp() 305 { 306 if (numMicroops) 307 delete [] microOps; 308 } 309 310 StaticInstPtr 311 fetchMicroop(MicroPC microPC) 312 { 313 assert(microPC < numMicroops); 314 return microOps[microPC]; 315 } 316 317 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 318}; 319 320/** 321 * Base class for predicated micro-operations. 322 */ 323class PredMicroop : public PredOp 324{ 325 /// Constructor 326 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 327 PredOp(mnem, _machInst, __opClass) 328 { 329 flags[IsMicroop] = true; 330 } 331}; 332} 333 334#endif //__ARCH_ARM_INSTS_PREDINST_HH__ 335