pred_inst.hh revision 7328:f45289e4f2f4
16899SN/A/* 26899SN/A * Copyright (c) 2010 ARM Limited 36899SN/A * All rights reserved 46899SN/A * 56899SN/A * The license below extends only to copyright in the software and shall 66899SN/A * not be construed as granting a license to any other intellectual 76899SN/A * property including but not limited to intellectual property relating 86899SN/A * to a hardware implementation of the functionality of the software 96899SN/A * licensed hereunder. You may use the software subject to the license 106899SN/A * terms below provided that you ensure that this notice is replicated 116899SN/A * unmodified and in its entirety in all distributions of the software, 126899SN/A * modified or unmodified, in source code or in binary form. 136899SN/A * 146899SN/A * Copyright (c) 2007-2008 The Florida State University 156899SN/A * All rights reserved. 166899SN/A * 176899SN/A * Redistribution and use in source and binary forms, with or without 186899SN/A * modification, are permitted provided that the following conditions are 196899SN/A * met: redistributions of source code must retain the above copyright 206899SN/A * notice, this list of conditions and the following disclaimer; 216899SN/A * redistributions in binary form must reproduce the above copyright 226899SN/A * notice, this list of conditions and the following disclaimer in the 236899SN/A * documentation and/or other materials provided with the distribution; 246899SN/A * neither the name of the copyright holders nor the names of its 256899SN/A * contributors may be used to endorse or promote products derived from 266899SN/A * this software without specific prior written permission. 276899SN/A * 286899SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296899SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 307632SBrad.Beckmann@amd.com * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 318232Snate@binkert.org * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 327053SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336899SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346899SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356899SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367053SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 377053SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387053SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 398932SBrad.Beckmann@amd.com * 408932SBrad.Beckmann@amd.com * Authors: Stephen Hines 418932SBrad.Beckmann@amd.com */ 426899SN/A#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 437053SN/A#define __ARCH_ARM_INSTS_PREDINST_HH__ 446899SN/A 457053SN/A#include "arch/arm/insts/static_inst.hh" 467053SN/A#include "base/trace.hh" 477053SN/A 487053SN/Anamespace ArmISA 498164Snilay@cs.wisc.edu{ 507053SN/Astatic inline uint32_t 516899SN/Arotate_imm(uint32_t immValue, int rotateValue) 526899SN/A{ 537053SN/A return ((immValue >> (rotateValue & 31)) | 547053SN/A (immValue << (32 - (rotateValue & 31)))); 556899SN/A} 567053SN/A 577053SN/Astatic inline uint32_t 586899SN/Amodified_imm(uint8_t ctrlImm, uint8_t dataImm) 597053SN/A{ 607053SN/A uint32_t bigData = dataImm; 617053SN/A uint32_t bigCtrl = ctrlImm; 627053SN/A if (bigCtrl < 4) { 636899SN/A switch (bigCtrl) { 648184Ssomayeh@cs.wisc.edu case 0: 658184Ssomayeh@cs.wisc.edu return bigData; 668184Ssomayeh@cs.wisc.edu case 1: 678184Ssomayeh@cs.wisc.edu return bigData | (bigData << 16); 687053SN/A case 2: 697053SN/A return (bigData << 8) | (bigData << 24); 707053SN/A case 3: 717053SN/A return (bigData << 0) | (bigData << 8) | 727053SN/A (bigData << 16) | (bigData << 24); 737053SN/A } 747053SN/A } 757053SN/A bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1); 767053SN/A bigData |= (1 << 7); 776899SN/A return bigData << (32 - bigCtrl); 786899SN/A} 797053SN/A 807053SN/Astatic inline uint64_t 816899SN/Asimd_modified_imm(bool op, uint8_t cmode, uint8_t data) 827053SN/A{ 836899SN/A uint64_t bigData = data; 848932SBrad.Beckmann@amd.com switch (cmode) { 858950Sandreas.hansson@arm.com case 0x0: 866899SN/A case 0x1: 877053SN/A bigData = (bigData << 0) | (bigData << 32); 887053SN/A break; 896899SN/A case 0x2: 907053SN/A case 0x3: 916899SN/A bigData = (bigData << 8) | (bigData << 40); 927053SN/A break; 937053SN/A case 0x4: 947053SN/A case 0x5: 957053SN/A bigData = (bigData << 16) | (bigData << 48); 968932SBrad.Beckmann@amd.com break; 978950Sandreas.hansson@arm.com case 0x6: 987053SN/A case 0x7: 997053SN/A bigData = (bigData << 24) | (bigData << 56); 1007053SN/A break; 1017053SN/A case 0x8: 1027053SN/A case 0x9: 1036899SN/A bigData = (bigData << 0) | (bigData << 16) | 1046899SN/A (bigData << 32) | (bigData << 48); 1057568SN/A break; 1068832SAli.Saidi@ARM.com case 0xa: 1078832SAli.Saidi@ARM.com case 0xb: 1088190SLisa.Hsu@amd.com bigData = (bigData << 8) | (bigData << 24) | 1097568SN/A (bigData << 40) | (bigData << 56); 1108949Sandreas.hansson@arm.com break; 1116899SN/A case 0xc: 1127053SN/A bigData = (0xffULL << 0) | (bigData << 8) | 1137053SN/A (0xffULL << 32) | (bigData << 40); 1147053SN/A break; 1157053SN/A case 0xd: 1166899SN/A bigData = (0xffffULL << 0) | (bigData << 16) | 1178975Sandreas.hansson@arm.com (0xffffULL << 32) | (bigData << 48); 1187053SN/A break; 1197053SN/A case 0xe: 1207053SN/A if (op) { 1217053SN/A bigData = (bigData << 0) | (bigData << 8) | 1227053SN/A (bigData << 16) | (bigData << 24) | 1237053SN/A (bigData << 32) | (bigData << 40) | 1247053SN/A (bigData << 48) | (bigData << 56); 1257053SN/A } else { 1266899SN/A bigData = 0; 1277053SN/A for (int i = 7; i >= 0; i--) { 1287053SN/A if (bits(data, i)) { 1297053SN/A bigData |= (0xFF << (i * 8)); 1306899SN/A } 1316899SN/A } 1327053SN/A } 1338184Ssomayeh@cs.wisc.edu case 0xf: 1348184Ssomayeh@cs.wisc.edu if (!op) { 1358184Ssomayeh@cs.wisc.edu uint64_t bVal = bits(bigData, 6) ? (0x1F) : (0x20); 1368184Ssomayeh@cs.wisc.edu bigData = (bits(bigData, 5, 0) << 19) | 1378184Ssomayeh@cs.wisc.edu (bVal << 25) | (bits(bigData, 7) << 31); 1388932SBrad.Beckmann@amd.com bigData |= (bigData << 32); 1398950Sandreas.hansson@arm.com } 1408184Ssomayeh@cs.wisc.edu // Fall through 1418184Ssomayeh@cs.wisc.edu default: 1428184Ssomayeh@cs.wisc.edu panic("Illegal modified SIMD immediate parameters.\n"); 1438832SAli.Saidi@ARM.com } 1448832SAli.Saidi@ARM.com return bigData; 1458184Ssomayeh@cs.wisc.edu} 1468184Ssomayeh@cs.wisc.edu 1478184Ssomayeh@cs.wisc.edu 1488184Ssomayeh@cs.wisc.edu/** 1498184Ssomayeh@cs.wisc.edu * Base class for predicated integer operations. 1508949Sandreas.hansson@arm.com */ 1518184Ssomayeh@cs.wisc.educlass PredOp : public ArmStaticInst 1528184Ssomayeh@cs.wisc.edu{ 1538184Ssomayeh@cs.wisc.edu protected: 1548184Ssomayeh@cs.wisc.edu 1558184Ssomayeh@cs.wisc.edu ConditionCode condCode; 1568184Ssomayeh@cs.wisc.edu 1578975Sandreas.hansson@arm.com /// Constructor 1588184Ssomayeh@cs.wisc.edu PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 1598184Ssomayeh@cs.wisc.edu ArmStaticInst(mnem, _machInst, __opClass), 1608184Ssomayeh@cs.wisc.edu condCode((ConditionCode)(unsigned)machInst.condCode) 1618184Ssomayeh@cs.wisc.edu { 1628184Ssomayeh@cs.wisc.edu } 1637053SN/A}; 1646899SN/A 1657053SN/A/** 1667053SN/A * Base class for predicated immediate operations. 1676899SN/A */ 1688932SBrad.Beckmann@amd.comclass PredImmOp : public PredOp 1698950Sandreas.hansson@arm.com{ 1706899SN/A protected: 1717053SN/A 1726899SN/A uint32_t imm; 1737053SN/A uint32_t rotated_imm; 1747053SN/A uint32_t rotated_carry; 1756899SN/A uint32_t rotate; 1767053SN/A 1778832SAli.Saidi@ARM.com /// Constructor 1788832SAli.Saidi@ARM.com PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 1797053SN/A PredOp(mnem, _machInst, __opClass), 1806899SN/A imm(machInst.imm), rotated_imm(0), rotated_carry(0), 1818190SLisa.Hsu@amd.com rotate(machInst.rotate << 1) 1827053SN/A { 1837053SN/A rotated_imm = rotate_imm(imm, rotate); 1847053SN/A if (rotate != 0) 1857053SN/A rotated_carry = bits(rotated_imm, 31); 1867053SN/A } 1877053SN/A 1886899SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 1897053SN/A}; 1906899SN/A 1918949Sandreas.hansson@arm.com/** 1929208Snilay@cs.wisc.edu * Base class for predicated integer operations. 1937053SN/A */ 1947053SN/Aclass PredIntOp : public PredOp 1956899SN/A{ 1967053SN/A protected: 1977053SN/A 1986899SN/A uint32_t shift_size; 1997053SN/A uint32_t shift; 2007053SN/A 2017053SN/A /// Constructor 2027053SN/A PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 2036899SN/A PredOp(mnem, _machInst, __opClass), 2048975Sandreas.hansson@arm.com shift_size(machInst.shiftSize), shift(machInst.shift) 2057053SN/A { 2067053SN/A } 2077053SN/A 2087053SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2097053SN/A}; 2107053SN/A 2117053SN/Aclass DataImmOp : public PredOp 2127053SN/A{ 2137053SN/A protected: 2147053SN/A IntRegIndex dest, op1; 2157053SN/A uint32_t imm; 2167053SN/A // Whether the carry flag should be modified if that's an option for 2177053SN/A // this instruction. 2187053SN/A bool rotC; 2197053SN/A 2207053SN/A DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2217053SN/A IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 2227053SN/A PredOp(mnem, _machInst, __opClass), 2236899SN/A dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 2246899SN/A {} 2256899SN/A 2267053SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2277053SN/A}; 2286899SN/A 2297053SN/Aclass DataRegOp : public PredOp 2307053SN/A{ 2316899SN/A protected: 2328932SBrad.Beckmann@amd.com IntRegIndex dest, op1, op2; 2338950Sandreas.hansson@arm.com int32_t shiftAmt; 2346899SN/A ArmShiftType shiftType; 2357053SN/A 2366899SN/A DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2378932SBrad.Beckmann@amd.com IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 2388950Sandreas.hansson@arm.com int32_t _shiftAmt, ArmShiftType _shiftType) : 2397053SN/A PredOp(mnem, _machInst, __opClass), 2407053SN/A dest(_dest), op1(_op1), op2(_op2), 2416899SN/A shiftAmt(_shiftAmt), shiftType(_shiftType) 2427568SN/A {} 2437568SN/A 2448832SAli.Saidi@ARM.com std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2457568SN/A}; 2468190SLisa.Hsu@amd.com 2478949Sandreas.hansson@arm.comclass DataRegRegOp : public PredOp 2489208Snilay@cs.wisc.edu{ 2497053SN/A protected: 2506899SN/A IntRegIndex dest, op1, op2, shift; 2517053SN/A ArmShiftType shiftType; 2527053SN/A 2537053SN/A DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2547053SN/A IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 2556899SN/A IntRegIndex _shift, ArmShiftType _shiftType) : 2568975Sandreas.hansson@arm.com PredOp(mnem, _machInst, __opClass), 2577053SN/A dest(_dest), op1(_op1), op2(_op2), shift(_shift), 2587053SN/A shiftType(_shiftType) 2597053SN/A {} 2607053SN/A 2617053SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2627053SN/A}; 2637053SN/A 2647053SN/A/** 2657053SN/A * Base class for predicated macro-operations. 2667053SN/A */ 2677053SN/Aclass PredMacroOp : public PredOp 2687053SN/A{ 2697053SN/A protected: 2706899SN/A 2717053SN/A uint32_t numMicroops; 2727053SN/A StaticInstPtr * microOps; 2737053SN/A 2747053SN/A /// Constructor 2757053SN/A PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 2766899SN/A PredOp(mnem, _machInst, __opClass), 2776899SN/A numMicroops(0) 2787053SN/A { 2797053SN/A // We rely on the subclasses of this object to handle the 2806899SN/A // initialization of the micro-operations, since they are 2817053SN/A // all of variable length 2826899SN/A flags[IsMacroop] = true; 2837053SN/A } 2847053SN/A 2856899SN/A ~PredMacroOp() 2867053SN/A { 2877053SN/A if (numMicroops) 2887053SN/A delete [] microOps; 2897053SN/A } 2906899SN/A 2916899SN/A StaticInstPtr 2927053SN/A fetchMicroop(MicroPC microPC) 2937053SN/A { 2947053SN/A assert(microPC < numMicroops); 2957053SN/A return microOps[microPC]; 2967053SN/A } 2977053SN/A 2987053SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2997053SN/A}; 3007053SN/A 3017053SN/A/** 3027053SN/A * Base class for predicated micro-operations. 3037053SN/A */ 3047053SN/Aclass PredMicroop : public PredOp 3057053SN/A{ 3067053SN/A /// Constructor 3077053SN/A PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 3087053SN/A PredOp(mnem, _machInst, __opClass) 3099208Snilay@cs.wisc.edu { 3107805Snilay@cs.wisc.edu flags[IsMicroop] = true; 3117805Snilay@cs.wisc.edu } 3127805Snilay@cs.wisc.edu}; 3137805Snilay@cs.wisc.edu} 3147805Snilay@cs.wisc.edu 3157805Snilay@cs.wisc.edu#endif //__ARCH_ARM_INSTS_PREDINST_HH__ 3169171Snilay@cs.wisc.edu