pred_inst.hh revision 7137
1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2007-2008 The Florida State University 15 * All rights reserved. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions are 19 * met: redistributions of source code must retain the above copyright 20 * notice, this list of conditions and the following disclaimer; 21 * redistributions in binary form must reproduce the above copyright 22 * notice, this list of conditions and the following disclaimer in the 23 * documentation and/or other materials provided with the distribution; 24 * neither the name of the copyright holders nor the names of its 25 * contributors may be used to endorse or promote products derived from 26 * this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 39 * 40 * Authors: Stephen Hines 41 */ 42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 43#define __ARCH_ARM_INSTS_PREDINST_HH__ 44 45#include "arch/arm/insts/static_inst.hh" 46#include "base/trace.hh" 47 48namespace ArmISA 49{ 50static inline uint32_t 51rotate_imm(uint32_t immValue, int rotateValue) 52{ 53 return ((immValue >> (rotateValue & 31)) | 54 (immValue << (32 - (rotateValue & 31)))); 55} 56 57/** 58 * Base class for predicated integer operations. 59 */ 60class PredOp : public ArmStaticInst 61{ 62 protected: 63 64 ConditionCode condCode; 65 66 /// Constructor 67 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 68 ArmStaticInst(mnem, _machInst, __opClass), 69 condCode((ConditionCode)(unsigned)machInst.condCode) 70 { 71 } 72}; 73 74/** 75 * Base class for predicated immediate operations. 76 */ 77class PredImmOpBase : public PredOp 78{ 79 protected: 80 81 uint32_t imm; 82 uint32_t rotated_imm; 83 uint32_t rotated_carry; 84 85 /// Constructor 86 PredImmOpBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 87 PredOp(mnem, _machInst, __opClass), 88 imm(machInst.imm), rotated_imm(0), rotated_carry(0) 89 { 90 } 91 92 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 93}; 94 95/** 96 * Base class for regular predicated immediate operations. 97 */ 98class PredImmOp : public PredImmOpBase 99{ 100 protected: 101 102 uint32_t rotate; 103 104 /// Constructor 105 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 106 PredImmOpBase(mnem, _machInst, __opClass), 107 rotate(machInst.rotate << 1) 108 { 109 rotated_imm = rotate_imm(imm, rotate); 110 if (rotate != 0) 111 rotated_carry = bits(rotated_imm, 31); 112 } 113}; 114 115/** 116 * Base class for modified predicated immediate operations. 117 */ 118class PredModImmOp : public PredImmOpBase 119{ 120 protected: 121 122 uint8_t ctrlImm; 123 uint8_t dataImm; 124 125 126 /// Constructor 127 PredModImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 128 PredImmOpBase(mnem, _machInst, __opClass), 129 ctrlImm(bits(machInst.instBits, 26) << 3 | 130 bits(machInst.instBits, 14, 12)), 131 dataImm(bits(machInst.instBits, 7, 0)) 132 { 133 rotated_imm = modified_imm(ctrlImm, dataImm); 134 rotated_carry = bits(rotated_imm, 31); 135 } 136}; 137 138/** 139 * Base class for predicated integer operations. 140 */ 141class PredIntOp : public PredOp 142{ 143 protected: 144 145 uint32_t shift_size; 146 uint32_t shift; 147 148 /// Constructor 149 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 150 PredOp(mnem, _machInst, __opClass), 151 shift_size(machInst.shiftSize), shift(machInst.shift) 152 { 153 } 154 155 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 156}; 157 158class DataImmOp : public PredOp 159{ 160 protected: 161 IntRegIndex dest, op1; 162 uint32_t imm; 163 // Whether the carry flag should be modified if that's an option for 164 // this instruction. 165 bool rotC; 166 167 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 168 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 169 PredOp(mnem, _machInst, __opClass), 170 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 171 {} 172}; 173 174class DataRegOp : public PredOp 175{ 176 protected: 177 IntRegIndex dest, op1, op2; 178 int32_t shiftAmt; 179 ArmShiftType shiftType; 180 181 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 182 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 183 int32_t _shiftAmt, ArmShiftType _shiftType) : 184 PredOp(mnem, _machInst, __opClass), 185 dest(_dest), op1(_op1), op2(_op2), 186 shiftAmt(_shiftAmt), shiftType(_shiftType) 187 {} 188}; 189 190class DataRegRegOp : public PredOp 191{ 192 protected: 193 IntRegIndex dest, op1, op2, shift; 194 ArmShiftType shiftType; 195 196 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 197 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 198 IntRegIndex _shift, ArmShiftType _shiftType) : 199 PredOp(mnem, _machInst, __opClass), 200 dest(_dest), op1(_op1), op2(_op2), shift(_shift), 201 shiftType(_shiftType) 202 {} 203}; 204 205/** 206 * Base class for predicated macro-operations. 207 */ 208class PredMacroOp : public PredOp 209{ 210 protected: 211 212 uint32_t numMicroops; 213 StaticInstPtr * microOps; 214 215 /// Constructor 216 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 217 PredOp(mnem, _machInst, __opClass), 218 numMicroops(0) 219 { 220 // We rely on the subclasses of this object to handle the 221 // initialization of the micro-operations, since they are 222 // all of variable length 223 flags[IsMacroop] = true; 224 } 225 226 ~PredMacroOp() 227 { 228 if (numMicroops) 229 delete [] microOps; 230 } 231 232 StaticInstPtr 233 fetchMicroop(MicroPC microPC) 234 { 235 assert(microPC < numMicroops); 236 return microOps[microPC]; 237 } 238 239 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 240}; 241 242/** 243 * Base class for predicated micro-operations. 244 */ 245class PredMicroop : public PredOp 246{ 247 /// Constructor 248 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 249 PredOp(mnem, _machInst, __opClass) 250 { 251 flags[IsMicroop] = true; 252 } 253}; 254} 255 256#endif //__ARCH_ARM_INSTS_PREDINST_HH__ 257