pred_inst.hh revision 10537
12SN/A/* 21762SN/A * Copyright (c) 2010, 2012-2013 ARM Limited 32SN/A * All rights reserved 42SN/A * 52SN/A * The license below extends only to copyright in the software and shall 62SN/A * not be construed as granting a license to any other intellectual 72SN/A * property including but not limited to intellectual property relating 82SN/A * to a hardware implementation of the functionality of the software 92SN/A * licensed hereunder. You may use the software subject to the license 102SN/A * terms below provided that you ensure that this notice is replicated 112SN/A * unmodified and in its entirety in all distributions of the software, 122SN/A * modified or unmodified, in source code or in binary form. 132SN/A * 142SN/A * Copyright (c) 2007-2008 The Florida State University 152SN/A * All rights reserved. 162SN/A * 172SN/A * Redistribution and use in source and binary forms, with or without 182SN/A * modification, are permitted provided that the following conditions are 192SN/A * met: redistributions of source code must retain the above copyright 202SN/A * notice, this list of conditions and the following disclaimer; 212SN/A * redistributions in binary form must reproduce the above copyright 222SN/A * notice, this list of conditions and the following disclaimer in the 232SN/A * documentation and/or other materials provided with the distribution; 242SN/A * neither the name of the copyright holders nor the names of its 252SN/A * contributors may be used to endorse or promote products derived from 262SN/A * this software without specific prior written permission. 272665Ssaidi@eecs.umich.edu * 282665Ssaidi@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292665Ssaidi@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352147SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 367678Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 378229Snate@binkert.org * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 387878Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392147SN/A * 402147SN/A * Authors: Stephen Hines 412680Sktlim@umich.edu */ 422132SN/A#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 432147SN/A#define __ARCH_ARM_INSTS_PREDINST_HH__ 445999Snate@binkert.org 452147SN/A#include "arch/arm/insts/static_inst.hh" 462147SN/A#include "base/trace.hh" 472147SN/A 482147SN/Anamespace ArmISA 492147SN/A{ 502147SN/Astatic inline uint32_t 512147SN/Arotate_imm(uint32_t immValue, uint32_t rotateValue) 522147SN/A{ 532147SN/A rotateValue &= 31; 542090SN/A return rotateValue == 0 ? immValue : 552147SN/A (immValue >> rotateValue) | (immValue << (32 - rotateValue)); 564695Sgblack@eecs.umich.edu} 5710417Sandreas.hansson@arm.com 5810417Sandreas.hansson@arm.comstatic inline uint32_t 592SN/Amodified_imm(uint8_t ctrlImm, uint8_t dataImm) 602SN/A{ 612612SN/A uint32_t bigData = dataImm; 622612SN/A uint32_t bigCtrl = ctrlImm; 632612SN/A if (bigCtrl < 4) { 642612SN/A switch (bigCtrl) { 652612SN/A case 0: 662612SN/A return bigData; 672612SN/A case 1: 682612SN/A return bigData | (bigData << 16); 692612SN/A case 2: 704695Sgblack@eecs.umich.edu return (bigData << 8) | (bigData << 24); 7110417Sandreas.hansson@arm.com case 3: 7210417Sandreas.hansson@arm.com return (bigData << 0) | (bigData << 8) | 732612SN/A (bigData << 16) | (bigData << 24); 742612SN/A } 758545Ssaidi@eecs.umich.edu } 768545Ssaidi@eecs.umich.edu bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1); 778545Ssaidi@eecs.umich.edu bigData |= (1 << 7); 788545Ssaidi@eecs.umich.edu return bigData << (32 - bigCtrl); 798545Ssaidi@eecs.umich.edu} 8010417Sandreas.hansson@arm.com 8110417Sandreas.hansson@arm.comstatic inline uint64_t 828545Ssaidi@eecs.umich.edusimd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid, 838545Ssaidi@eecs.umich.edu bool isAarch64 = false) 845004Sgblack@eecs.umich.edu{ 854183Sgblack@eecs.umich.edu uint64_t bigData = data; 864183Sgblack@eecs.umich.edu immValid = true; 874183Sgblack@eecs.umich.edu switch (cmode) { 884183Sgblack@eecs.umich.edu case 0x0: 895004Sgblack@eecs.umich.edu case 0x1: 905004Sgblack@eecs.umich.edu bigData = (bigData << 0) | (bigData << 32); 9110417Sandreas.hansson@arm.com break; 9210417Sandreas.hansson@arm.com case 0x2: 935004Sgblack@eecs.umich.edu case 0x3: 945004Sgblack@eecs.umich.edu bigData = (bigData << 8) | (bigData << 40); 955004Sgblack@eecs.umich.edu break; 965004Sgblack@eecs.umich.edu case 0x4: 975004Sgblack@eecs.umich.edu case 0x5: 985004Sgblack@eecs.umich.edu bigData = (bigData << 16) | (bigData << 48); 995004Sgblack@eecs.umich.edu break; 1005004Sgblack@eecs.umich.edu case 0x6: 1015004Sgblack@eecs.umich.edu case 0x7: 10210417Sandreas.hansson@arm.com bigData = (bigData << 24) | (bigData << 56); 10310417Sandreas.hansson@arm.com break; 1044183Sgblack@eecs.umich.edu case 0x8: 1054183Sgblack@eecs.umich.edu case 0x9: 1062SN/A bigData = (bigData << 0) | (bigData << 16) | 107 (bigData << 32) | (bigData << 48); 108 break; 109 case 0xa: 110 case 0xb: 111 bigData = (bigData << 8) | (bigData << 24) | 112 (bigData << 40) | (bigData << 56); 113 break; 114 case 0xc: 115 bigData = (0xffULL << 0) | (bigData << 8) | 116 (0xffULL << 32) | (bigData << 40); 117 break; 118 case 0xd: 119 bigData = (0xffffULL << 0) | (bigData << 16) | 120 (0xffffULL << 32) | (bigData << 48); 121 break; 122 case 0xe: 123 if (op) { 124 bigData = 0; 125 for (int i = 7; i >= 0; i--) { 126 if (bits(data, i)) { 127 bigData |= (ULL(0xFF) << (i * 8)); 128 } 129 } 130 } else { 131 bigData = (bigData << 0) | (bigData << 8) | 132 (bigData << 16) | (bigData << 24) | 133 (bigData << 32) | (bigData << 40) | 134 (bigData << 48) | (bigData << 56); 135 } 136 break; 137 case 0xf: 138 { 139 uint64_t bVal = 0; 140 if (!op) { 141 bVal = bits(bigData, 6) ? (0x1F) : (0x20); 142 bigData = (bits(bigData, 5, 0) << 19) | 143 (bVal << 25) | (bits(bigData, 7) << 31); 144 bigData |= (bigData << 32); 145 break; 146 } else if (isAarch64) { 147 bVal = bits(bigData, 6) ? (0x0FF) : (0x100); 148 bigData = (bits(bigData, 5, 0) << 48) | 149 (bVal << 54) | (bits(bigData, 7) << 63); 150 break; 151 } 152 } 153 // Fall through, immediate encoding is invalid. 154 default: 155 immValid = false; 156 break; 157 } 158 return bigData; 159} 160 161static inline uint64_t 162vfp_modified_imm(uint8_t data, bool wide) 163{ 164 uint64_t bigData = data; 165 uint64_t repData; 166 if (wide) { 167 repData = bits(data, 6) ? 0xFF : 0; 168 bigData = (bits(bigData, 5, 0) << 48) | 169 (repData << 54) | (bits(~bigData, 6) << 62) | 170 (bits(bigData, 7) << 63); 171 } else { 172 repData = bits(data, 6) ? 0x1F : 0; 173 bigData = (bits(bigData, 5, 0) << 19) | 174 (repData << 25) | (bits(~bigData, 6) << 30) | 175 (bits(bigData, 7) << 31); 176 } 177 return bigData; 178} 179 180 181/** 182 * Base class for predicated integer operations. 183 */ 184class PredOp : public ArmStaticInst 185{ 186 protected: 187 188 ConditionCode condCode; 189 190 /// Constructor 191 PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 192 ArmStaticInst(mnem, _machInst, __opClass) 193 { 194 if (machInst.aarch64) 195 condCode = COND_UC; 196 else if (machInst.itstateMask) 197 condCode = (ConditionCode)(uint8_t)machInst.itstateCond; 198 else 199 condCode = (ConditionCode)(unsigned)machInst.condCode; 200 } 201}; 202 203/** 204 * Base class for predicated immediate operations. 205 */ 206class PredImmOp : public PredOp 207{ 208 protected: 209 210 uint32_t imm; 211 uint32_t rotated_imm; 212 uint32_t rotated_carry; 213 uint32_t rotate; 214 215 /// Constructor 216 PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 217 PredOp(mnem, _machInst, __opClass), 218 imm(machInst.imm), rotated_imm(0), rotated_carry(0), 219 rotate(machInst.rotate << 1) 220 { 221 rotated_imm = rotate_imm(imm, rotate); 222 if (rotate != 0) 223 rotated_carry = bits(rotated_imm, 31); 224 } 225 226 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 227}; 228 229/** 230 * Base class for predicated integer operations. 231 */ 232class PredIntOp : public PredOp 233{ 234 protected: 235 236 uint32_t shift_size; 237 uint32_t shift; 238 239 /// Constructor 240 PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 241 PredOp(mnem, _machInst, __opClass), 242 shift_size(machInst.shiftSize), shift(machInst.shift) 243 { 244 } 245 246 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 247}; 248 249class DataImmOp : public PredOp 250{ 251 protected: 252 IntRegIndex dest, op1; 253 uint32_t imm; 254 // Whether the carry flag should be modified if that's an option for 255 // this instruction. 256 bool rotC; 257 258 DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 259 IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 260 PredOp(mnem, _machInst, __opClass), 261 dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 262 {} 263 264 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 265}; 266 267class DataRegOp : public PredOp 268{ 269 protected: 270 IntRegIndex dest, op1, op2; 271 int32_t shiftAmt; 272 ArmShiftType shiftType; 273 274 DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 275 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 276 int32_t _shiftAmt, ArmShiftType _shiftType) : 277 PredOp(mnem, _machInst, __opClass), 278 dest(_dest), op1(_op1), op2(_op2), 279 shiftAmt(_shiftAmt), shiftType(_shiftType) 280 {} 281 282 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 283}; 284 285class DataRegRegOp : public PredOp 286{ 287 protected: 288 IntRegIndex dest, op1, op2, shift; 289 ArmShiftType shiftType; 290 291 DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 292 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 293 IntRegIndex _shift, ArmShiftType _shiftType) : 294 PredOp(mnem, _machInst, __opClass), 295 dest(_dest), op1(_op1), op2(_op2), shift(_shift), 296 shiftType(_shiftType) 297 {} 298 299 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 300}; 301 302/** 303 * Base class for predicated macro-operations. 304 */ 305class PredMacroOp : public PredOp 306{ 307 protected: 308 309 uint32_t numMicroops; 310 StaticInstPtr * microOps; 311 312 /// Constructor 313 PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 314 PredOp(mnem, _machInst, __opClass), 315 numMicroops(0), microOps(nullptr) 316 { 317 // We rely on the subclasses of this object to handle the 318 // initialization of the micro-operations, since they are 319 // all of variable length 320 flags[IsMacroop] = true; 321 } 322 323 ~PredMacroOp() 324 { 325 if (numMicroops) 326 delete [] microOps; 327 } 328 329 StaticInstPtr 330 fetchMicroop(MicroPC microPC) const 331 { 332 assert(microPC < numMicroops); 333 return microOps[microPC]; 334 } 335 336 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 337}; 338 339/** 340 * Base class for predicated micro-operations. 341 */ 342class PredMicroop : public PredOp 343{ 344 /// Constructor 345 PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 346 PredOp(mnem, _machInst, __opClass) 347 { 348 flags[IsMicroop] = true; 349 } 350 351 void 352 advancePC(PCState &pcState) const 353 { 354 if (flags[IsLastMicroop]) 355 pcState.uEnd(); 356 else 357 pcState.uAdvance(); 358 } 359}; 360} 361 362#endif //__ARCH_ARM_INSTS_PREDINST_HH__ 363