pred_inst.hh revision 10037:5cac77888310 
1/*
2 * Copyright (c) 2010, 2012-2013 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2007-2008 The Florida State University
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Stephen Hines
41 */
42#ifndef __ARCH_ARM_INSTS_PREDINST_HH__
43#define __ARCH_ARM_INSTS_PREDINST_HH__
44
45#include "arch/arm/insts/static_inst.hh"
46#include "base/trace.hh"
47
48namespace ArmISA
49{
50static inline uint32_t
51rotate_imm(uint32_t immValue, int rotateValue)
52{
53    return ((immValue >> (rotateValue & 31)) |
54            (immValue << (32 - (rotateValue & 31))));
55}
56
57static inline uint32_t
58modified_imm(uint8_t ctrlImm, uint8_t dataImm)
59{
60    uint32_t bigData = dataImm;
61    uint32_t bigCtrl = ctrlImm;
62    if (bigCtrl < 4) {
63        switch (bigCtrl) {
64          case 0:
65            return bigData;
66          case 1:
67            return bigData | (bigData << 16);
68          case 2:
69            return (bigData << 8) | (bigData << 24);
70          case 3:
71            return (bigData << 0) | (bigData << 8) |
72                   (bigData << 16) | (bigData << 24);
73        }
74    }
75    bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1);
76    bigData |= (1 << 7);
77    return bigData << (32 - bigCtrl);
78}
79
80static inline uint64_t
81simd_modified_imm(bool op, uint8_t cmode, uint8_t data, bool &immValid,
82                  bool isAarch64 = false)
83{
84    uint64_t bigData = data;
85    immValid = true;
86    switch (cmode) {
87      case 0x0:
88      case 0x1:
89        bigData = (bigData << 0) | (bigData << 32);
90        break;
91      case 0x2:
92      case 0x3:
93        bigData = (bigData << 8) | (bigData << 40);
94        break;
95      case 0x4:
96      case 0x5:
97        bigData = (bigData << 16) | (bigData << 48);
98        break;
99      case 0x6:
100      case 0x7:
101        bigData = (bigData << 24) | (bigData << 56);
102        break;
103      case 0x8:
104      case 0x9:
105        bigData = (bigData << 0) | (bigData << 16) |
106                  (bigData << 32) | (bigData << 48);
107        break;
108      case 0xa:
109      case 0xb:
110        bigData = (bigData << 8) | (bigData << 24) |
111                  (bigData << 40) | (bigData << 56);
112        break;
113      case 0xc:
114        bigData = (0xffULL << 0) | (bigData << 8) |
115                  (0xffULL << 32) | (bigData << 40);
116        break;
117      case 0xd:
118        bigData = (0xffffULL << 0) | (bigData << 16) |
119                  (0xffffULL << 32) | (bigData << 48);
120        break;
121      case 0xe:
122        if (op) {
123            bigData = 0;
124            for (int i = 7; i >= 0; i--) {
125                if (bits(data, i)) {
126                    bigData |= (ULL(0xFF) << (i * 8));
127                }
128            }
129        } else {
130            bigData = (bigData << 0)  | (bigData << 8)  |
131                      (bigData << 16) | (bigData << 24) |
132                      (bigData << 32) | (bigData << 40) |
133                      (bigData << 48) | (bigData << 56);
134        }
135        break;
136      case 0xf:
137        {
138            uint64_t bVal = 0;
139            if (!op) {
140                bVal = bits(bigData, 6) ? (0x1F) : (0x20);
141                bigData = (bits(bigData, 5, 0) << 19) |
142                          (bVal << 25) | (bits(bigData, 7) << 31);
143                bigData |= (bigData << 32);
144                break;
145            } else if (isAarch64) {
146                bVal = bits(bigData, 6) ? (0x0FF) : (0x100);
147                bigData = (bits(bigData, 5, 0) << 48) |
148                          (bVal << 54) | (bits(bigData, 7) << 63);
149                break;
150            }
151        }
152        // Fall through, immediate encoding is invalid.
153      default:
154        immValid = false;
155        break;
156    }
157    return bigData;
158}
159
160static inline uint64_t
161vfp_modified_imm(uint8_t data, bool wide)
162{
163    uint64_t bigData = data;
164    uint64_t repData;
165    if (wide) {
166        repData = bits(data, 6) ? 0xFF : 0;
167        bigData = (bits(bigData, 5, 0) << 48) |
168                  (repData << 54) | (bits(~bigData, 6) << 62) |
169                  (bits(bigData, 7) << 63);
170    } else {
171        repData = bits(data, 6) ? 0x1F : 0;
172        bigData = (bits(bigData, 5, 0) << 19) |
173                  (repData << 25) | (bits(~bigData, 6) << 30) |
174                  (bits(bigData, 7) << 31);
175    }
176    return bigData;
177}
178
179
180/**
181 * Base class for predicated integer operations.
182 */
183class PredOp : public ArmStaticInst
184{
185  protected:
186
187    ConditionCode condCode;
188
189    /// Constructor
190    PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
191           ArmStaticInst(mnem, _machInst, __opClass)
192    {
193        if (machInst.aarch64)
194            condCode = COND_UC;
195        else if (machInst.itstateMask)
196            condCode = (ConditionCode)(uint8_t)machInst.itstateCond;
197        else
198            condCode = (ConditionCode)(unsigned)machInst.condCode;
199    }
200};
201
202/**
203 * Base class for predicated immediate operations.
204 */
205class PredImmOp : public PredOp
206{
207    protected:
208
209    uint32_t imm;
210    uint32_t rotated_imm;
211    uint32_t rotated_carry;
212    uint32_t rotate;
213
214    /// Constructor
215    PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
216              PredOp(mnem, _machInst, __opClass),
217              imm(machInst.imm), rotated_imm(0), rotated_carry(0),
218              rotate(machInst.rotate << 1)
219    {
220        rotated_imm = rotate_imm(imm, rotate);
221        if (rotate != 0)
222            rotated_carry = bits(rotated_imm, 31);
223    }
224
225    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
226};
227
228/**
229 * Base class for predicated integer operations.
230 */
231class PredIntOp : public PredOp
232{
233    protected:
234
235    uint32_t shift_size;
236    uint32_t shift;
237
238    /// Constructor
239    PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
240              PredOp(mnem, _machInst, __opClass),
241              shift_size(machInst.shiftSize), shift(machInst.shift)
242    {
243    }
244
245    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
246};
247
248class DataImmOp : public PredOp
249{
250  protected:
251    IntRegIndex dest, op1;
252    uint32_t imm;
253    // Whether the carry flag should be modified if that's an option for
254    // this instruction.
255    bool rotC;
256
257    DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
258              IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
259        PredOp(mnem, _machInst, __opClass),
260        dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
261    {}
262
263    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
264};
265
266class DataRegOp : public PredOp
267{
268  protected:
269    IntRegIndex dest, op1, op2;
270    int32_t shiftAmt;
271    ArmShiftType shiftType;
272
273    DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
274              IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
275              int32_t _shiftAmt, ArmShiftType _shiftType) :
276        PredOp(mnem, _machInst, __opClass),
277        dest(_dest), op1(_op1), op2(_op2),
278        shiftAmt(_shiftAmt), shiftType(_shiftType)
279    {}
280
281    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
282};
283
284class DataRegRegOp : public PredOp
285{
286  protected:
287    IntRegIndex dest, op1, op2, shift;
288    ArmShiftType shiftType;
289
290    DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
291                 IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
292                 IntRegIndex _shift, ArmShiftType _shiftType) :
293        PredOp(mnem, _machInst, __opClass),
294        dest(_dest), op1(_op1), op2(_op2), shift(_shift),
295        shiftType(_shiftType)
296    {}
297
298    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
299};
300
301/**
302 * Base class for predicated macro-operations.
303 */
304class PredMacroOp : public PredOp
305{
306    protected:
307
308    uint32_t numMicroops;
309    StaticInstPtr * microOps;
310
311    /// Constructor
312    PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
313                PredOp(mnem, _machInst, __opClass),
314                numMicroops(0)
315    {
316        // We rely on the subclasses of this object to handle the
317        // initialization of the micro-operations, since they are
318        // all of variable length
319        flags[IsMacroop] = true;
320    }
321
322    ~PredMacroOp()
323    {
324        if (numMicroops)
325            delete [] microOps;
326    }
327
328    StaticInstPtr
329    fetchMicroop(MicroPC microPC) const
330    {
331        assert(microPC < numMicroops);
332        return microOps[microPC];
333    }
334
335    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
336};
337
338/**
339 * Base class for predicated micro-operations.
340 */
341class PredMicroop : public PredOp
342{
343    /// Constructor
344    PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
345                PredOp(mnem, _machInst, __opClass)
346    {
347        flags[IsMicroop] = true;
348    }
349
350    void
351    advancePC(PCState &pcState) const
352    {
353        if (flags[IsLastMicroop])
354            pcState.uEnd();
355        else
356            pcState.uAdvance();
357    }
358};
359}
360
361#endif //__ARCH_ARM_INSTS_PREDINST_HH__
362