pred_inst.hh revision 7329
17110Sgblack@eecs.umich.edu/* 27110Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37110Sgblack@eecs.umich.edu * All rights reserved 47110Sgblack@eecs.umich.edu * 57110Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67110Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77110Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87110Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97110Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107110Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117110Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127110Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137110Sgblack@eecs.umich.edu * 147110Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_INSTS_PREDINST_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_INSTS_PREDINST_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/static_inst.hh" 466253Sgblack@eecs.umich.edu#include "base/trace.hh" 476253Sgblack@eecs.umich.edu 486253Sgblack@eecs.umich.edunamespace ArmISA 496253Sgblack@eecs.umich.edu{ 506253Sgblack@eecs.umich.edustatic inline uint32_t 516253Sgblack@eecs.umich.edurotate_imm(uint32_t immValue, int rotateValue) 526253Sgblack@eecs.umich.edu{ 536253Sgblack@eecs.umich.edu return ((immValue >> (rotateValue & 31)) | 546253Sgblack@eecs.umich.edu (immValue << (32 - (rotateValue & 31)))); 556253Sgblack@eecs.umich.edu} 566253Sgblack@eecs.umich.edu 577140Sgblack@eecs.umich.edustatic inline uint32_t 587140Sgblack@eecs.umich.edumodified_imm(uint8_t ctrlImm, uint8_t dataImm) 597140Sgblack@eecs.umich.edu{ 607140Sgblack@eecs.umich.edu uint32_t bigData = dataImm; 617140Sgblack@eecs.umich.edu uint32_t bigCtrl = ctrlImm; 627140Sgblack@eecs.umich.edu if (bigCtrl < 4) { 637140Sgblack@eecs.umich.edu switch (bigCtrl) { 647140Sgblack@eecs.umich.edu case 0: 657140Sgblack@eecs.umich.edu return bigData; 667140Sgblack@eecs.umich.edu case 1: 677140Sgblack@eecs.umich.edu return bigData | (bigData << 16); 687140Sgblack@eecs.umich.edu case 2: 697140Sgblack@eecs.umich.edu return (bigData << 8) | (bigData << 24); 707140Sgblack@eecs.umich.edu case 3: 717140Sgblack@eecs.umich.edu return (bigData << 0) | (bigData << 8) | 727140Sgblack@eecs.umich.edu (bigData << 16) | (bigData << 24); 737140Sgblack@eecs.umich.edu } 747140Sgblack@eecs.umich.edu } 757140Sgblack@eecs.umich.edu bigCtrl = (bigCtrl << 1) | ((bigData >> 7) & 0x1); 767140Sgblack@eecs.umich.edu bigData |= (1 << 7); 777140Sgblack@eecs.umich.edu return bigData << (32 - bigCtrl); 787140Sgblack@eecs.umich.edu} 797140Sgblack@eecs.umich.edu 807328Sgblack@eecs.umich.edustatic inline uint64_t 817328Sgblack@eecs.umich.edusimd_modified_imm(bool op, uint8_t cmode, uint8_t data) 827328Sgblack@eecs.umich.edu{ 837328Sgblack@eecs.umich.edu uint64_t bigData = data; 847328Sgblack@eecs.umich.edu switch (cmode) { 857328Sgblack@eecs.umich.edu case 0x0: 867328Sgblack@eecs.umich.edu case 0x1: 877328Sgblack@eecs.umich.edu bigData = (bigData << 0) | (bigData << 32); 887328Sgblack@eecs.umich.edu break; 897328Sgblack@eecs.umich.edu case 0x2: 907328Sgblack@eecs.umich.edu case 0x3: 917328Sgblack@eecs.umich.edu bigData = (bigData << 8) | (bigData << 40); 927328Sgblack@eecs.umich.edu break; 937328Sgblack@eecs.umich.edu case 0x4: 947328Sgblack@eecs.umich.edu case 0x5: 957328Sgblack@eecs.umich.edu bigData = (bigData << 16) | (bigData << 48); 967328Sgblack@eecs.umich.edu break; 977328Sgblack@eecs.umich.edu case 0x6: 987328Sgblack@eecs.umich.edu case 0x7: 997328Sgblack@eecs.umich.edu bigData = (bigData << 24) | (bigData << 56); 1007328Sgblack@eecs.umich.edu break; 1017328Sgblack@eecs.umich.edu case 0x8: 1027328Sgblack@eecs.umich.edu case 0x9: 1037328Sgblack@eecs.umich.edu bigData = (bigData << 0) | (bigData << 16) | 1047328Sgblack@eecs.umich.edu (bigData << 32) | (bigData << 48); 1057328Sgblack@eecs.umich.edu break; 1067328Sgblack@eecs.umich.edu case 0xa: 1077328Sgblack@eecs.umich.edu case 0xb: 1087328Sgblack@eecs.umich.edu bigData = (bigData << 8) | (bigData << 24) | 1097328Sgblack@eecs.umich.edu (bigData << 40) | (bigData << 56); 1107328Sgblack@eecs.umich.edu break; 1117328Sgblack@eecs.umich.edu case 0xc: 1127328Sgblack@eecs.umich.edu bigData = (0xffULL << 0) | (bigData << 8) | 1137328Sgblack@eecs.umich.edu (0xffULL << 32) | (bigData << 40); 1147328Sgblack@eecs.umich.edu break; 1157328Sgblack@eecs.umich.edu case 0xd: 1167328Sgblack@eecs.umich.edu bigData = (0xffffULL << 0) | (bigData << 16) | 1177328Sgblack@eecs.umich.edu (0xffffULL << 32) | (bigData << 48); 1187328Sgblack@eecs.umich.edu break; 1197328Sgblack@eecs.umich.edu case 0xe: 1207328Sgblack@eecs.umich.edu if (op) { 1217328Sgblack@eecs.umich.edu bigData = (bigData << 0) | (bigData << 8) | 1227328Sgblack@eecs.umich.edu (bigData << 16) | (bigData << 24) | 1237328Sgblack@eecs.umich.edu (bigData << 32) | (bigData << 40) | 1247328Sgblack@eecs.umich.edu (bigData << 48) | (bigData << 56); 1257328Sgblack@eecs.umich.edu } else { 1267328Sgblack@eecs.umich.edu bigData = 0; 1277328Sgblack@eecs.umich.edu for (int i = 7; i >= 0; i--) { 1287328Sgblack@eecs.umich.edu if (bits(data, i)) { 1297328Sgblack@eecs.umich.edu bigData |= (0xFF << (i * 8)); 1307328Sgblack@eecs.umich.edu } 1317328Sgblack@eecs.umich.edu } 1327328Sgblack@eecs.umich.edu } 1337328Sgblack@eecs.umich.edu case 0xf: 1347328Sgblack@eecs.umich.edu if (!op) { 1357328Sgblack@eecs.umich.edu uint64_t bVal = bits(bigData, 6) ? (0x1F) : (0x20); 1367328Sgblack@eecs.umich.edu bigData = (bits(bigData, 5, 0) << 19) | 1377328Sgblack@eecs.umich.edu (bVal << 25) | (bits(bigData, 7) << 31); 1387328Sgblack@eecs.umich.edu bigData |= (bigData << 32); 1397328Sgblack@eecs.umich.edu } 1407328Sgblack@eecs.umich.edu // Fall through 1417328Sgblack@eecs.umich.edu default: 1427328Sgblack@eecs.umich.edu panic("Illegal modified SIMD immediate parameters.\n"); 1437328Sgblack@eecs.umich.edu } 1447328Sgblack@eecs.umich.edu return bigData; 1457328Sgblack@eecs.umich.edu} 1467328Sgblack@eecs.umich.edu 1477329Sgblack@eecs.umich.edustatic inline uint64_t 1487329Sgblack@eecs.umich.eduvfp_modified_imm(uint8_t data, bool wide) 1497329Sgblack@eecs.umich.edu{ 1507329Sgblack@eecs.umich.edu uint64_t bigData = data; 1517329Sgblack@eecs.umich.edu uint64_t repData; 1527329Sgblack@eecs.umich.edu if (wide) { 1537329Sgblack@eecs.umich.edu repData = bits(data, 6) ? 0xFF : 0; 1547329Sgblack@eecs.umich.edu bigData = (bits(bigData, 5, 0) << 48) | 1557329Sgblack@eecs.umich.edu (repData << 54) | (bits(~bigData, 6) << 62) | 1567329Sgblack@eecs.umich.edu (bits(bigData, 7) << 63); 1577329Sgblack@eecs.umich.edu } else { 1587329Sgblack@eecs.umich.edu repData = bits(data, 6) ? 0x1F : 0; 1597329Sgblack@eecs.umich.edu bigData = (bits(bigData, 5, 0) << 19) | 1607329Sgblack@eecs.umich.edu (repData << 25) | (bits(~bigData, 6) << 30) | 1617329Sgblack@eecs.umich.edu (bits(bigData, 7) << 31); 1627329Sgblack@eecs.umich.edu } 1637329Sgblack@eecs.umich.edu return bigData; 1647329Sgblack@eecs.umich.edu} 1657329Sgblack@eecs.umich.edu 1667140Sgblack@eecs.umich.edu 1676253Sgblack@eecs.umich.edu/** 1686253Sgblack@eecs.umich.edu * Base class for predicated integer operations. 1696253Sgblack@eecs.umich.edu */ 1706253Sgblack@eecs.umich.educlass PredOp : public ArmStaticInst 1716253Sgblack@eecs.umich.edu{ 1726253Sgblack@eecs.umich.edu protected: 1736253Sgblack@eecs.umich.edu 1746253Sgblack@eecs.umich.edu ConditionCode condCode; 1756253Sgblack@eecs.umich.edu 1766253Sgblack@eecs.umich.edu /// Constructor 1777099Sgblack@eecs.umich.edu PredOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 1786253Sgblack@eecs.umich.edu ArmStaticInst(mnem, _machInst, __opClass), 1796253Sgblack@eecs.umich.edu condCode((ConditionCode)(unsigned)machInst.condCode) 1806253Sgblack@eecs.umich.edu { 1816253Sgblack@eecs.umich.edu } 1826253Sgblack@eecs.umich.edu}; 1836253Sgblack@eecs.umich.edu 1846253Sgblack@eecs.umich.edu/** 1856253Sgblack@eecs.umich.edu * Base class for predicated immediate operations. 1866253Sgblack@eecs.umich.edu */ 1877143Sgblack@eecs.umich.educlass PredImmOp : public PredOp 1886253Sgblack@eecs.umich.edu{ 1896306Sgblack@eecs.umich.edu protected: 1906253Sgblack@eecs.umich.edu 1916306Sgblack@eecs.umich.edu uint32_t imm; 1926306Sgblack@eecs.umich.edu uint32_t rotated_imm; 1936306Sgblack@eecs.umich.edu uint32_t rotated_carry; 1947110Sgblack@eecs.umich.edu uint32_t rotate; 1957110Sgblack@eecs.umich.edu 1967110Sgblack@eecs.umich.edu /// Constructor 1977099Sgblack@eecs.umich.edu PredImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 1987143Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 1997143Sgblack@eecs.umich.edu imm(machInst.imm), rotated_imm(0), rotated_carry(0), 2007110Sgblack@eecs.umich.edu rotate(machInst.rotate << 1) 2016306Sgblack@eecs.umich.edu { 2026306Sgblack@eecs.umich.edu rotated_imm = rotate_imm(imm, rotate); 2036306Sgblack@eecs.umich.edu if (rotate != 0) 2047110Sgblack@eecs.umich.edu rotated_carry = bits(rotated_imm, 31); 2056306Sgblack@eecs.umich.edu } 2066306Sgblack@eecs.umich.edu 2077143Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2086253Sgblack@eecs.umich.edu}; 2096253Sgblack@eecs.umich.edu 2106253Sgblack@eecs.umich.edu/** 2116253Sgblack@eecs.umich.edu * Base class for predicated integer operations. 2126253Sgblack@eecs.umich.edu */ 2136253Sgblack@eecs.umich.educlass PredIntOp : public PredOp 2146253Sgblack@eecs.umich.edu{ 2156306Sgblack@eecs.umich.edu protected: 2166253Sgblack@eecs.umich.edu 2176306Sgblack@eecs.umich.edu uint32_t shift_size; 2186306Sgblack@eecs.umich.edu uint32_t shift; 2196253Sgblack@eecs.umich.edu 2206306Sgblack@eecs.umich.edu /// Constructor 2217099Sgblack@eecs.umich.edu PredIntOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 2226306Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 2236306Sgblack@eecs.umich.edu shift_size(machInst.shiftSize), shift(machInst.shift) 2246306Sgblack@eecs.umich.edu { 2256306Sgblack@eecs.umich.edu } 2266306Sgblack@eecs.umich.edu 2276306Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2286253Sgblack@eecs.umich.edu}; 2296253Sgblack@eecs.umich.edu 2307137Sgblack@eecs.umich.educlass DataImmOp : public PredOp 2317137Sgblack@eecs.umich.edu{ 2327137Sgblack@eecs.umich.edu protected: 2337137Sgblack@eecs.umich.edu IntRegIndex dest, op1; 2347137Sgblack@eecs.umich.edu uint32_t imm; 2357137Sgblack@eecs.umich.edu // Whether the carry flag should be modified if that's an option for 2367137Sgblack@eecs.umich.edu // this instruction. 2377137Sgblack@eecs.umich.edu bool rotC; 2387137Sgblack@eecs.umich.edu 2397137Sgblack@eecs.umich.edu DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2407137Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) : 2417137Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 2427137Sgblack@eecs.umich.edu dest(_dest), op1(_op1), imm(_imm), rotC(_rotC) 2437137Sgblack@eecs.umich.edu {} 2447142Sgblack@eecs.umich.edu 2457142Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2467137Sgblack@eecs.umich.edu}; 2477137Sgblack@eecs.umich.edu 2487137Sgblack@eecs.umich.educlass DataRegOp : public PredOp 2497137Sgblack@eecs.umich.edu{ 2507137Sgblack@eecs.umich.edu protected: 2517137Sgblack@eecs.umich.edu IntRegIndex dest, op1, op2; 2527137Sgblack@eecs.umich.edu int32_t shiftAmt; 2537137Sgblack@eecs.umich.edu ArmShiftType shiftType; 2547137Sgblack@eecs.umich.edu 2557137Sgblack@eecs.umich.edu DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2567137Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 2577137Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType) : 2587137Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 2597137Sgblack@eecs.umich.edu dest(_dest), op1(_op1), op2(_op2), 2607137Sgblack@eecs.umich.edu shiftAmt(_shiftAmt), shiftType(_shiftType) 2617137Sgblack@eecs.umich.edu {} 2627142Sgblack@eecs.umich.edu 2637142Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2647137Sgblack@eecs.umich.edu}; 2657137Sgblack@eecs.umich.edu 2667137Sgblack@eecs.umich.educlass DataRegRegOp : public PredOp 2677137Sgblack@eecs.umich.edu{ 2687137Sgblack@eecs.umich.edu protected: 2697137Sgblack@eecs.umich.edu IntRegIndex dest, op1, op2, shift; 2707137Sgblack@eecs.umich.edu ArmShiftType shiftType; 2717137Sgblack@eecs.umich.edu 2727137Sgblack@eecs.umich.edu DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2737137Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2, 2747137Sgblack@eecs.umich.edu IntRegIndex _shift, ArmShiftType _shiftType) : 2757137Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 2767137Sgblack@eecs.umich.edu dest(_dest), op1(_op1), op2(_op2), shift(_shift), 2777137Sgblack@eecs.umich.edu shiftType(_shiftType) 2787137Sgblack@eecs.umich.edu {} 2797142Sgblack@eecs.umich.edu 2807142Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2817137Sgblack@eecs.umich.edu}; 2827137Sgblack@eecs.umich.edu 2836253Sgblack@eecs.umich.edu/** 2846253Sgblack@eecs.umich.edu * Base class for predicated macro-operations. 2856253Sgblack@eecs.umich.edu */ 2866253Sgblack@eecs.umich.educlass PredMacroOp : public PredOp 2876253Sgblack@eecs.umich.edu{ 2886306Sgblack@eecs.umich.edu protected: 2896253Sgblack@eecs.umich.edu 2906306Sgblack@eecs.umich.edu uint32_t numMicroops; 2916306Sgblack@eecs.umich.edu StaticInstPtr * microOps; 2926253Sgblack@eecs.umich.edu 2936306Sgblack@eecs.umich.edu /// Constructor 2947099Sgblack@eecs.umich.edu PredMacroOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 2956306Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass), 2966306Sgblack@eecs.umich.edu numMicroops(0) 2976306Sgblack@eecs.umich.edu { 2986306Sgblack@eecs.umich.edu // We rely on the subclasses of this object to handle the 2996306Sgblack@eecs.umich.edu // initialization of the micro-operations, since they are 3006306Sgblack@eecs.umich.edu // all of variable length 3016306Sgblack@eecs.umich.edu flags[IsMacroop] = true; 3026306Sgblack@eecs.umich.edu } 3036253Sgblack@eecs.umich.edu 3046306Sgblack@eecs.umich.edu ~PredMacroOp() 3056306Sgblack@eecs.umich.edu { 3066306Sgblack@eecs.umich.edu if (numMicroops) 3076306Sgblack@eecs.umich.edu delete [] microOps; 3086306Sgblack@eecs.umich.edu } 3096253Sgblack@eecs.umich.edu 3106306Sgblack@eecs.umich.edu StaticInstPtr 3116306Sgblack@eecs.umich.edu fetchMicroop(MicroPC microPC) 3126306Sgblack@eecs.umich.edu { 3136306Sgblack@eecs.umich.edu assert(microPC < numMicroops); 3146306Sgblack@eecs.umich.edu return microOps[microPC]; 3156306Sgblack@eecs.umich.edu } 3166253Sgblack@eecs.umich.edu 3176306Sgblack@eecs.umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 3186253Sgblack@eecs.umich.edu}; 3196253Sgblack@eecs.umich.edu 3206253Sgblack@eecs.umich.edu/** 3216253Sgblack@eecs.umich.edu * Base class for predicated micro-operations. 3226253Sgblack@eecs.umich.edu */ 3236253Sgblack@eecs.umich.educlass PredMicroop : public PredOp 3246253Sgblack@eecs.umich.edu{ 3256306Sgblack@eecs.umich.edu /// Constructor 3267099Sgblack@eecs.umich.edu PredMicroop(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 3276306Sgblack@eecs.umich.edu PredOp(mnem, _machInst, __opClass) 3286306Sgblack@eecs.umich.edu { 3296306Sgblack@eecs.umich.edu flags[IsMicroop] = true; 3306306Sgblack@eecs.umich.edu } 3316253Sgblack@eecs.umich.edu}; 3326253Sgblack@eecs.umich.edu} 3336253Sgblack@eecs.umich.edu 3346253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_PREDINST_HH__ 335