pred_inst.cc revision 6262:43950710afdc
1/* Copyright (c) 2007-2008 The Florida State University 2 * All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions are 6 * met: redistributions of source code must retain the above copyright 7 * notice, this list of conditions and the following disclaimer; 8 * redistributions in binary form must reproduce the above copyright 9 * notice, this list of conditions and the following disclaimer in the 10 * documentation and/or other materials provided with the distribution; 11 * neither the name of the copyright holders nor the names of its 12 * contributors may be used to endorse or promote products derived from 13 * this software without specific prior written permission. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26 * 27 * Authors: Stephen Hines 28 */ 29 30#include "arch/arm/insts/pred_inst.hh" 31 32namespace ArmISA 33{ 34std::string 35PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 36{ 37 std::stringstream ss; 38 printMnemonic(ss); 39 if (_numDestRegs > 0) { 40 printReg(ss, _destRegIdx[0]); 41 } 42 43 ss << ", "; 44 45 if (_numSrcRegs > 0) { 46 printReg(ss, _srcRegIdx[0]); 47 ss << ", "; 48 } 49 50 return ss.str(); 51} 52 53std::string 54PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 55{ 56 std::stringstream ss; 57 58 ccprintf(ss, "%-10s ", mnemonic); 59 60 if (_numDestRegs > 0) { 61 printReg(ss, _destRegIdx[0]); 62 } 63 64 ss << ", "; 65 66 if (_numSrcRegs > 0) { 67 printReg(ss, _srcRegIdx[0]); 68 ss << ", "; 69 } 70 71 return ss.str(); 72} 73 74std::string 75PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 76{ 77 std::stringstream ss; 78 79 ccprintf(ss, "%-10s ", mnemonic); 80 81 if (_numDestRegs > 0) { 82 printReg(ss, _destRegIdx[0]); 83 } 84 85 ss << ", "; 86 87 if (_numSrcRegs > 0) { 88 printReg(ss, _srcRegIdx[0]); 89 ss << ", "; 90 } 91 92 return ss.str(); 93} 94 95std::string 96PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const 97{ 98 std::stringstream ss; 99 100 ccprintf(ss, "%-10s ", mnemonic); 101 102 return ss.str(); 103} 104} 105