pred_inst.cc revision 6253:988a001820f8 
12SN/A/* Copyright (c) 2007-2008 The Florida State University
21762SN/A * All rights reserved.
32SN/A *
42SN/A * Redistribution and use in source and binary forms, with or without
52SN/A * modification, are permitted provided that the following conditions are
62SN/A * met: redistributions of source code must retain the above copyright
72SN/A * notice, this list of conditions and the following disclaimer;
82SN/A * redistributions in binary form must reproduce the above copyright
92SN/A * notice, this list of conditions and the following disclaimer in the
102SN/A * documentation and/or other materials provided with the distribution;
112SN/A * neither the name of the copyright holders nor the names of its
122SN/A * contributors may be used to endorse or promote products derived from
132SN/A * this software without specific prior written permission.
142SN/A *
152SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
162SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
172SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
182SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
192SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
202SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
212SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
222SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
232SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
242SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
252SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
262SN/A *
272665Ssaidi@eecs.umich.edu * Authors: Stephen Hines
282665Ssaidi@eecs.umich.edu */
292SN/A
302SN/A#include "arch/arm/insts/pred_inst.hh"
312SN/A
322SN/Anamespace ArmISA
332SN/A{
348229Snate@binkert.orgstd::string
358229Snate@binkert.orgPredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
362SN/A{
378229Snate@binkert.org    std::stringstream ss;
384167Sbinkertn@umich.edu
392SN/A    ccprintf(ss, "%-10s ", mnemonic);
40252SN/A
411872SN/A    if (_numDestRegs > 0) {
42252SN/A        printReg(ss, _destRegIdx[0]);
4310905Sandreas.sandberg@arm.com    }
442SN/A
452SN/A    ss << ", ";
462SN/A
472SN/A    if (_numSrcRegs > 0) {
482SN/A        printReg(ss, _srcRegIdx[0]);
492SN/A        ss << ", ";
502SN/A    }
512SN/A
522SN/A    return ss.str();
532SN/A}
542SN/A
552SN/Astd::string
562SN/APredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
572SN/A{
582SN/A    std::stringstream ss;
592SN/A
60251SN/A    ccprintf(ss, "%-10s ", mnemonic);
61251SN/A
62252SN/A    if (_numDestRegs > 0) {
6311168Sandreas.hansson@arm.com        printReg(ss, _destRegIdx[0]);
6411168Sandreas.hansson@arm.com    }
652SN/A
662SN/A    ss << ", ";
672SN/A
682SN/A    if (_numSrcRegs > 0) {
692SN/A        printReg(ss, _srcRegIdx[0]);
702SN/A        ss << ", ";
712SN/A    }
722SN/A
732SN/A    return ss.str();
742SN/A}
752SN/A
762SN/Astd::string
772SN/APredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
782SN/A{
792SN/A    std::stringstream ss;
802SN/A
812SN/A    ccprintf(ss, "%-10s ", mnemonic);
822SN/A
832SN/A    if (_numDestRegs > 0) {
842SN/A        printReg(ss, _destRegIdx[0]);
852SN/A    }
862SN/A
872SN/A    ss << ", ";
882SN/A
892SN/A    if (_numSrcRegs > 0) {
902SN/A        printReg(ss, _srcRegIdx[0]);
912SN/A        ss << ", ";
922SN/A    }
93
94    return ss.str();
95}
96
97std::string
98PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99{
100    std::stringstream ss;
101
102    ccprintf(ss, "%-10s ", mnemonic);
103
104    return ss.str();
105}
106}
107