pred_inst.cc revision 6253 
1/* Copyright (c) 2007-2008 The Florida State University
2 * All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are
6 * met: redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer;
8 * redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution;
11 * neither the name of the copyright holders nor the names of its
12 * contributors may be used to endorse or promote products derived from
13 * this software without specific prior written permission.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 *
27 * Authors: Stephen Hines
28 */
29
30#include "arch/arm/insts/pred_inst.hh"
31
32namespace ArmISA
33{
34std::string
35PredOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
36{
37    std::stringstream ss;
38
39    ccprintf(ss, "%-10s ", mnemonic);
40
41    if (_numDestRegs > 0) {
42        printReg(ss, _destRegIdx[0]);
43    }
44
45    ss << ", ";
46
47    if (_numSrcRegs > 0) {
48        printReg(ss, _srcRegIdx[0]);
49        ss << ", ";
50    }
51
52    return ss.str();
53}
54
55std::string
56PredImmOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
57{
58    std::stringstream ss;
59
60    ccprintf(ss, "%-10s ", mnemonic);
61
62    if (_numDestRegs > 0) {
63        printReg(ss, _destRegIdx[0]);
64    }
65
66    ss << ", ";
67
68    if (_numSrcRegs > 0) {
69        printReg(ss, _srcRegIdx[0]);
70        ss << ", ";
71    }
72
73    return ss.str();
74}
75
76std::string
77PredIntOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
78{
79    std::stringstream ss;
80
81    ccprintf(ss, "%-10s ", mnemonic);
82
83    if (_numDestRegs > 0) {
84        printReg(ss, _destRegIdx[0]);
85    }
86
87    ss << ", ";
88
89    if (_numSrcRegs > 0) {
90        printReg(ss, _srcRegIdx[0]);
91        ss << ", ";
92    }
93
94    return ss.str();
95}
96
97std::string
98PredMacroOp::generateDisassembly(Addr pc, const SymbolTable *symtab) const
99{
100    std::stringstream ss;
101
102    ccprintf(ss, "%-10s ", mnemonic);
103
104    return ss.str();
105}
106}
107