110037SARM gem5 Developers/* 210037SARM gem5 Developers * Copyright (c) 2012-2013 ARM Limited 310037SARM gem5 Developers * All rights reserved 410037SARM gem5 Developers * 510037SARM gem5 Developers * The license below extends only to copyright in the software and shall 610037SARM gem5 Developers * not be construed as granting a license to any other intellectual 710037SARM gem5 Developers * property including but not limited to intellectual property relating 810037SARM gem5 Developers * to a hardware implementation of the functionality of the software 910037SARM gem5 Developers * licensed hereunder. You may use the software subject to the license 1010037SARM gem5 Developers * terms below provided that you ensure that this notice is replicated 1110037SARM gem5 Developers * unmodified and in its entirety in all distributions of the software, 1210037SARM gem5 Developers * modified or unmodified, in source code or in binary form. 1310037SARM gem5 Developers * 1410037SARM gem5 Developers * Redistribution and use in source and binary forms, with or without 1510037SARM gem5 Developers * modification, are permitted provided that the following conditions are 1610037SARM gem5 Developers * met: redistributions of source code must retain the above copyright 1710037SARM gem5 Developers * notice, this list of conditions and the following disclaimer; 1810037SARM gem5 Developers * redistributions in binary form must reproduce the above copyright 1910037SARM gem5 Developers * notice, this list of conditions and the following disclaimer in the 2010037SARM gem5 Developers * documentation and/or other materials provided with the distribution; 2110037SARM gem5 Developers * neither the name of the copyright holders nor the names of its 2210037SARM gem5 Developers * contributors may be used to endorse or promote products derived from 2310037SARM gem5 Developers * this software without specific prior written permission. 2410037SARM gem5 Developers * 2510037SARM gem5 Developers * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 2610037SARM gem5 Developers * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 2710037SARM gem5 Developers * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 2810037SARM gem5 Developers * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 2910037SARM gem5 Developers * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 3010037SARM gem5 Developers * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 3110037SARM gem5 Developers * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 3210037SARM gem5 Developers * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 3310037SARM gem5 Developers * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 3410037SARM gem5 Developers * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 3510037SARM gem5 Developers * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 3610037SARM gem5 Developers * 3710037SARM gem5 Developers * Authors: Mbou Eyole 3810037SARM gem5 Developers * Giacomo Gabrielli 3910037SARM gem5 Developers */ 4010037SARM gem5 Developers 4110037SARM gem5 Developers/// @file 4210037SARM gem5 Developers/// Utility functions and datatypes used by AArch64 NEON memory instructions. 4310037SARM gem5 Developers 4410037SARM gem5 Developers#ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__ 4510037SARM gem5 Developers#define __ARCH_ARM_INSTS_NEON64_MEM_HH__ 4610037SARM gem5 Developers 4710037SARM gem5 Developersnamespace ArmISA 4810037SARM gem5 Developers{ 4910037SARM gem5 Developers 5010037SARM gem5 Developerstypedef uint64_t XReg; 5110037SARM gem5 Developers 5210037SARM gem5 Developers/// 128-bit NEON vector register. 5310037SARM gem5 Developersstruct VReg { 5410037SARM gem5 Developers XReg hi; 5510037SARM gem5 Developers XReg lo; 5610037SARM gem5 Developers}; 5710037SARM gem5 Developers 5810037SARM gem5 Developers/// Write a single NEON vector element leaving the others untouched. 5910037SARM gem5 Developersinline void 6010037SARM gem5 DeveloperswriteVecElem(VReg *dest, XReg src, int index, int eSize) 6110037SARM gem5 Developers{ 6210037SARM gem5 Developers // eSize must be less than 4: 6310037SARM gem5 Developers // 0 -> 8-bit elems, 6410037SARM gem5 Developers // 1 -> 16-bit elems, 6510037SARM gem5 Developers // 2 -> 32-bit elems, 6610037SARM gem5 Developers // 3 -> 64-bit elems 6710037SARM gem5 Developers assert(eSize <= 3); 6810037SARM gem5 Developers 6910037SARM gem5 Developers int eBits = 8 << eSize; 7010037SARM gem5 Developers int lsbPos = index * eBits; 7110037SARM gem5 Developers assert(lsbPos < 128); 7210037SARM gem5 Developers int shiftAmt = lsbPos % 64; 7310037SARM gem5 Developers 7410037SARM gem5 Developers XReg maskBits = -1; 7510037SARM gem5 Developers if (eBits == 64) { 7610037SARM gem5 Developers maskBits = 0; 7710037SARM gem5 Developers } else { 7810037SARM gem5 Developers maskBits = maskBits << eBits; 7910037SARM gem5 Developers } 8010037SARM gem5 Developers maskBits = ~maskBits; 8110037SARM gem5 Developers 8210037SARM gem5 Developers XReg sMask = maskBits; 8310037SARM gem5 Developers maskBits = sMask << shiftAmt; 8410037SARM gem5 Developers 8510037SARM gem5 Developers if (lsbPos < 64) { 8610037SARM gem5 Developers dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt); 8710037SARM gem5 Developers } else { 8810037SARM gem5 Developers dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt); 8910037SARM gem5 Developers } 9010037SARM gem5 Developers} 9110037SARM gem5 Developers 9210037SARM gem5 Developers/// Read a single NEON vector element. 9310037SARM gem5 Developersinline XReg 9410037SARM gem5 DevelopersreadVecElem(VReg src, int index, int eSize) 9510037SARM gem5 Developers{ 9610037SARM gem5 Developers // eSize must be less than 4: 9710037SARM gem5 Developers // 0 -> 8-bit elems, 9810037SARM gem5 Developers // 1 -> 16-bit elems, 9910037SARM gem5 Developers // 2 -> 32-bit elems, 10010037SARM gem5 Developers // 3 -> 64-bit elems 10110037SARM gem5 Developers assert(eSize <= 3); 10210037SARM gem5 Developers 10310037SARM gem5 Developers XReg data; 10410037SARM gem5 Developers 10510037SARM gem5 Developers int eBits = 8 << eSize; 10610037SARM gem5 Developers int lsbPos = index * eBits; 10710037SARM gem5 Developers assert(lsbPos < 128); 10810037SARM gem5 Developers int shiftAmt = lsbPos % 64; 10910037SARM gem5 Developers 11010037SARM gem5 Developers XReg maskBits = -1; 11110037SARM gem5 Developers if (eBits == 64) { 11210037SARM gem5 Developers maskBits = 0; 11310037SARM gem5 Developers } else { 11410037SARM gem5 Developers maskBits = maskBits << eBits; 11510037SARM gem5 Developers } 11610037SARM gem5 Developers maskBits = ~maskBits; 11710037SARM gem5 Developers 11810037SARM gem5 Developers if (lsbPos < 64) { 11910037SARM gem5 Developers data = (src.lo >> shiftAmt) & maskBits; 12010037SARM gem5 Developers } else { 12110037SARM gem5 Developers data = (src.hi >> shiftAmt) & maskBits; 12210037SARM gem5 Developers } 12310037SARM gem5 Developers return data; 12410037SARM gem5 Developers} 12510037SARM gem5 Developers 12610037SARM gem5 Developers} // namespace ArmISA 12710037SARM gem5 Developers 12810037SARM gem5 Developers#endif // __ARCH_ARM_INSTS_NEON64_MEM_HH__ 129