misc64.hh revision 10037:5cac77888310
1/* 2 * Copyright (c) 2011-2013 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are 16 * met: redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer; 18 * redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution; 21 * neither the name of the copyright holders nor the names of its 22 * contributors may be used to endorse or promote products derived from 23 * this software without specific prior written permission. 24 * 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 * 37 * Authors: Gabe Black 38 */ 39 40#ifndef __ARCH_ARM_INSTS_MISC64_HH__ 41#define __ARCH_ARM_INSTS_MISC64_HH__ 42 43#include "arch/arm/insts/static_inst.hh" 44 45class RegRegImmImmOp64 : public ArmStaticInst 46{ 47 protected: 48 IntRegIndex dest; 49 IntRegIndex op1; 50 uint64_t imm1; 51 uint64_t imm2; 52 53 RegRegImmImmOp64(const char *mnem, ExtMachInst _machInst, 54 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 55 uint64_t _imm1, uint64_t _imm2) : 56 ArmStaticInst(mnem, _machInst, __opClass), 57 dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2) 58 {} 59 60 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 61}; 62 63class RegRegRegImmOp64 : public ArmStaticInst 64{ 65 protected: 66 IntRegIndex dest; 67 IntRegIndex op1; 68 IntRegIndex op2; 69 uint64_t imm; 70 71 RegRegRegImmOp64(const char *mnem, ExtMachInst _machInst, 72 OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1, 73 IntRegIndex _op2, uint64_t _imm) : 74 ArmStaticInst(mnem, _machInst, __opClass), 75 dest(_dest), op1(_op1), op2(_op2), imm(_imm) 76 {} 77 78 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 79}; 80 81class UnknownOp64 : public ArmStaticInst 82{ 83 protected: 84 85 UnknownOp64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) : 86 ArmStaticInst(mnem, _machInst, __opClass) 87 {} 88 89 std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 90}; 91 92#endif 93