misc.hh revision 7232 
1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder.  You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions are
16 * met: redistributions of source code must retain the above copyright
17 * notice, this list of conditions and the following disclaimer;
18 * redistributions in binary form must reproduce the above copyright
19 * notice, this list of conditions and the following disclaimer in the
20 * documentation and/or other materials provided with the distribution;
21 * neither the name of the copyright holders nor the names of its
22 * contributors may be used to endorse or promote products derived from
23 * this software without specific prior written permission.
24 *
25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
26 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
27 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
28 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
29 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
30 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
31 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
32 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
33 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
34 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
35 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 *
37 * Authors: Gabe Black
38 */
39
40#ifndef __ARCH_ARM_INSTS_MISC_HH__
41#define __ARCH_ARM_INSTS_MISC_HH__
42
43#include "arch/arm/insts/pred_inst.hh"
44
45class MrsOp : public PredOp
46{
47  protected:
48    IntRegIndex dest;
49
50    MrsOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
51            IntRegIndex _dest) :
52        PredOp(mnem, _machInst, __opClass), dest(_dest)
53    {}
54
55    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
56};
57
58class MsrBase : public PredOp
59{
60  protected:
61    uint8_t byteMask;
62
63    MsrBase(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
64            uint8_t _byteMask) :
65        PredOp(mnem, _machInst, __opClass), byteMask(_byteMask)
66    {}
67
68    void printMsrBase(std::ostream &os) const;
69};
70
71class MsrImmOp : public MsrBase
72{
73  protected:
74    uint32_t imm;
75
76    MsrImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
77             uint32_t _imm, uint8_t _byteMask) :
78        MsrBase(mnem, _machInst, __opClass, _byteMask), imm(_imm)
79    {}
80
81    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
82};
83
84class MsrRegOp : public MsrBase
85{
86  protected:
87    IntRegIndex op1;
88
89    MsrRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
90             IntRegIndex _op1, uint8_t _byteMask) :
91        MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
92    {}
93
94    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
95};
96
97class RevOp : public PredOp
98{
99  protected:
100    IntRegIndex dest;
101    IntRegIndex op1;
102
103    RevOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
104          IntRegIndex _dest, IntRegIndex _op1) :
105        PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
106    {}
107
108    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
109};
110
111class RegImmRegOp : public PredOp
112{
113  protected:
114    IntRegIndex dest;
115    uint32_t imm;
116    IntRegIndex op1;
117
118    RegImmRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
119                IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1) :
120        PredOp(mnem, _machInst, __opClass),
121        dest(_dest), imm(_imm), op1(_op1)
122    {}
123
124    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
125};
126
127class RegImmRegShiftOp : public PredOp
128{
129  protected:
130    IntRegIndex dest;
131    uint32_t imm;
132    IntRegIndex op1;
133    int32_t shiftAmt;
134    ArmShiftType shiftType;
135
136    RegImmRegShiftOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
137                     IntRegIndex _dest, uint32_t _imm, IntRegIndex _op1,
138                     int32_t _shiftAmt, ArmShiftType _shiftType) :
139        PredOp(mnem, _machInst, __opClass),
140        dest(_dest), imm(_imm), op1(_op1),
141        shiftAmt(_shiftAmt), shiftType(_shiftType)
142    {}
143
144    std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const;
145};
146
147#endif
148