mem.hh revision 7291
12292SN/A/* 210333Smitch.hayenga@arm.com * Copyright (c) 2010 ARM Limited 39444SAndreas.Sandberg@ARM.com * All rights reserved 49444SAndreas.Sandberg@ARM.com * 59444SAndreas.Sandberg@ARM.com * The license below extends only to copyright in the software and shall 69444SAndreas.Sandberg@ARM.com * not be construed as granting a license to any other intellectual 79444SAndreas.Sandberg@ARM.com * property including but not limited to intellectual property relating 89444SAndreas.Sandberg@ARM.com * to a hardware implementation of the functionality of the software 99444SAndreas.Sandberg@ARM.com * licensed hereunder. You may use the software subject to the license 109444SAndreas.Sandberg@ARM.com * terms below provided that you ensure that this notice is replicated 119444SAndreas.Sandberg@ARM.com * unmodified and in its entirety in all distributions of the software, 129444SAndreas.Sandberg@ARM.com * modified or unmodified, in source code or in binary form. 139444SAndreas.Sandberg@ARM.com * 142329SN/A * Copyright (c) 2007-2008 The Florida State University 1510239Sbinhpham@cs.rutgers.edu * All rights reserved. 162292SN/A * 172292SN/A * Redistribution and use in source and binary forms, with or without 182292SN/A * modification, are permitted provided that the following conditions are 192292SN/A * met: redistributions of source code must retain the above copyright 202292SN/A * notice, this list of conditions and the following disclaimer; 212292SN/A * redistributions in binary form must reproduce the above copyright 222292SN/A * notice, this list of conditions and the following disclaimer in the 232292SN/A * documentation and/or other materials provided with the distribution; 242292SN/A * neither the name of the copyright holders nor the names of its 252292SN/A * contributors may be used to endorse or promote products derived from 262292SN/A * this software without specific prior written permission. 272292SN/A * 282292SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 292292SN/A * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 302292SN/A * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 312292SN/A * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 322292SN/A * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 332292SN/A * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 342292SN/A * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 352292SN/A * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 362292SN/A * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 372292SN/A * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 382292SN/A * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 392292SN/A * 402689Sktlim@umich.edu * Authors: Stephen Hines 412689Sktlim@umich.edu */ 422689Sktlim@umich.edu#ifndef __ARCH_ARM_MEM_HH__ 432292SN/A#define __ARCH_ARM_MEM_HH__ 442292SN/A 452292SN/A#include "arch/arm/insts/pred_inst.hh" 462292SN/A 472292SN/Anamespace ArmISA 482329SN/A{ 494395Ssaidi@eecs.umich.edu 502292SN/Aclass Swap : public PredOp 512292SN/A{ 522292SN/A protected: 538591Sgblack@eecs.umich.edu IntRegIndex dest; 548506Sgblack@eecs.umich.edu IntRegIndex op1; 553326Sktlim@umich.edu IntRegIndex base; 568481Sgblack@eecs.umich.edu 578229Snate@binkert.org Swap(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 586658Snate@binkert.org IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _base) 592292SN/A : PredOp(mnem, _machInst, __opClass), 608230Snate@binkert.org dest(_dest), op1(_op1), base(_base) 618232Snate@binkert.org {} 623348Sbinkertn@umich.edu 632669Sktlim@umich.edu std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 642292SN/A}; 658737Skoansin.tan@gmail.com 665529Snate@binkert.org// The address is a base register plus an immediate. 672292SN/Aclass RfeOp : public PredOp 682329SN/A{ 692329SN/A public: 702329SN/A enum AddrMode { 712329SN/A DecrementAfter, 722329SN/A DecrementBefore, 732329SN/A IncrementAfter, 742329SN/A IncrementBefore 752329SN/A }; 762329SN/A protected: 772329SN/A IntRegIndex base; 782292SN/A AddrMode mode; 792292SN/A bool wb; 802292SN/A 812292SN/A RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 822733Sktlim@umich.edu IntRegIndex _base, AddrMode _mode, bool _wb) 832292SN/A : PredOp(mnem, _machInst, __opClass), 842292SN/A base(_base), mode(_mode), wb(_wb) 852907Sktlim@umich.edu {} 862292SN/A 872292SN/A std::string generateDisassembly(Addr pc, const SymbolTable *symtab) const; 882292SN/A}; 892292SN/A 902292SN/Aclass Memory : public PredOp 912292SN/A{ 922292SN/A public: 935529Snate@binkert.org enum AddrMode { 945529Snate@binkert.org AddrMd_Offset, 955529Snate@binkert.org AddrMd_PreIndex, 962292SN/A AddrMd_PostIndex 972292SN/A }; 982292SN/A 992292SN/A protected: 1002727Sktlim@umich.edu 1012727Sktlim@umich.edu IntRegIndex dest; 1022727Sktlim@umich.edu IntRegIndex base; 1032907Sktlim@umich.edu bool add; 1048922Swilliam.wang@arm.com 1052907Sktlim@umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1069444SAndreas.Sandberg@ARM.com IntRegIndex _dest, IntRegIndex _base, bool _add) 1079444SAndreas.Sandberg@ARM.com : PredOp(mnem, _machInst, __opClass), 1082307SN/A dest(_dest), base(_base), add(_add) 1092348SN/A {} 1102307SN/A 1112307SN/A virtual void 1122292SN/A printOffset(std::ostream &os) const 1132292SN/A {} 1142292SN/A 1152292SN/A virtual void 1162292SN/A printDest(std::ostream &os) const 1172292SN/A { 1182292SN/A printReg(os, dest); 1192292SN/A } 1202292SN/A 1212292SN/A void printInst(std::ostream &os, AddrMode addrMode) const; 1222292SN/A}; 1232292SN/A 1242292SN/A// The address is a base register plus an immediate. 1252292SN/Aclass MemoryImm : public Memory 1268545Ssaidi@eecs.umich.edu{ 1278545Ssaidi@eecs.umich.edu protected: 1288545Ssaidi@eecs.umich.edu int32_t imm; 1298199SAli.Saidi@ARM.com 1308199SAli.Saidi@ARM.com MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1318199SAli.Saidi@ARM.com IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 1328199SAli.Saidi@ARM.com : Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 1338199SAli.Saidi@ARM.com {} 1348545Ssaidi@eecs.umich.edu 1358545Ssaidi@eecs.umich.edu void 1368545Ssaidi@eecs.umich.edu printOffset(std::ostream &os) const 1378545Ssaidi@eecs.umich.edu { 1388545Ssaidi@eecs.umich.edu int32_t pImm = imm; 1398545Ssaidi@eecs.umich.edu if (!add) 1402292SN/A pImm = -pImm; 1412292SN/A ccprintf(os, "#%d", pImm); 1422292SN/A } 1432329SN/A}; 1442292SN/A 1452292SN/A// The address is a base register plus an immediate. 1462292SN/Aclass MemoryDImm : public MemoryImm 1472292SN/A{ 1482292SN/A protected: 1492292SN/A IntRegIndex dest2; 1502292SN/A 1512292SN/A MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1522292SN/A IntRegIndex _dest, IntRegIndex _dest2, 1532292SN/A IntRegIndex _base, bool _add, int32_t _imm) 1542292SN/A : MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm), 1552292SN/A dest2(_dest2) 1562292SN/A {} 1572292SN/A 1582790Sktlim@umich.edu void 1592790Sktlim@umich.edu printDest(std::ostream &os) const 1602669Sktlim@umich.edu { 1612669Sktlim@umich.edu MemoryImm::printDest(os); 1622292SN/A os << ", "; 1632292SN/A printReg(os, dest2); 1642292SN/A } 1652292SN/A}; 1662292SN/A 1672292SN/A// The address is a shifted register plus an immediate 1682292SN/Aclass MemoryReg : public Memory 1692292SN/A{ 1702292SN/A protected: 1712292SN/A int32_t shiftAmt; 1722292SN/A ArmShiftType shiftType; 1732292SN/A IntRegIndex index; 1742292SN/A 1752292SN/A MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1762292SN/A IntRegIndex _dest, IntRegIndex _base, bool _add, 1772292SN/A int32_t _shiftAmt, ArmShiftType _shiftType, 1782292SN/A IntRegIndex _index) 1792292SN/A : Memory(mnem, _machInst, __opClass, _dest, _base, _add), 1802292SN/A shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 1812292SN/A {} 1822292SN/A 1832292SN/A void 1842292SN/A printOffset(std::ostream &os) const 18510239Sbinhpham@cs.rutgers.edu { 18610239Sbinhpham@cs.rutgers.edu if (!add) 18710239Sbinhpham@cs.rutgers.edu os << "-"; 18810239Sbinhpham@cs.rutgers.edu printReg(os, index); 18910239Sbinhpham@cs.rutgers.edu if (shiftType != LSL || shiftAmt != 0) { 1902292SN/A switch (shiftType) { 1912292SN/A case LSL: 1922292SN/A ccprintf(os, " LSL #%d", shiftAmt); 1932292SN/A break; 1942292SN/A case LSR: 1952292SN/A if (shiftAmt == 0) { 1962292SN/A ccprintf(os, " LSR #%d", 32); 1972292SN/A } else { 1982292SN/A ccprintf(os, " LSR #%d", shiftAmt); 1992292SN/A } 2009444SAndreas.Sandberg@ARM.com break; 2019444SAndreas.Sandberg@ARM.com case ASR: 2029444SAndreas.Sandberg@ARM.com if (shiftAmt == 0) { 2032292SN/A ccprintf(os, " ASR #%d", 32); 2042292SN/A } else { 2052292SN/A ccprintf(os, " ASR #%d", shiftAmt); 2062292SN/A } 2072292SN/A break; 2082292SN/A case ROR: 2099444SAndreas.Sandberg@ARM.com if (shiftAmt == 0) { 2109444SAndreas.Sandberg@ARM.com ccprintf(os, " RRX"); 2119444SAndreas.Sandberg@ARM.com } else { 2129444SAndreas.Sandberg@ARM.com ccprintf(os, " ROR #%d", shiftAmt); 2139444SAndreas.Sandberg@ARM.com } 2149444SAndreas.Sandberg@ARM.com break; 2152292SN/A } 2162292SN/A } 2172292SN/A } 2182292SN/A}; 2192292SN/A 2202292SN/Aclass MemoryDReg : public MemoryReg 2212292SN/A{ 2222292SN/A protected: 2232292SN/A IntRegIndex dest2; 2242292SN/A 2252292SN/A MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 2262678Sktlim@umich.edu IntRegIndex _dest, IntRegIndex _dest2, 2272678Sktlim@umich.edu IntRegIndex _base, bool _add, 2282292SN/A int32_t _shiftAmt, ArmShiftType _shiftType, 2292907Sktlim@umich.edu IntRegIndex _index) 2302907Sktlim@umich.edu : MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add, 2312907Sktlim@umich.edu _shiftAmt, _shiftType, _index), 2322292SN/A dest2(_dest2) 2339444SAndreas.Sandberg@ARM.com {} 2349444SAndreas.Sandberg@ARM.com 2359444SAndreas.Sandberg@ARM.com void 2362698Sktlim@umich.edu printDest(std::ostream &os) const 2372678Sktlim@umich.edu { 2382678Sktlim@umich.edu MemoryReg::printDest(os); 2396974Stjones1@inf.ed.ac.uk os << ", "; 2406974Stjones1@inf.ed.ac.uk printReg(os, dest2); 2416974Stjones1@inf.ed.ac.uk } 2422698Sktlim@umich.edu}; 2433349Sbinkertn@umich.edu 2442693Sktlim@umich.edutemplate<class Base> 2452292SN/Aclass MemoryOffset : public Base 2462292SN/A{ 2472292SN/A protected: 2486974Stjones1@inf.ed.ac.uk MemoryOffset(const char *mnem, ExtMachInst _machInst, 2496974Stjones1@inf.ed.ac.uk OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2506974Stjones1@inf.ed.ac.uk bool _add, int32_t _imm) 2512292SN/A : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 2529440SAndreas.Sandberg@ARM.com {} 2532292SN/A 2549440SAndreas.Sandberg@ARM.com MemoryOffset(const char *mnem, ExtMachInst _machInst, 2552292SN/A OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2569440SAndreas.Sandberg@ARM.com bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 2572292SN/A IntRegIndex _index) 2589440SAndreas.Sandberg@ARM.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, 2592292SN/A _shiftAmt, _shiftType, _index) 2602329SN/A {} 2612329SN/A 2629440SAndreas.Sandberg@ARM.com MemoryOffset(const char *mnem, ExtMachInst _machInst, 2632329SN/A OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 2642292SN/A IntRegIndex _base, bool _add, int32_t _imm) 2652292SN/A : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 2662733Sktlim@umich.edu {} 2672292SN/A 2682292SN/A MemoryOffset(const char *mnem, ExtMachInst _machInst, 2692292SN/A OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 2702292SN/A IntRegIndex _base, bool _add, 2712907Sktlim@umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 2722907Sktlim@umich.edu IntRegIndex _index) 2732669Sktlim@umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 2742907Sktlim@umich.edu _shiftAmt, _shiftType, _index) 2758922Swilliam.wang@arm.com {} 2762292SN/A 2772698Sktlim@umich.edu std::string 2789044SAli.Saidi@ARM.com generateDisassembly(Addr pc, const SymbolTable *symtab) const 2792678Sktlim@umich.edu { 2802678Sktlim@umich.edu std::stringstream ss; 2812698Sktlim@umich.edu this->printInst(ss, Memory::AddrMd_Offset); 2822678Sktlim@umich.edu return ss.str(); 28310537Sandreas.hansson@arm.com } 28410537Sandreas.hansson@arm.com}; 28510537Sandreas.hansson@arm.com 2869046SAli.Saidi@ARM.comtemplate<class Base> 2872678Sktlim@umich.educlass MemoryPreIndex : public Base 2882698Sktlim@umich.edu{ 2892678Sktlim@umich.edu protected: 2909046SAli.Saidi@ARM.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 2919046SAli.Saidi@ARM.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2929046SAli.Saidi@ARM.com bool _add, int32_t _imm) 2939046SAli.Saidi@ARM.com : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 2949046SAli.Saidi@ARM.com {} 2959046SAli.Saidi@ARM.com 2969046SAli.Saidi@ARM.com MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 2979046SAli.Saidi@ARM.com OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2982698Sktlim@umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 2992678Sktlim@umich.edu IntRegIndex _index) 3002698Sktlim@umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3012678Sktlim@umich.edu _shiftAmt, _shiftType, _index) 3026974Stjones1@inf.ed.ac.uk {} 3036974Stjones1@inf.ed.ac.uk 3046974Stjones1@inf.ed.ac.uk MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3056974Stjones1@inf.ed.ac.uk OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 30610333Smitch.hayenga@arm.com IntRegIndex _base, bool _add, int32_t _imm) 30710333Smitch.hayenga@arm.com : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3086974Stjones1@inf.ed.ac.uk {} 3096974Stjones1@inf.ed.ac.uk 3106974Stjones1@inf.ed.ac.uk MemoryPreIndex(const char *mnem, ExtMachInst _machInst, 3112678Sktlim@umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3122678Sktlim@umich.edu IntRegIndex _base, bool _add, 3132698Sktlim@umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3142678Sktlim@umich.edu IntRegIndex _index) 3152678Sktlim@umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3162678Sktlim@umich.edu _shiftAmt, _shiftType, _index) 3172678Sktlim@umich.edu {} 3182678Sktlim@umich.edu 3192678Sktlim@umich.edu std::string 3202678Sktlim@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3212678Sktlim@umich.edu { 3222678Sktlim@umich.edu std::stringstream ss; 3235336Shines@cs.fsu.edu this->printInst(ss, Memory::AddrMd_PreIndex); 3242678Sktlim@umich.edu return ss.str(); 3252678Sktlim@umich.edu } 3262698Sktlim@umich.edu}; 3272678Sktlim@umich.edu 3282678Sktlim@umich.edutemplate<class Base> 3292698Sktlim@umich.educlass MemoryPostIndex : public Base 3302678Sktlim@umich.edu{ 3312678Sktlim@umich.edu protected: 3322678Sktlim@umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3332678Sktlim@umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3342678Sktlim@umich.edu bool _add, int32_t _imm) 3352678Sktlim@umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 3362292SN/A {} 3372292SN/A 3382292SN/A MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3392292SN/A OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 3404326Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 3412292SN/A IntRegIndex _index) 3424326Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 3434395Ssaidi@eecs.umich.edu _shiftAmt, _shiftType, _index) 3444326Sgblack@eecs.umich.edu {} 3452292SN/A 3469152Satgutier@umich.edu MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3479152Satgutier@umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 3489152Satgutier@umich.edu IntRegIndex _base, bool _add, int32_t _imm) 3499152Satgutier@umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm) 3509152Satgutier@umich.edu {} 3512292SN/A 3522292SN/A MemoryPostIndex(const char *mnem, ExtMachInst _machInst, 3536974Stjones1@inf.ed.ac.uk OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2, 35410031SAli.Saidi@ARM.com IntRegIndex _base, bool _add, 3554326Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 3564395Ssaidi@eecs.umich.edu IntRegIndex _index) 3574326Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, 3589046SAli.Saidi@ARM.com _shiftAmt, _shiftType, _index) 3599046SAli.Saidi@ARM.com {} 3602292SN/A 3612292SN/A std::string 3622669Sktlim@umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 3632669Sktlim@umich.edu { 3646974Stjones1@inf.ed.ac.uk std::stringstream ss; 3656974Stjones1@inf.ed.ac.uk this->printInst(ss, Memory::AddrMd_PostIndex); 3666974Stjones1@inf.ed.ac.uk return ss.str(); 3672292SN/A } 3689046SAli.Saidi@ARM.com}; 3696974Stjones1@inf.ed.ac.uk} 3706974Stjones1@inf.ed.ac.uk 3712292SN/A#endif //__ARCH_ARM_INSTS_MEM_HH__ 3722292SN/A