mem.hh revision 7118
17118Sgblack@eecs.umich.edu/* 27118Sgblack@eecs.umich.edu * Copyright (c) 2010 ARM Limited 37118Sgblack@eecs.umich.edu * All rights reserved 47118Sgblack@eecs.umich.edu * 57118Sgblack@eecs.umich.edu * The license below extends only to copyright in the software and shall 67118Sgblack@eecs.umich.edu * not be construed as granting a license to any other intellectual 77118Sgblack@eecs.umich.edu * property including but not limited to intellectual property relating 87118Sgblack@eecs.umich.edu * to a hardware implementation of the functionality of the software 97118Sgblack@eecs.umich.edu * licensed hereunder. You may use the software subject to the license 107118Sgblack@eecs.umich.edu * terms below provided that you ensure that this notice is replicated 117118Sgblack@eecs.umich.edu * unmodified and in its entirety in all distributions of the software, 127118Sgblack@eecs.umich.edu * modified or unmodified, in source code or in binary form. 137118Sgblack@eecs.umich.edu * 147118Sgblack@eecs.umich.edu * Copyright (c) 2007-2008 The Florida State University 156253Sgblack@eecs.umich.edu * All rights reserved. 166253Sgblack@eecs.umich.edu * 176253Sgblack@eecs.umich.edu * Redistribution and use in source and binary forms, with or without 186253Sgblack@eecs.umich.edu * modification, are permitted provided that the following conditions are 196253Sgblack@eecs.umich.edu * met: redistributions of source code must retain the above copyright 206253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer; 216253Sgblack@eecs.umich.edu * redistributions in binary form must reproduce the above copyright 226253Sgblack@eecs.umich.edu * notice, this list of conditions and the following disclaimer in the 236253Sgblack@eecs.umich.edu * documentation and/or other materials provided with the distribution; 246253Sgblack@eecs.umich.edu * neither the name of the copyright holders nor the names of its 256253Sgblack@eecs.umich.edu * contributors may be used to endorse or promote products derived from 266253Sgblack@eecs.umich.edu * this software without specific prior written permission. 276253Sgblack@eecs.umich.edu * 286253Sgblack@eecs.umich.edu * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 296253Sgblack@eecs.umich.edu * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 306253Sgblack@eecs.umich.edu * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 316253Sgblack@eecs.umich.edu * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 326253Sgblack@eecs.umich.edu * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 336253Sgblack@eecs.umich.edu * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 346253Sgblack@eecs.umich.edu * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 356253Sgblack@eecs.umich.edu * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 366253Sgblack@eecs.umich.edu * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 376253Sgblack@eecs.umich.edu * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 386253Sgblack@eecs.umich.edu * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 396253Sgblack@eecs.umich.edu * 406253Sgblack@eecs.umich.edu * Authors: Stephen Hines 416253Sgblack@eecs.umich.edu */ 426253Sgblack@eecs.umich.edu#ifndef __ARCH_ARM_MEM_HH__ 436253Sgblack@eecs.umich.edu#define __ARCH_ARM_MEM_HH__ 446253Sgblack@eecs.umich.edu 456253Sgblack@eecs.umich.edu#include "arch/arm/insts/pred_inst.hh" 466253Sgblack@eecs.umich.edu 476253Sgblack@eecs.umich.edunamespace ArmISA 486253Sgblack@eecs.umich.edu{ 497118Sgblack@eecs.umich.edu 507118Sgblack@eecs.umich.educlass MemoryNew : public PredOp 517118Sgblack@eecs.umich.edu{ 527118Sgblack@eecs.umich.edu public: 537118Sgblack@eecs.umich.edu enum AddrMode { 547118Sgblack@eecs.umich.edu AddrMd_Offset, 557118Sgblack@eecs.umich.edu AddrMd_PreIndex, 567118Sgblack@eecs.umich.edu AddrMd_PostIndex 577118Sgblack@eecs.umich.edu }; 587118Sgblack@eecs.umich.edu 597118Sgblack@eecs.umich.edu protected: 607118Sgblack@eecs.umich.edu 617118Sgblack@eecs.umich.edu IntRegIndex dest; 627118Sgblack@eecs.umich.edu IntRegIndex base; 637118Sgblack@eecs.umich.edu bool add; 647118Sgblack@eecs.umich.edu 657118Sgblack@eecs.umich.edu MemoryNew(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 667118Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add) 677118Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 687118Sgblack@eecs.umich.edu dest(_dest), base(_base), add(_add) 697118Sgblack@eecs.umich.edu {} 707118Sgblack@eecs.umich.edu 717118Sgblack@eecs.umich.edu virtual void 727118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 737118Sgblack@eecs.umich.edu {} 747118Sgblack@eecs.umich.edu 757118Sgblack@eecs.umich.edu void printInst(std::ostream &os, AddrMode addrMode) const; 767118Sgblack@eecs.umich.edu}; 777118Sgblack@eecs.umich.edu 787118Sgblack@eecs.umich.edu// The address is a base register plus an immediate. 797118Sgblack@eecs.umich.educlass MemoryNewImm : public MemoryNew 807118Sgblack@eecs.umich.edu{ 817118Sgblack@eecs.umich.edu protected: 827118Sgblack@eecs.umich.edu int32_t imm; 837118Sgblack@eecs.umich.edu 847118Sgblack@eecs.umich.edu MemoryNewImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 857118Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm) 867118Sgblack@eecs.umich.edu : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm) 877118Sgblack@eecs.umich.edu {} 887118Sgblack@eecs.umich.edu 897118Sgblack@eecs.umich.edu void 907118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 917118Sgblack@eecs.umich.edu { 927118Sgblack@eecs.umich.edu int32_t pImm = imm; 937118Sgblack@eecs.umich.edu if (!add) 947118Sgblack@eecs.umich.edu pImm = -pImm; 957118Sgblack@eecs.umich.edu ccprintf(os, "#%d", pImm); 967118Sgblack@eecs.umich.edu } 977118Sgblack@eecs.umich.edu}; 987118Sgblack@eecs.umich.edu 997118Sgblack@eecs.umich.edu// The address is a shifted register plus an immediate 1007118Sgblack@eecs.umich.educlass MemoryNewReg : public MemoryNew 1017118Sgblack@eecs.umich.edu{ 1027118Sgblack@eecs.umich.edu protected: 1037118Sgblack@eecs.umich.edu int32_t shiftAmt; 1047118Sgblack@eecs.umich.edu ArmShiftType shiftType; 1057118Sgblack@eecs.umich.edu IntRegIndex index; 1067118Sgblack@eecs.umich.edu 1077118Sgblack@eecs.umich.edu MemoryNewReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass, 1087118Sgblack@eecs.umich.edu IntRegIndex _dest, IntRegIndex _base, bool _add, 1097118Sgblack@eecs.umich.edu int32_t _shiftAmt, ArmShiftType _shiftType, 1107118Sgblack@eecs.umich.edu IntRegIndex _index) 1117118Sgblack@eecs.umich.edu : MemoryNew(mnem, _machInst, __opClass, _dest, _base, _add), 1127118Sgblack@eecs.umich.edu shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index) 1137118Sgblack@eecs.umich.edu {} 1147118Sgblack@eecs.umich.edu 1157118Sgblack@eecs.umich.edu void 1167118Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 1177118Sgblack@eecs.umich.edu { 1187118Sgblack@eecs.umich.edu if (!add) 1197118Sgblack@eecs.umich.edu os << "-"; 1207118Sgblack@eecs.umich.edu printReg(os, index); 1217118Sgblack@eecs.umich.edu if (shiftType != LSL || shiftAmt != 0) { 1227118Sgblack@eecs.umich.edu switch (shiftType) { 1237118Sgblack@eecs.umich.edu case LSL: 1247118Sgblack@eecs.umich.edu ccprintf(os, " LSL #%d", shiftAmt); 1257118Sgblack@eecs.umich.edu break; 1267118Sgblack@eecs.umich.edu case LSR: 1277118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 1287118Sgblack@eecs.umich.edu ccprintf(os, " LSR #%d", 32); 1297118Sgblack@eecs.umich.edu } else { 1307118Sgblack@eecs.umich.edu ccprintf(os, " LSR #%d", shiftAmt); 1317118Sgblack@eecs.umich.edu } 1327118Sgblack@eecs.umich.edu break; 1337118Sgblack@eecs.umich.edu case ASR: 1347118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 1357118Sgblack@eecs.umich.edu ccprintf(os, " ASR #%d", 32); 1367118Sgblack@eecs.umich.edu } else { 1377118Sgblack@eecs.umich.edu ccprintf(os, " ASR #%d", shiftAmt); 1387118Sgblack@eecs.umich.edu } 1397118Sgblack@eecs.umich.edu break; 1407118Sgblack@eecs.umich.edu case ROR: 1417118Sgblack@eecs.umich.edu if (shiftAmt == 0) { 1427118Sgblack@eecs.umich.edu ccprintf(os, " RRX"); 1437118Sgblack@eecs.umich.edu } else { 1447118Sgblack@eecs.umich.edu ccprintf(os, " ROR #%d", shiftAmt); 1457118Sgblack@eecs.umich.edu } 1467118Sgblack@eecs.umich.edu break; 1477118Sgblack@eecs.umich.edu } 1487118Sgblack@eecs.umich.edu } 1497118Sgblack@eecs.umich.edu } 1507118Sgblack@eecs.umich.edu}; 1517118Sgblack@eecs.umich.edu 1527118Sgblack@eecs.umich.edutemplate<class Base> 1537118Sgblack@eecs.umich.educlass MemoryNewOffset : public Base 1547118Sgblack@eecs.umich.edu{ 1557118Sgblack@eecs.umich.edu protected: 1567118Sgblack@eecs.umich.edu MemoryNewOffset(const char *mnem, ExtMachInst _machInst, 1577118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 1587118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 1597118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 1607118Sgblack@eecs.umich.edu {} 1617118Sgblack@eecs.umich.edu 1627118Sgblack@eecs.umich.edu MemoryNewOffset(const char *mnem, ExtMachInst _machInst, 1637118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 1647118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 1657118Sgblack@eecs.umich.edu IntRegIndex _index) 1667118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 1677118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 1687118Sgblack@eecs.umich.edu {} 1697118Sgblack@eecs.umich.edu 1707118Sgblack@eecs.umich.edu std::string 1717118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 1727118Sgblack@eecs.umich.edu { 1737118Sgblack@eecs.umich.edu std::stringstream ss; 1747118Sgblack@eecs.umich.edu this->printInst(ss, MemoryNew::AddrMd_Offset); 1757118Sgblack@eecs.umich.edu return ss.str(); 1767118Sgblack@eecs.umich.edu } 1777118Sgblack@eecs.umich.edu}; 1787118Sgblack@eecs.umich.edu 1797118Sgblack@eecs.umich.edutemplate<class Base> 1807118Sgblack@eecs.umich.educlass MemoryNewPreIndex : public Base 1817118Sgblack@eecs.umich.edu{ 1827118Sgblack@eecs.umich.edu protected: 1837118Sgblack@eecs.umich.edu MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst, 1847118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 1857118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 1867118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 1877118Sgblack@eecs.umich.edu {} 1887118Sgblack@eecs.umich.edu 1897118Sgblack@eecs.umich.edu MemoryNewPreIndex(const char *mnem, ExtMachInst _machInst, 1907118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 1917118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 1927118Sgblack@eecs.umich.edu IntRegIndex _index) 1937118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 1947118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 1957118Sgblack@eecs.umich.edu {} 1967118Sgblack@eecs.umich.edu 1977118Sgblack@eecs.umich.edu std::string 1987118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 1997118Sgblack@eecs.umich.edu { 2007118Sgblack@eecs.umich.edu std::stringstream ss; 2017118Sgblack@eecs.umich.edu this->printInst(ss, MemoryNew::AddrMd_PreIndex); 2027118Sgblack@eecs.umich.edu return ss.str(); 2037118Sgblack@eecs.umich.edu } 2047118Sgblack@eecs.umich.edu}; 2057118Sgblack@eecs.umich.edu 2067118Sgblack@eecs.umich.edutemplate<class Base> 2077118Sgblack@eecs.umich.educlass MemoryNewPostIndex : public Base 2087118Sgblack@eecs.umich.edu{ 2097118Sgblack@eecs.umich.edu protected: 2107118Sgblack@eecs.umich.edu MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst, 2117118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2127118Sgblack@eecs.umich.edu bool _add, int32_t _imm) 2137118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm) 2147118Sgblack@eecs.umich.edu {} 2157118Sgblack@eecs.umich.edu 2167118Sgblack@eecs.umich.edu MemoryNewPostIndex(const char *mnem, ExtMachInst _machInst, 2177118Sgblack@eecs.umich.edu OpClass __opClass, IntRegIndex _dest, IntRegIndex _base, 2187118Sgblack@eecs.umich.edu bool _add, int32_t _shiftAmt, ArmShiftType _shiftType, 2197118Sgblack@eecs.umich.edu IntRegIndex _index) 2207118Sgblack@eecs.umich.edu : Base(mnem, _machInst, __opClass, _dest, _base, _add, 2217118Sgblack@eecs.umich.edu _shiftAmt, _shiftType, _index) 2227118Sgblack@eecs.umich.edu {} 2237118Sgblack@eecs.umich.edu 2247118Sgblack@eecs.umich.edu std::string 2257118Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const 2267118Sgblack@eecs.umich.edu { 2277118Sgblack@eecs.umich.edu std::stringstream ss; 2287118Sgblack@eecs.umich.edu this->printInst(ss, MemoryNew::AddrMd_PostIndex); 2297118Sgblack@eecs.umich.edu return ss.str(); 2307118Sgblack@eecs.umich.edu } 2317118Sgblack@eecs.umich.edu}; 2327118Sgblack@eecs.umich.edu 2336253Sgblack@eecs.umich.edu/** 2346253Sgblack@eecs.umich.edu * Base class for general Arm memory-format instructions. 2356253Sgblack@eecs.umich.edu */ 2366253Sgblack@eecs.umich.educlass Memory : public PredOp 2376253Sgblack@eecs.umich.edu{ 2386253Sgblack@eecs.umich.edu protected: 2396253Sgblack@eecs.umich.edu 2406253Sgblack@eecs.umich.edu /// Memory request flags. See mem_req_base.hh. 2416253Sgblack@eecs.umich.edu unsigned memAccessFlags; 2426253Sgblack@eecs.umich.edu 2436253Sgblack@eecs.umich.edu /// Displacement for EA calculation (signed). 2446253Sgblack@eecs.umich.edu int32_t disp; 2456253Sgblack@eecs.umich.edu int32_t disp8; 2466253Sgblack@eecs.umich.edu int32_t up; 2476253Sgblack@eecs.umich.edu int32_t hilo, 2486253Sgblack@eecs.umich.edu shift_size, 2496253Sgblack@eecs.umich.edu shift; 2506253Sgblack@eecs.umich.edu 2516253Sgblack@eecs.umich.edu /// Constructor 2526305Sgblack@eecs.umich.edu Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 2536253Sgblack@eecs.umich.edu : PredOp(mnem, _machInst, __opClass), 2546253Sgblack@eecs.umich.edu memAccessFlags(0), 2556253Sgblack@eecs.umich.edu disp(machInst.immed11_0), 2566253Sgblack@eecs.umich.edu disp8(machInst.immed7_0 << 2), 2576253Sgblack@eecs.umich.edu up(machInst.puswl.up), 2586253Sgblack@eecs.umich.edu hilo((machInst.immedHi11_8 << 4) | machInst.immedLo3_0), 2596253Sgblack@eecs.umich.edu shift_size(machInst.shiftSize), shift(machInst.shift) 2606253Sgblack@eecs.umich.edu { 2616253Sgblack@eecs.umich.edu } 2626253Sgblack@eecs.umich.edu 2636253Sgblack@eecs.umich.edu std::string 2646253Sgblack@eecs.umich.edu generateDisassembly(Addr pc, const SymbolTable *symtab) const; 2656307Sgblack@eecs.umich.edu 2666307Sgblack@eecs.umich.edu virtual void 2676307Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2686307Sgblack@eecs.umich.edu {} 2696253Sgblack@eecs.umich.edu}; 2706253Sgblack@eecs.umich.edu 2716307Sgblack@eecs.umich.educlass MemoryDisp : public Memory 2726253Sgblack@eecs.umich.edu{ 2736253Sgblack@eecs.umich.edu protected: 2746253Sgblack@eecs.umich.edu /// Constructor 2756307Sgblack@eecs.umich.edu MemoryDisp(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 2766305Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass) 2776253Sgblack@eecs.umich.edu { 2786253Sgblack@eecs.umich.edu } 2796253Sgblack@eecs.umich.edu 2806307Sgblack@eecs.umich.edu void 2816307Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2826307Sgblack@eecs.umich.edu { 2836307Sgblack@eecs.umich.edu ccprintf(os, "#%#x", (machInst.puswl.up ? disp : -disp)); 2846307Sgblack@eecs.umich.edu } 2856307Sgblack@eecs.umich.edu}; 2866307Sgblack@eecs.umich.edu 2876307Sgblack@eecs.umich.educlass MemoryHilo : public Memory 2886307Sgblack@eecs.umich.edu{ 2896307Sgblack@eecs.umich.edu protected: 2906307Sgblack@eecs.umich.edu /// Constructor 2916307Sgblack@eecs.umich.edu MemoryHilo(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 2926307Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass) 2936307Sgblack@eecs.umich.edu { 2946307Sgblack@eecs.umich.edu } 2956307Sgblack@eecs.umich.edu 2966307Sgblack@eecs.umich.edu void 2976307Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 2986307Sgblack@eecs.umich.edu { 2996307Sgblack@eecs.umich.edu ccprintf(os, "#%#x", (machInst.puswl.up ? hilo : -hilo)); 3006307Sgblack@eecs.umich.edu } 3016307Sgblack@eecs.umich.edu}; 3026307Sgblack@eecs.umich.edu 3036307Sgblack@eecs.umich.educlass MemoryShift : public Memory 3046307Sgblack@eecs.umich.edu{ 3056307Sgblack@eecs.umich.edu protected: 3066307Sgblack@eecs.umich.edu /// Constructor 3076307Sgblack@eecs.umich.edu MemoryShift(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 3086307Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass) 3096307Sgblack@eecs.umich.edu { 3106307Sgblack@eecs.umich.edu } 3116307Sgblack@eecs.umich.edu 3126307Sgblack@eecs.umich.edu void 3136307Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 3146307Sgblack@eecs.umich.edu { 3156307Sgblack@eecs.umich.edu printShiftOperand(os); 3166307Sgblack@eecs.umich.edu } 3176307Sgblack@eecs.umich.edu}; 3186307Sgblack@eecs.umich.edu 3196307Sgblack@eecs.umich.educlass MemoryReg : public Memory 3206307Sgblack@eecs.umich.edu{ 3216307Sgblack@eecs.umich.edu protected: 3226307Sgblack@eecs.umich.edu /// Constructor 3236307Sgblack@eecs.umich.edu MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass) 3246307Sgblack@eecs.umich.edu : Memory(mnem, _machInst, __opClass) 3256307Sgblack@eecs.umich.edu { 3266307Sgblack@eecs.umich.edu } 3276307Sgblack@eecs.umich.edu 3286307Sgblack@eecs.umich.edu void 3296307Sgblack@eecs.umich.edu printOffset(std::ostream &os) const 3306307Sgblack@eecs.umich.edu { 3316307Sgblack@eecs.umich.edu os << (machInst.puswl.up ? "+ " : "- "); 3326307Sgblack@eecs.umich.edu printReg(os, machInst.rm); 3336307Sgblack@eecs.umich.edu } 3346253Sgblack@eecs.umich.edu}; 3356253Sgblack@eecs.umich.edu} 3366253Sgblack@eecs.umich.edu 3376253Sgblack@eecs.umich.edu#endif //__ARCH_ARM_INSTS_MEM_HH__ 338